JP4596243B2 - Signal output device and video display device - Google Patents

Description

  The present invention relates to a signal output device to a capacitive load including an image display element or the like, and a video display device using the signal output device, in which the number of constituent elements is reduced, the voltage is increased, the processing speed is increased, and the power consumption The present invention relates to a technique for realizing reduction and the like.

  An image display device such as a projection display device includes, for example, a spatial light modulator using a liquid crystal panel or DMD (Digital Micromirror Device: manufactured by Texas Instruments Incorporated), and an optical system including a projection lens. A configuration is known in which an image is projected on a front screen. In recent years, as a one-dimensional spatial modulation type light modulation element, a grating light valve (hereinafter referred to as “GLV”) developed by Silicon Light Machine (SLM) of the United States has attracted attention. Yes. The GLV element is a diffraction grating spatial modulator having a ribbon structure that can be modulated using a Coulomb attractive force generated by application of a voltage.

  For example, when a voltage averaging method is used, a plurality of level signals are used in a driving circuit of a liquid crystal display element. For this purpose, voltage dividing means using a series-connected voltage dividing resistor group and a voltage dividing output are taken out. There is known a configuration including a drive circuit (driver) including a voltage gradation selector (see, for example, Patent Document 1).

  Examples of the configuration in the case of driving a load capacitance such as a liquid crystal display element or a GLV element include the configuration described below.

(I) A mode in which a voltage signal having a small amplitude is amplified and supplied to a load capacitor (see FIG. 8).
(II) A mode in which a current signal is passed through a resistor to generate a voltage and this is supplied to a load capacitor (see FIG. 9).

  First, in the above form (I), for example, as shown in FIG. 8, a voltage control circuit a having a small dynamic range is provided, and the output is amplified by an amplifier b to drive a load capacitance (or capacitive load) c. To do. Note that “HVDD” shown in the figure indicates the power supply voltage supplied to the amplifier b.

  In the above-described form (II), for example, as shown in FIG. 9, one end of the resistor d is connected to the power line e of “HVDD” and the other end of the resistor d is connected to the current amount control circuit f and the load. The capacitor c is connected. The current amount control circuit f controls a current (referred to as “I”) that flows through the resistor d. When the resistance value of the resistor d is denoted as “R” and the voltage applied to the load capacitor c is denoted as “V”, the relationship “V = HVDD−R · I” is obtained. Thus, the drive voltage of the load capacity c can be controlled.

JP 54-5399 A

  However, the conventional circuit configuration has various problems with respect to the number of constituent elements, high voltage, processing speed, power consumption, and the like.

  For example, in a configuration including a selector for outputting a plurality of voltages according to the number of gradations, when an FET (field effect transistor) is required, the number of FETs increases as the number of gradations increases, and the configuration Problems such as increasing complexity. In particular, when the output voltage is high, a high breakdown voltage FET with a large occupation area is required, and a wide arrangement space must be ensured. Further, since a high voltage control signal is required to control the high voltage FET, noise generated by the control signal is a problem. In addition, in a configuration using a DAC (digital-analog converter) based on resistance voltage division, the parasitic capacitance of the resistor and the output switching element (FET) is large, which hinders the speeding up of the operation. When the number of output channels is increased, the number of DACs is increased accordingly. This increases the occupied area, which leads to an increase in circuit scale.

  Further, regarding the processing speed and power consumption, for example, in the above-described form (I), it is difficult to change the output signal at high speed because the output amplitude of the amplifier b in FIG. Therefore, the problem is that the power consumption of the amplifier increases.

  In the above-mentioned form (II), since a current is always passed through the resistor d in FIG. 9, the power consumption increases.

  Therefore, an object of the present invention is to provide a circuit configuration suitable for feeding control of a capacitive load.

In order to solve the above-described problem, the signal output device of the present invention includes a resistor and a current control device for controlling a current flowing through the resistor, and a signal output device for supplying a supply current to the capacitive load . First switch means connected in series to the capacitive load; second switch means connected in series to the resistor and connected between the resistor and the current control device; and Control means for controlling the open / closed state of the first switch means and the second switch means, the potential of the connection point of the resistor and the first switch means, the first switch means and the capacitive load Detecting means for detecting a potential difference between the first switch means and the second switch means, and one end of the resistor connected to each other. Switch means Provided between the resistor and the capacitive load, wherein the first switch means includes a closed state for supplying a supply current to the capacitive load and an open state for interrupting the supply current to the capacitive load. The second switch means is switched between a closed state in which a current controlled by the current control device flows to the resistor and an open state in which the current is interrupted, and the first switch means When the second switch means is closed, the current control device defines a current that flows through the resistor, the supply current is supplied to the capacitive load, and a potential difference detected by the detection means The first and second switch means are defined to be in an open state when a predetermined value or less is reached .

  Therefore, in the present invention, since the power is supplied to the capacitive load only when the first switch means is closed, the power consumption can be reduced. Further, in a relatively simple circuit configuration using the resistor, the first and second switch means, and the current control device, the current flowing through the resistor is defined when the second switch means is closed, and the number of gradations is increased. (Even when the number of gradations increases, there is no increase in voltage dividing resistors, switching elements, etc. in the high voltage output portion).

  According to the present invention, it is possible to simplify the circuit configuration for power supply control to the capacitive load, and to reduce the circuit scale and reduce the power consumption.

The present invention includes a resistor and a current control device for controlling a current flowing through the resistor, and is connected in series to the capacitive load in a signal output device for supplying a supply current to the capacitive load. A first switch means, a second switch means connected in series with the resistor and connected between the resistor and the current control device, and the first switch means and the second switch means. Detects a potential difference between the control means for controlling the open / close state, the potential at the connection point of the resistor and the first switch means, and the potential at the connection point of the first switch means and the capacitive load Detecting means for performing the operation, a connection point of the first switch means and the second switch means and one end of the resistor are connected, and the first switch means includes the resistor and the capacitive load. Between The first switch means is switched between a closed state in which a supply current is supplied to the capacitive load and an open state in which the supply current to the capacitive load is cut off. It is switched between a closed state in which the current controlled by the current control device is passed through the resistor and an open state in which the current is interrupted, and the first switch means and the second switch means are in the closed state. When the current flowing through the resistor is defined by the current control device and the supply current is supplied to the capacitive load, and the potential difference detected by the detection means becomes equal to or less than a predetermined value, the first And the second switch means is defined in an open state. This eliminates the need for a high-breakdown-voltage switching element in the second switch means, which is effective for speeding up the switching operation and reducing noise. In addition, the current can be cut off when the current does not need to flow through the resistor by the second switch means, which is effective in reducing power consumption.

  In application to the drive circuit of the image display element, it is effective for power saving and performance improvement.

  The present invention relates to a circuit configuration for supplying a desired current to a capacitive load, including a resistor and a current control device for controlling a current flowing through the resistor. For example, in application to a video display device, it can be used for drive control of an image display element, but is not limited to this, and various devices that require high voltage drive (for example, a piezoelectric element, a cooling pump element, etc.) The present invention can be widely applied to such drive circuits.

  FIG. 1 is a block diagram showing a basic configuration example of a video display apparatus according to the present invention.

  The video display device 1 includes a data processing circuit 2, a memory 3, a display driver circuit 4, and a display panel 5.

  In the processing of video data, for example, an external input digital video signal is input to the data processing circuit 2 and processed, and an output signal of the data processing circuit 2 is sent to the display driver circuit 4 at the subsequent stage. The memory 3 is used for temporarily storing data in data processing.

  When receiving a signal indicating the input data from the data processing circuit 2, the display driver circuit 4 sequentially converts the signal into an analog signal (D / A = digital-analog conversion). The analog signals obtained by the D / A conversion are sequentially held (sample / hold), and the output is sent as a drive signal to the display panel 5.

  The display panel 5 is configured using an image display element (for example, a liquid crystal display element, a GLV element, a light emitting diode, an organic EL element, etc.), and a drive signal from the display driver circuit 4 is supplied to the element. As a result, image display is performed. For example, a configuration in which the display panel 5 is used as a light modulation unit to modulate light from a light source (laser light source or the like) and project the modulated drawing light onto a screen (front projection or rear projection) to display an image. Is mentioned.

  FIG. 2 shows a configuration example of the display driver circuit 4.

  After the data is input from the data processing circuit 2 to the digital data input circuit 4a, it is sent to a subsequent current DAC (digital-analog converter) 4b.

  The output signal of the current DAC 4b is sent to a plurality of sample and hold circuits 4c, 4c,. Signals from the timing control circuit 4d are supplied to these circuits and the digital data input circuit 4a, and a hold voltage held in accordance with operation control according to the signals is supplied to each output unit (signal output device 6). , 6,..., And the output of the display driver circuit 4 is driven to drive the display panel 5.

  FIG. 3 shows an example of the basic configuration of the output unit constituting the display driver circuit 4.

  One end of the resistor 7 is connected to the power supply line 8 of the power supply voltage “HVDD”, and the other end of the resistor 7 is connected to the first switch means (hereinafter referred to as “SW1”) and the second switch means ( This is referred to as “SW2”). Note that these switch means are constituted by using semiconductor switching elements such as FETs, but in the drawing, they are simplified by symbols of open / close switches.

  The first switch means SW1 is connected in series to the capacitive load “C” (or load capacity, which is an image display element in this example). That is, SW1 is switched between a closed state in which a supply current is supplied to the capacitive load C and an open state in which the supply current to the capacitive load C is interrupted. In this configuration example, SW1 is placed in the display driver circuit (IC) and capacitive load C is placed in the display panel. However, the configuration is not limited to this, and both SW1 and capacitive load C are placed in the display panel. Is possible.

  The second switch means SW2 is connected in series with the resistor 7, and is provided between the resistor 7 and the current control device 9 in this example. That is, SW2 is switched between a closed state in which the current controlled by the current control device 9 is passed through the resistor 7 and an open state in which the current is interrupted. SW2 can be provided between the resistor 7 and the power supply line 8. However, as in this example, the resistor 7 is connected to the current control device 9 via SW2, and SW2 and its power supply line 8 are connected. A configuration in which the circuit portion on the lower side (low potential side) is composed of a low withstand voltage element is preferable (there is no need to use a high withstand voltage FET for SW2, etc., which is advantageous for noise reduction). When SW2 is cut off, HVDD is applied to the connection point between the resistor 7 and SW1 each time. For this reason, the voltage sampled and held by SW1 does not depend on the previous voltage history (that is, does not depend on the previous output voltage).

  The current control device 9 controls a current flowing through the resistor 7 (hereinafter referred to as “I”) in the closed state of SW2. As shown in an equivalent circuit using a variable current source symbol in the figure, the value of the current “I” is controlled in accordance with a control signal (denoted “SS”), and is arbitrarily applied to the capacitive load C via SW1. Current. For example, when a DAC and a sample and hold circuit are provided as shown in FIG. 2, the current value of the resistor 7 is controlled in accordance with the hold signal SS after D / A conversion. This can cope with an increase in the number of output channels without increasing the number of DACs, and is effective in preventing an increase in chip area (occupied area). The current control device 9 includes a configuration that can control the current value continuously, a configuration that controls the current value stepwise (gradation selector, etc.), a configuration that combines both, and the like. The circuit configuration (current amount control circuit) can be used. Further, even when the output voltage supplied to the capacitive load C such as a GLV element is high, in the form in which the SW2 and the current control device 9 are configured as a low breakdown voltage circuit portion as in this example, The number of high withstand voltage FETs can be reduced, and the configuration of the high voltage output unit can be determined regardless of the number of gradations.

  The control means 10 controls the open / close state of SW1 and SW2 by timing control based on a predetermined input signal (synchronization signal, clock signal, etc.). That is, SW1 is switched between a closed state in which the supply current is supplied to the capacitive load C and an open state in which the supply current to the capacitive load C is cut off by a control signal sent from the control means 10 to SW1. Further, according to a control signal sent from the control means 10 to SW2, SW2 is switched between a closed state in which the current controlled by the current control device 9 is passed through the resistor 7 and an open state in which the current is cut off.

  FIG. 4 is a waveform diagram showing a control example, and the meanings of the symbols shown in the figure are as follows.

“SIGO1” = potential at the connection point of the resistor 7 and SW1 “SIGO2” = output potential (terminal potential of the capacitive load C)

  The opening and closing operations of SW1 and SW2 are synchronized, but when the on period of SW1 is denoted as “T1” and the on period of SW2 is denoted as “T2”, “T2> T1” (T2 is equal to T1) A little longer than that, including the corresponding period length.)

  In the signal output device 6, first, when the SW 2 is turned on, the current “I” controlled by the current control device 9 flows through the resistor 7. That is, when the resistance value of the resistor 7 is written as “R”, “HVDD−R × I” is obtained as SIGO1. Next, when SW1 is turned on, a current is supplied to the capacitive load C (load driving). For example, until the SW1 is turned off, SIGO2 gradually increases from a predetermined voltage (a time constant circuit is formed by the resistance value R, the capacitance of the capacitive load C, etc.).

Thereafter, SW2 is turned off after SW1 is turned off. Note that during the period in which SW1 and SW2 are in the OFF state, no current flows through the resistor 7, so that power consumption can be reduced. When control by SW2 is not performed, the power consumption is “(HVDD) ² / R”. However, when control by SW2 is performed, the power consumption is “((HVDD) ² / R) × ( T2 / T3) ", and the latter is reduced by (T2 / T3) times. “T3” indicates the ON / OFF cycle of SW1 and SW2.
In application to the video display device, control is performed so that the video non-display period within one cycle of the video synchronization signal includes a period during which SW1 and SW2 are kept off.

  FIG. 5 is a waveform diagram illustrating a case where the capacitive load C is light (capacity is small). SIGO2 rises from a predetermined voltage and shows a constant value. Then, the original operation is rapidly performed by the ON operation of SW1 and SW2. It shows how it falls to the voltage level.

  As described above, the value of the current I flowing through the resistor 7 is defined by the current control device 9 according to the open / close state of SW2, and the current (drive current) is supplied to the capacitive load C according to the open / close state of SW1.

  FIG. 6 shows another example 6A of the signal output device, and the differences from the configuration shown in FIG. 3 are as follows.

  A detection means 11 for detecting a potential difference between the potential at the connection point between the resistor 7 and SW1 and the potential at the connection point between SW1 and the capacitive load C is provided.

  SW1 and SW2 are defined to be open when the potential difference detected by the detection means 11 is less than or equal to a predetermined value.

  In this example, detection means 11 (voltage difference detection circuit) for detecting a voltage difference between SIGO1 and SIGO2 is provided in parallel to SW1, and the detected voltage difference is a predetermined constant. When the value falls below the reference value, both SW1 and SW2 are turned off (that is, the control means 10 receives the detection signal from the detection means 11 and defines both switch means in the off state).

  Thereby, when there is no need to change the output voltage (when the difference between SIGO1 and SIGO2 is small), it is possible to further enhance the power saving effect by preventing current from flowing through the resistor 7.

  FIG. 7 shows another example 6B of the signal output device. The difference from the configuration shown in FIG. 3 is that SW1 has a configuration in which a plurality of switching elements 12 and 13 are connected in series.

  That is, the switching elements 12 and 13 are connected in series, the switching element 12 is connected to the resistor 7, and the switching element 13 is connected to the capacitive load C. Note that semiconductor switching elements such as FETs are used as the switching elements 12 and 13 and ON / OFF control is performed in response to a control signal from the control means 10.

  “C12” and “C13” in the figure indicate the parasitic capacitances of the switching elements 12 and 13, respectively. By inserting a plurality of switching elements in a serial connection state, the effects and harmful effects caused by the parasitic capacitances are reduced. Therefore, it is possible to prevent performance degradation (for example, AC crosstalk that affects the capacitive load C via parasitic capacitance can be reduced).

  According to the configuration described above, the following advantages can be obtained.

-Low power consumption can be realized by controlling the current flowing through the resistor 7 by turning on / off the switch means.
-By shutting off the power supply path to the capacitive load C with SW1, noise accompanying on / off of the current flowing through the resistor 7 is not output.
The detection means 11 for detecting the potential difference between SIGO1 and SIGO2 is provided in the output stage and monitored. When the potential difference is small, the power consumption can be further reduced by turning off SW1 and SW2.
-By adopting SW1 in which a plurality of switching elements are connected in series, AC crosstalk due to the signal of SIGO1 can be prevented from appearing in SIGO2 at the output point.

It is a block diagram which shows the basic structural example of the video display apparatus which concerns on this invention. It is the figure which showed the structural example of the display driver circuit. It is the figure which showed the basic structural example about the signal output device which concerns on this invention. It is the wave form diagram which showed the example of control with FIG. It is a wave form diagram which shows the case where load capacity is small. It is the figure which showed the other example of the signal output device which concerns on this invention. It is the figure which showed another example about the signal output device which concerns on this invention. It is the figure which showed the example of the conventional structure. It is the figure which showed another example about the conventional structure.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Video display apparatus 6, 6A, 6B ... Signal output device, 7 ... Resistance, 9 ... Current control apparatus, 10 ... Control means, 11 ... Detection means, 12, 13 ... Switching element, SW1 ... First switch means SW2 ... second switch means C ... capacitive load

Claims (5)

In a signal output device for supplying a supply current to a capacitive load, comprising a resistor and a current control device for controlling the current flowing through the resistor,
First switch means connected in series to the capacitive load;
Second switch means connected in series to the resistor and connected between the resistor and the current control device ;
Control means for controlling the open / closed state of the first switch means and the second switch means;
Detecting means for detecting a potential difference between the potential of the connection point of the resistor and the first switch means and the potential of the connection point of the first switch means and the capacitive load;
The connection point of the first switch means and the second switch means and one end of the resistor are connected,
The first switch means is provided between the resistor and the capacitive load;
The first switch means is switched between a closed state for supplying a supply current to the capacitive load and an open state for cutting off the supply current to the capacitive load,
The second switch means is switched between a closed state in which a current controlled by the current control device is passed through the resistor and an open state in which the current is interrupted.
When the first switch means and the second switch means are in a closed state, the current flowing through the resistor is defined by the current control device and the supply current is supplied to the capacitive load ,
The signal output device according to claim 1, wherein when the potential difference detected by the detection means becomes equal to or less than a predetermined value, the first and second switch means are defined in an open state . In a signal output device for supplying a supply current to a capacitive load, comprising a resistor and a current control device for controlling the current flowing through the resistor,
First switch means connected in series to the capacitive load;
Second switch means connected in series to the resistor and connected between the resistor and the current control device ;
Control means for controlling the open / close state of the first switch means and the second switch means,
The connection point of the first switch means and the second switch means and one end of the resistor are connected,
The first switch means is provided between the resistor and the capacitive load;
The first switch means is switched between a closed state for supplying a supply current to the capacitive load and an open state for cutting off the supply current to the capacitive load,
The second switch means is switched between a closed state in which a current controlled by the current control device is passed through the resistor and an open state in which the current is interrupted.
When the first switch means and the second switch means are in a closed state, the current flowing through the resistor is defined by the current control device and the supply current is supplied to the capacitive load,
The first switch means comprises a first semiconductor switching element and a second semiconductor switching element connected in series,
A first parasitic capacitance is connected to the first semiconductor switching element, and a second parasitic capacitance is connected to the second semiconductor switching element,
The signal output device , wherein the first semiconductor switching element and the second semiconductor switching element are subjected to on / off control in response to a control signal from a first control means . In the signal output device according to claim 1,
A signal output device, wherein the capacitive load is an image display element. In a video display device including a circuit for processing a video signal and driving an image display element,
A current control device for controlling a resistor and a current flowing through the resistor;
First switch means connected in series to the image display element;
Second switch means connected in series to the resistor and connected between the resistor and the current control device ;
Control means for controlling the open / closed state of the first switch means and the second switch means;
Detecting means for detecting a potential difference between the potential of the connection point of the resistor and the first switch means and the potential of the connection point of the first switch means and the image display element ;
The connection point of the first switch means and the second switch means and one end of the resistor are connected,
The first switch means is provided between the resistor and the image display element ;
The first switch means is switched between a closed state in which a supply current is supplied to the image display element and an open state in which the supply current to the image display element is cut off,
The second switch means is switched between a closed state in which a current controlled by the current control device is passed through the resistor and an open state in which the current is interrupted.
When the first switch means and the second switch means are in a closed state, the current control device defines a current flowing through the resistor and the supply current is supplied to the image display element.
An image display device characterized in that the first and second switch means are defined in an open state when the potential difference detected by the detection means is equal to or less than a predetermined value . In a video display device including a circuit for processing a video signal and driving an image display element,
A current control device for controlling a resistor and a current flowing through the resistor;
First switch means connected in series to the image display element;
Second switch means connected in series to the resistor and connected between the resistor and the current control device ;
Control means for controlling the open / close state of the first switch means and the second switch means,
The connection point of the first switch means and the second switch means and one end of the resistor are connected,
The first switch means is provided between the resistor and the image display element;
The first switch means is switched between a closed state in which a supply current is supplied to the image display element and an open state in which the supply current to the image display element is cut off,
The second switch means is switched between a closed state in which a current controlled by the current control device is passed through the resistor and an open state in which the current is interrupted.
When the first switch means and the second switch means are in a closed state, the current control device defines a current flowing through the resistor and the supply current is supplied to the image display element.
The first switch means comprises a first semiconductor switching element and a second semiconductor switching element connected in series,
A first parasitic capacitance is connected to the first semiconductor switching element, and a second parasitic capacitance is connected to the second semiconductor switching element,
An image display device , wherein the first semiconductor switching element and the second semiconductor switching element are subjected to on / off control in response to a control signal from a first control means .

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