JP4596872B2 - Solid-state image sensor - Google Patents

Description

  The present invention relates to a charge transfer element and a solid-state image sensor that transfer signal charges between connected shift registers, such as a frame transfer type CCD (Charge Coupled Device) image sensor, and in particular, a CCD shift register of an imaging unit. The present invention relates to a solid-state imaging device capable of switching a plurality of transfer electrodes arranged in succession to driving in the same phase.

  A mobile phone with a camera function, a digital camera, and the like are equipped with a high-resolution solid-state imaging device having millions of pixels. These devices include a display unit for previewing an image to be captured.

  In the preview operation, it is necessary to ensure the frame rate. However, the time for reading the signal charge for each pixel from the solid-state image sensor and the time for processing the read signal increase according to the number of pixels of the solid-state image sensor, and this is the current high-pixel number solid-state image sensor. However, it is difficult to secure the frame rate. That is, although the reading speed and the signal processing speed are improved, the current situation is still not sufficient. In particular, since a CCD image sensor sequentially reads out signal charges for each pixel via a horizontal shift register, it is necessary to drive the horizontal shift register with a clock having a frequency proportional to the product of the number of pixels and the frame rate. Problems such as a decrease in transfer efficiency, an increase in power consumption, and heat generation occur.

  The preview image has a small screen and is used exclusively for the purpose of confirming the subject. For this reason, it is not necessary to have a resolution as high as that of a still image that is acquired according to the shutter operation and recorded on a recording medium, for example.

  Therefore, in the current preview operation, for example, the number of signal charge packets to be transferred by the horizontal shift register is reduced by adding and combining information charges of a plurality of pixels arranged close to each other in the vertical shift register of the imaging unit. Ensuring the frame rate is done. The user confirms the image to be captured in the preview, and then operates the shutter button to capture a still image. In this still image shooting, all pixels of the solid-state image sensor are read out to obtain a high-resolution image.

  Conventionally, as a frame transfer type CCD image sensor corresponding to the acquisition of an image without pixel compression in still image shooting and the acquisition of an image with pixel compression in preview, the imaging unit has three-phase drive vertical A shift register transfer electrode (image pickup unit transfer electrode) having a nine-phase gate structure has been proposed.

  FIG. 4 is a plan view of the main part showing the structure of the image pickup unit and storage unit of the conventional frame transfer type CCD image sensor. In this structure, three transfer electrodes are associated with each bit of the vertical shift register of each of the image pickup unit 2 and the storage unit 4, and the nine transfer electrodes constituting the three consecutive bits are independent of each other. Can be applied. That is, in the imaging unit 2, the imaging unit transfer electrodes gi1 to gi9 are repeatedly arranged in the column direction on the channel region 6 of the vertical shift register, and the storage unit transfer electrodes gs1 to gs9 are repeatedly arranged in the column direction in the storage unit 4. Arranged. Here, each bit of the imaging unit 2 constitutes one light receiving pixel. For example, in the case of a Bayer color filter, two types of filters having different color transmission characteristics are alternately arranged in the light receiving pixels arranged in the column direction. The

  In the imaging unit 2 in the exposure period, the imaging unit 2 and the storage unit 4 at the time of standard driving performed in still image shooting, the three-phase clocks φi1 to φi3 or φs1 to φs3 are applied to the three transfer electrodes of each bit. The For example, in the image pickup unit 2, the clock φi1 is applied to the transfer electrodes gi1, gi4, and gi7, the clock φi2 is applied to the transfer electrodes gi2, gi5, and gi8, and the clock φi3 is applied to the transfer electrodes gi3, gi6, and gi9. Accumulation and frame transfer are performed. In the storage section 4, the clock φs1 is applied to the transfer electrodes gs1, gs4, and gs7, the clock φs2 is applied to the transfer electrodes gs2, gs5, and gs8, and the clock φs3 is applied to the transfer electrodes gs3, gs6, and gs9. In addition, operations such as temporary storage of signal charges are performed.

  On the other hand, in preview shooting, pixel compression driving is performed in which frame charge transfer is performed after signal charge addition / synthesis processing is performed on three consecutive pixels in the column direction of the imaging unit 2. For example, as a signal charge addition and synthesis process when pixels of different colors are arranged alternately in the column direction, the center pixel of the three pixels is thinned out, and the signal charges of the same color pixels on both sides thereof are added. Done. Specifically, in the processing, first, signal charges accumulated in the central pixel in which the transfer electrodes gi4 to gi6 are arranged among the three pixels are discharged to the substrate by applying an off voltage to the transfer electrodes, and thereafter Then, the transfer electrodes gi1 to gi6 are driven to add and combine the signal charges of the pixels corresponding to the transfer electrodes gi1 to gi3 with the signal charges stored in the pixels corresponding to the transfer electrodes gi7 to gi9.

  After performing the addition / combination processing for every three pixels in this way, in pixel compression driving, three-phase driving is performed in which the three transfer electrodes of each bit of the imaging unit 2 and the storage unit 4 are in phase. That is, clock φi1 is applied to transfer electrodes gi1 to gi3, clock φi2 is applied to transfer electrodes gi4 to gi6, clock φi3 is transferred to transfer electrodes gi7 to gi9, clock φs1 is transferred to transfer electrodes gs1 to gs3, clock φs2 is transferred to transfer electrodes gs4 to gs6, and transfer electrodes are transferred. The clock φs3 is applied to gs7 to gs9. As a result, in pixel compression driving, frame transfer that is three times faster at the same clock frequency as in standard driving is realized, and smear is reduced.

  As described above, in order to reduce smear by further speeding up the frame transfer, the imaging unit 2 needs to increase the moving distance of the signal charge per clock cycle. However, this is not necessary for the light-shielding storage unit 4. From this point of view, in pixel compression driving, it is not necessary to drive the transfer electrodes of each bit of the storage unit 4 in the same phase, and the storage unit applies a different clock to each transfer electrode of each bit as in standard driving. A configuration with three-phase driving is also conceivable. And it may be possible to reduce the area of the storage unit 4 by configuring as such.

  For example, in a CCD image sensor that performs pixel compression, a mechanical shutter is provided in front of the imaging unit, and in still image shooting, when the exposure period ends, the mechanical shutter is closed and signal charges are read line by line. In this configuration, the storage unit is not required for still image shooting, and the storage unit is required only during preview shooting in which the mechanical shutter cannot be used because it is necessary to ensure the frame rate. Therefore, it is sufficient that the shift register of the storage unit has a number of bits that can store an image in which the number of pixels is compressed. Conventionally, since one transfer electrode of each of the image pickup unit and the storage unit is formed to have the same width, the transfer unit is configured to be an image pickup unit that drives n consecutive transfer electrodes (three in the conventional technology described above) in the same phase of the clock. On the other hand, an accumulation unit that drives each transfer electrode with a clock having a different phase can basically have an area of 1 / n.

  However, the short-channel effect cannot be ignored in the CCD shift register that has been miniaturized in recent years, and the case where the effective transfer electrode width is increased by applying an in-phase clock to three consecutive ones and one transfer electrode. In this case, there is a difference in the influence of the short channel effect. Specifically, even when the same clock voltage is applied, the channel potential under the transfer electrode when the clock is applied to the individual transfer electrodes is the transfer when the clock is applied to three consecutive lines in common. It becomes shallower than the channel potential under the electrode. Therefore, for example, in pixel compression driving, an off voltage is applied to the transfer electrodes gi7 to gi9 of the imaging unit 2, an on voltage is applied to the transfer electrode gs1 of the storage unit 4, and a signal is transmitted from the imaging unit 2 side to the storage unit 4 side. When transferring charge, the difference between the channel potential in the off state on the imaging unit side and the channel potential in the on state of the storage unit is reduced as compared with the case where the on voltage is commonly applied to the conventional transfer electrodes gs1 to gs3. There has been a problem that transfer efficiency may be lowered.

  In response to this deterioration in transfer efficiency, the concentration profile of impurities injected into the substrate surface to form a buried channel is changed between the imaging unit and the storage unit, and the channel potential of the storage unit is configured deeper than the channel potential of the imaging unit. Can be considered as a countermeasure.

  However, in a CCD image sensor with a small cell size in recent years, it is difficult to form a steep change in the density profile at the boundary between the imaging unit and the storage unit. As a result, there is a problem in that deterioration of transfer efficiency may not be sufficiently prevented.

  The present invention has been made to solve the above-described problem, and can transfer signal charges from the imaging unit to the storage unit at high speed while ensuring charge transfer efficiency. An object of the present invention is to provide a solid-state imaging device capable of reducing the size.

  In the solid-state imaging device according to the present invention, signal charges are transferred in a column direction by a plurality of first transfer electrodes arranged in the column direction, and nk lines (n is an integer of 2 or more, k is a line number) continuously arranged in the column direction. The first transfer electrode (which is an integer greater than or equal to 3) can be driven independently of each other, and the signal charges from the first shift register by a plurality of second transfer electrodes arranged in a column direction. A second shift register in which the k second transfer electrodes that are taken in and accumulated and are continuously arranged in the column direction can be driven independently of each other, and the first shift register has k continuous The first transfer electrode can be driven by switching between standard driving for k-phase driving with different phases or bit compression driving for k-phase driving with n consecutive first transfer electrodes in phase. Yes, each second transfer Area of the unit gate region and To channel region of the second shift register poles intersect is greater than the area of the unit gate region where the a and the first transfer electrode and the channel region of the first shift register intersect.

  According to the present invention, since the area of the unit gate electrode related to the second transfer electrode is larger than the area of the unit gate electrode related to the first transfer electrode, the area below each second transfer electrode when the on-voltage is applied. The channel potential becomes deeper than the channel potential under each first transfer electrode. As a result, the channel potential difference generated between the two bits when the signal charge is transferred from the last bit of the first shift register to the first bit of the second shift register can be ensured not only in the standard driving but also in the bit compression driving. It becomes possible. At the time of bit compression driving, the transfer of signal charges from the first shift register to the second shift register is completed with a 1 / n number of clocks at the time of standard driving, and the movement speed of the signal charges is correspondingly increased. Charge transfer efficiency can be maintained at a suitable level even in high-speed signal charge transfer during compression driving.

  A preferred aspect of the present invention is a charge transfer device in which a width of the second transfer electrode is larger than a width of the first transfer electrode.

In another charge transfer device according to the present invention, the n is equal to the k, each bit of the first shift register is associated with the k first transfer electrodes, and the bit compression drive In the charge transfer element that synthesizes the signal charges accumulated in α out of k consecutive bits in the column direction by the first shift register and transfers them to the second shift register in the column direction. The width ws of the transfer electrode is the following relational expression corresponding to the width wi of the first transfer electrode:
wi <ws <αwi + (α−1) d (where d is the gap width between the first transfer electrodes or the second transfer electrodes)
It satisfies.

  According to the present invention, each bit of the second shift register is transferred and stored with the combined amount of signal charges stored in α bits. The charge storage capacities in the first shift register and the second shift register basically increase according to the area of the channel region that stores the signal charge and the depth of the channel potential. Here, a potential well formed with one transfer electrode in an ON state spreads to a gap between adjacent transfer electrodes by a fringe electric field. When the width of the first transfer electrode is wi, the width of the second transfer electrode is ws, and the gap width is d, the effective width of each first transfer electrode is wi + d, and the effective width of each second transfer electrode is The width is ws + d. If the depth of the potential well under each of the first transfer electrode and the second transfer electrode is the same, if the effective width of the second transfer electrode is equal to the sum of the effective widths of the α first transfer electrodes, The signal charge obtained by synthesizing α pixels under the two transfer electrodes can be held. From this viewpoint, ws = αwi + (α−1) d. Here, in order to maintain good transfer efficiency from the first shift register to the second shift register, wi <ws is set, so that the potential well under one first transfer electrode is different due to the short channel effect. The depth is shallower than the potential well below the second transfer electrode. Therefore, in practice, ws can be made narrower than αwi + (α−1) d. That is, ws can be set to satisfy wi <ws <αwi + (α−1) d. Thus, by making the second transfer electrode wider than the first transfer electrode, it is possible to maintain the charge transfer efficiency from the first shift register to the second shift register in the bit compression drive, The area of the second shift register is reduced by a width smaller than the width [αwi + (α-1) d] necessary for the arrangement of α transfer electrodes that have accumulated signal charges in one shift register. Can do.

  A solid-state imaging device according to the present invention includes a plurality of imaging unit shift registers arranged in a row direction, in which signal charges are accumulated and transferred in a column direction for a plurality of pixels by a plurality of imaging unit transfer electrodes arranged in a column direction. The nine image pickup unit transfer electrodes continuously arranged in the column direction can be driven independently from each other, and a plurality of image pickup units are arranged in the row direction corresponding to the plurality of image pickup unit shift registers, and the column direction A storage unit shift register that takes in the signal charge from the imaging unit shift register and temporarily stores the signal charge by a plurality of storage unit transfer electrodes arranged in a row. A storage unit that can be driven independently, and the imaging unit shift register is set to a standard drive that drives three consecutive imaging unit transfer electrodes in different phases from each other, or the imaging unit It is possible to switch between pixel compression driving for three-phase driving with three consecutive transmission electrodes in the same phase, and the storage unit transfer electrode has a width corresponding to twice the width of the imaging unit transfer electrode The area of the unit gate region where each storage unit transfer electrode and the channel region of each storage unit shift register intersect is the same as the area of each imaging unit transfer electrode and the channel region of each imaging unit shift register. It is larger than the area of the unit gate region.

  According to the present invention, it becomes easy to control the impurity concentration profile at the boundary between the first shift register (imaging unit) and the second shift register (storage unit), and not only standard driving but also bit compression driving (pixel compression driving). In this case, the signal charge can be transferred from the first shift register (imaging unit) to the second shift register (storage unit) at high speed while ensuring the charge transfer efficiency.

  Hereinafter, embodiments of the present invention (hereinafter referred to as embodiments) will be described with reference to the drawings.

  FIG. 1 is a schematic plan view showing a schematic configuration of a CCD image sensor 10 according to the present invention. The CCD image sensor 10 has a frame transfer type structure, and includes an imaging unit 10i, a storage unit 10s, a horizontal transfer unit 10h, and an output unit 10d formed on the surface of a semiconductor substrate.

  A plurality of cells (pixels) that generate charges (information charges) according to the amount of incident light are arranged in a matrix in the imaging unit 10i. A color filter (not shown) is attached to the imaging unit 10i, thereby giving color sensitivity characteristics to each cell. Each column of cells arranged in a matrix in the imaging unit 10i constitutes a vertical CCD shift register (first shift register). The vertical CCD shift register of the image pickup unit 10i includes a plurality of transfer electrodes (gate electrodes) provided in the row direction on the substrate. By the clock φi applied to these transfer electrodes, accumulation of information charges in the image pickup unit 10i and Vertical transfer is controlled. Here, nine transfer electrodes of the imaging unit 10i are configured to be driven independently of each other (9-phase gate structure). As will be described later, the CCD image sensor 10 is used by separately providing a mechanical shutter on the front surface of the imaging unit 10i.

  The storage unit 10s is covered with a light shielding film, and charge generation due to incidence of light is prevented. The storage unit 10s includes a plurality of vertical CCD shift registers (second shift registers) arranged in the row direction. The vertical CCD shift registers of the storage unit 10s are provided corresponding to the vertical CCD shift registers of the imaging unit 10i. The vertical CCD shift registers corresponding to each other of the imaging unit 10i and the storage unit 10s have continuous channels, and by driving both shift registers in synchronization, signal charges can be transferred from the imaging unit 10i to the storage unit 10s. . Incidentally, the vertical CCD shift register of the storage unit 10s has a bit number corresponding to 1/3 of the number of rows of the imaging unit 10i for the reason described later. The vertical CCD shift register of the storage unit 10s includes a plurality of transfer electrodes passed in the row direction, like the imaging unit 10i. The three transfer electrodes of the storage section 10s are configured to be driven independently of each other (three-phase gate structure). The storage and vertical transfer of information charges in the storage unit 10s are controlled by the three-phase clock φs applied to these transfer electrodes.

  When the set exposure period ends, the information charges accumulated in the imaging unit 10i are vertically transferred to the horizontal transfer unit 10h via the accumulation unit 10s. Here, for example, when shooting a high-resolution still image, the image sensor 10 individually reads out the signal charge of each light receiving pixel of the imaging unit 10i (standard drive). In this photographing mode, when the exposure period ends, the mechanical shutter is closed to shield the imaging unit 10i, and the signal charges accumulated in the imaging unit 10i are read out to the output unit 10d via the accumulation unit 10s and the horizontal transfer unit 10h.

  On the other hand, when performing display on a preview screen or video recording that does not require much resolution, the frame rate can be ensured by adding and synthesizing a plurality of pixels of the imaging unit 10i (pixel compression driving). Here, in the pixel compression driving, with respect to the column direction, every three pixels are added and combined by the imaging unit 10i, and one signal charge packet is generated. As a result, the number of pixels in the column direction is compressed to 1/3. In this shooting mode, when the exposure period ends, after performing addition synthesis processing in the column direction, signal charges are transferred from the imaging unit 10i to the storage unit 10s at high speed. Thereafter, the signal charges from the storage unit 10s are vertically transferred line by line to the horizontal transfer unit 10h and read out to the output unit 10d.

  As described above, since a smear can be prevented by using a mechanical shutter in still image shooting, an accumulation unit is not required, and the accumulation unit is exclusively used as a signal charge storage destination in frame transfer during preview or the like. Is provided. That is, the vertical CCD shift register of the storage unit 10s basically only needs to be able to store a preview image or a moving image in which the number of pixels is compressed in the column direction. Therefore, as described above, the number of bits is the number of rows of the imaging unit 10i. Is set to a value corresponding to 1/3 of.

  The horizontal transfer unit 10h sequentially transfers information charges transferred from the storage unit 10s to the output unit 10d in response to a horizontal transfer clock φh applied to the plurality of gate electrodes. The output unit 10d is composed of an electrically independent capacitor and an amplifier that extracts the potential change thereof. The information charge output from the horizontal transfer unit 10h is received by the capacitor in units of 1 bit and converted into a voltage value. Output as a signal.

  FIG. 2 is a plan view of the main part showing the structure of the imaging unit 10 i and the storage unit 10 s of the CCD image sensor 10. In the imaging unit 10 i and the storage unit 10 s, a plurality of channel regions 12 extending in the column direction are arranged in the row direction with the element isolation region 14 interposed therebetween, and transfer electrodes are arranged across the channel region 12. The imaging unit transfer electrodes gi1 to gi9 are repeatedly arranged in the column direction in the imaging unit 10i. The imaging unit transfer electrodes gi1 to gi9 have a nine-phase gate structure as described above, and are configured to be able to apply independent clocks. Each bit of the vertical shift register 16i constitutes a light receiving pixel, and each transfer bit is associated with three transfer electrodes. For example, a Bayer color filter is arranged in the imaging unit 10i, and two types of filters having different color transmission characteristics are alternately arranged in the light receiving pixels arranged in the column direction.

  On the other hand, storage unit transfer electrodes gs1 to gs3 are repeatedly arranged in the column direction in the storage unit 10s. The storage unit transfer electrodes gs1 to gs3 have a three-phase gate structure as described above, and are configured to be able to apply independent clocks. The storage unit transfer electrodes gs1 to gs3 define one bit of the vertical shift register 16s, and clocks φs1 to φs3 are supplied to these electrodes gs1 to gs3, respectively, and three-phase driving is performed.

  Here, the area Ss where the storage unit transfer electrodes gs1 to gs3 intersect with the channel region of the vertical shift register 16s is set larger than the area Si where the imaging unit transfer electrodes gi1 to gi9 intersect with the channel region of the vertical shift register 16i. Is done. Here, since the channel widths of both the vertical shift registers 16i and 16s are configured in common, the width ws of each of the storage unit transfer electrodes gs1 to gs3 is set larger than the width w i of each of the imaging unit transfer electrodes gi1 to gi9. . That is, the magnification κ (≡ws / wi) is configured so that κ> 1. As a result, the channel potential under the storage unit transfer electrode when the ON voltage is applied becomes deeper than the channel potential under the imaging unit transfer electrode. Thus, the signal charge from the last bit electrode gi9 of the vertical shift register 16i of the imaging unit 10i to the first bit electrode gs1 of the vertical shift register 16s of the storage unit 10s is increased by the amount of the channel potential below the storage unit transfer electrode. The channel potential difference generated between the two bits at the time of transfer is increased, and the charge transfer efficiency is maintained and improved.

  Further, as will be described later, in pixel compression driving, the combined amount of the signal charges accumulated in the two light receiving pixels is transferred and accumulated in each accumulation unit transfer electrode. The width ws (or area Ss) is set to enable this. Here, a potential well formed with one transfer electrode in an ON state spreads to a gap between adjacent transfer electrodes by a fringe electric field. When the gap width is d, the effective width of each image pickup unit transfer electrode is wi + d, and the effective width of each storage unit transfer electrode is ws + d. If the depth of the potential well under each image pickup unit transfer electrode and the storage unit transfer electrode is the same, if the effective width of the storage unit transfer electrode is equal to the sum of the effective widths of the two image pickup unit transfer electrodes, storage is performed. A signal charge obtained by synthesizing two light receiving pixels can be held under the partial transfer electrode. From this point of view, ws = 2wi + d. Here, in order to maintain good transfer efficiency from the imaging unit to the storage unit, wi <ws is set, and therefore, the depth of the potential well under one imaging unit transfer electrode is stored due to the difference in the short channel effect. It becomes shallower than the potential well under the partial transfer electrode. Therefore, in practice, ws can be made smaller than 2wi + d. That is, ws can be set to satisfy wi <ws <2wi + d. Thus, by setting the storage unit transfer electrode to be wider than the imaging unit transfer electrode, it is possible to maintain the charge transfer efficiency from the imaging unit to the storage unit in the pixel compression drive, and in the imaging unit Since the width can be smaller than the width (2wi + d) necessary for the arrangement of the two transfer electrodes that have accumulated the charge, the area of the accumulation portion can be reduced. The specific numerical value of κ can be determined according to, for example, an experiment or simulation that determines the difference in the degree of the short channel effect between the storage unit transfer electrode and the imaging unit transfer electrode with an expanded width. Here, κ = 2 is set, and both the transfer efficiency and the charge storage capacity of the storage unit transfer electrode are suitably maintained.

  Next, driving of the vertical shift register of the CCD image sensor 10 will be described.

  In the imaging unit 10i in the exposure period and the imaging unit 10i in standard driving performed in still image shooting, the three-phase clocks φi1 to φi3 are applied to the three transfer electrodes of each bit. For example, the clock φi1 is applied to the transfer electrodes gi1, gi4, gi7, the clock φi2 is applied to the transfer electrodes gi2, gi5, gi8, and the clock φi3 is applied to the transfer electrodes gi3, gi6, gi9. Done.

  In the storage unit 10s, three-phase clocks φs1 to φs3 are applied to the three transfer electrodes gs1 to gs3 of each bit, and operations such as vertical transfer and temporary storage of signal charges are performed. At the time of vertical transfer of signal charges from the imaging unit 10i to the storage unit 10s, the clocks φs1 to φs3 are clock signals synchronized with the clocks φi1 to φi3, respectively.

  On the other hand, in preview shooting, pixel compression driving is performed in which frame charge transfer is performed after signal charge addition / synthesis processing is performed on three consecutive pixels in the column direction of the imaging unit 10i. For example, as an addition synthesis process in the CCD image sensor 10 in which pixels of different colors are arranged alternately in the column direction, the center pixel of the three pixels is thinned out, and the signal charges of the pixels of the same color on both sides thereof are added. Is done. Specifically, in the processing, first, signal charges accumulated in the central pixel in which the transfer electrodes gi4 to gi6 are arranged among the three pixels are applied to the transfer electrodes by applying an off voltage to the same as in the electronic shutter. After discharging to the substrate in principle, the transfer electrodes gi1 to gi6 are driven, and the signal charges of the pixels corresponding to the transfer electrodes gi1 to gi3 are added to the signal charges accumulated in the pixels corresponding to the transfer electrodes gi7 to gi9. To do.

  After performing the addition / combination processing for every three pixels in this way, in pixel compression driving, three-phase driving is performed in which the three transfer electrodes of each bit of the imaging unit 10i are in phase. That is, the clock φi1 is applied to the transfer electrodes gi1 to gi3, the clock φi2 is applied to the transfer electrodes gi4 to gi6, and the clock φi3 is applied to the transfer electrodes gi7 to gi9. As a result, in pixel compression driving, frame transfer that is three times faster at the same clock frequency as in standard driving is realized, and smear is reduced. In this frame transfer, the clocks φs1 to φs3 applied to the storage unit 10s are clock signals synchronized with the clocks φi1 to φi3, respectively.

  FIG. 3 is a schematic diagram showing a change in channel potential at the output terminal of the vertical shift register 16i of the imaging unit 10i and the input terminal of the vertical shift register 16s of the storage unit 10s during the vertical transfer of signal charges. The solid lines 20a and 20b shown in the image pickup unit 10i in the figure represent channel potentials during standard driving, and the alternate long and short dash lines 22a and 22b represent channel potentials during pixel compression driving. In the figure, the horizontal direction represents the direction along the channel of the vertical shift register. Further, the vertical direction represents the channel potential, and the lower the channel direction, the deeper the channel potential.

  In FIG. 3A, a potential well is formed at the output end of the vertical shift register 16i of the imaging unit 10i. On the other hand, in the storage unit 10s, φs1 is an off voltage and the channel potential below the electrode gs1 is set as a barrier potential ψsb. It shows the state. In standard driving, an on-voltage is applied only to the electrode gi9, and a potential well 20a having a channel potential of ψis is formed. During pixel compression driving, the electrodes gi7 to gi9 are commonly applied with an on-voltage, and a potential well 22a having a channel potential of Ψis ′ is formed. Here, the potential well 20a at the time of standard driving is formed under a single electrode and strongly receives the short channel effect, while the potential well 22a at the time of pixel compression driving is effective by driving three electrodes in common. The electrode width is increased and the short channel effect is mitigated. Therefore, Ψis <Ψis ′.

  FIG. 3B shows a state in which the potential wells 20a and 22a are formed at the output end of the vertical shift register 16i of the imaging unit 10i, the φs1 is turned on in the storage unit 10s, and the channel potential Ψss is below the electrode gs1. The state where the potential well 24 is formed is shown. As described above, the width ws of the transfer electrode of the storage unit 10s is set to wi <ws <2wi + d. Therefore, Ψis <Ψss <Ψis ′ due to the difference in the short channel effect.

  FIG. 3C shows a state in which the potential wells 20a and 22a formed at the output end of the vertical shift register 16i of the imaging unit 10i are eliminated to form barrier potentials 20b and 22b from the state shown in FIG. Show. In standard driving, Ψis <Ψss, and the distance that the signal charge should move is a relatively short distance corresponding to the transfer electrode width wi of the imaging unit 10i, so that the signal charge is an electrode with good charge transfer efficiency. Move to gs1. On the other hand, at the time of pixel compression driving, the distance that the signal charge should move is increased by the increase in the effective transfer electrode width, and there is a possibility that the charge transfer efficiency may be lowered particularly at high speed driving like frame transfer. is there. In order to solve this problem, in this CCD image sensor, the transfer channel width ws of the accumulating unit 10s is enlarged to reduce the short channel effect and increase Ψss. Thereby, in the state shown in FIG. 3C, the fringe electric field at the boundary between the imaging unit and the storage unit is increased, and the deterioration of the charge transfer efficiency is suppressed.

1 is a schematic plan view showing a schematic configuration of a CCD image sensor according to the present invention. It is a top view of the principal part which shows the structure of the imaging part and storage part of a CCD image sensor. It is a schematic diagram showing a change in channel potential at the output end of the vertical shift register of the imaging unit and the input end of the vertical shift register of the storage unit during vertical transfer of signal charges. It is a top view of the principal part which shows the structure of the imaging part and storage part of the conventional frame transfer type CCD image sensor.

Explanation of symbols

10 CCD image sensor, 10i imaging unit, 10s storage unit, 10h horizontal transfer unit, 10d output unit, 12 channel region, 14 element separation region, 16i, 16s vertical shift register.

Claims (4)

The signal charges are transferred in the column direction by a plurality of imaging unit transfer electrodes arranged in the column direction, and nk (n is an integer of 2 or more, k is an integer of 3 or more) arranged in the column direction continuously. an imaging unit shift register imaging unit transfer electrodes can be driven independently of each other,
A channel region having the same width as that of the imaging unit shift register, the signal charges are taken in from the imaging unit shift register and accumulated by a plurality of storage unit transfer electrodes arranged in the column direction, and continuously arranged in the column direction an accumulator shift register in which the k accumulator transfer electrodes can be driven independently of each other;
Have
The image pickup unit shift register is configured to perform standard driving in which k consecutive image pickup unit transfer electrodes are driven in k phases as different phases, or k phase drive in which n successive image pickup unit transfer electrodes are in phase. It can be driven by switching whether to use bit compression drive,
The area of the unit gate region where each storage unit transfer electrode and the channel region of the storage unit shift register intersect is the area of the unit gate region where each imaging unit transfer electrode and the channel region of the imaging unit shift register intersect Greater than,
A solid-state imaging device characterized by the above. The solid-state imaging device according to claim 1,
A solid-state imaging device , wherein a width of the storage unit transfer electrode is larger than a width of the imaging unit transfer electrode. 3. The solid-state imaging device according to claim 1, wherein the n is equal to the k, and each bit of the imaging unit shift register is associated with the k imaging unit transfer electrodes, bit compression driving a solid-state imaging to column transferring the signal charges accumulated in the α-number of the bits of each k or continuous in the column direction by the imaging unit shift register synthesis and continue the storage unit shift register In the element
The width ws of the storage unit transfer electrode is the following relational expression corresponding to the width wi of the imaging unit transfer electrode:
wi <ws <αwi + (α−1) d (where d is the gap width between the imaging unit transfer electrodes or the storage unit transfer electrodes)
The solid-state image sensor characterized by satisfy | filling. It includes a plurality of imaging unit shift registers arranged in the row direction, and stores signal charges for each of the plurality of pixels and transfers in the column direction by a plurality of imaging unit transfer electrodes arranged in the column direction, and continuously in the column direction. An imaging unit in which the nine imaging unit transfer electrodes arranged side by side can be driven independently of each other;
A storage unit shift register that takes in the signal charge from the imaging unit shift register and temporarily stores it by a plurality of storage unit transfer electrodes arranged in a row direction and in a column direction corresponding to the plurality of imaging unit shift registers. A storage section in which the three storage section transfer electrodes arranged continuously in the column direction can be driven independently of each other;
Have
The imaging unit shift register is configured to perform standard driving in which three consecutive imaging unit transfer electrodes are driven in three phases as phases different from each other, or three consecutive imaging unit transfer electrodes in three phases are driven in phase. It can be driven by switching whether to use pixel compression drive,
The storage unit transfer electrode has a width corresponding to twice the width of the imaging unit transfer electrode, and an area of a unit gate region where each storage unit transfer electrode and the channel region of each storage unit shift register intersect Is larger than the area of the unit gate region where each of the imaging unit transfer electrodes and the channel region of each imaging unit shift register intersect,
A solid-state imaging device characterized by the above.

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