JP4597640B2 - FDTD computing device and FDTD computing method - Google Patents

Description

  The present invention relates to an FDTD arithmetic apparatus and an FDTD arithmetic method, and more particularly to an FDTD arithmetic apparatus used in general electromagnetic field simulation such as evaluating characteristics of an antenna and absorption amount when a radio wave is irradiated on a dielectric simulating a human body, The present invention relates to an FDTD calculation method.

  The FDTD (Finite Difference Time Domain Method) method divides a region to be analyzed into blocks of lattice cubes called cells, assigns an electric field on each side, and assigns a magnetic field in the vertical direction to the center of each surface. It is an electromagnetic field simulation technique that expresses spatial and temporal changes of electric and magnetic fields in the analysis region by solving equations. This method is implemented using programming languages such as Fortran and C.

An outline of the FDTD method is shown in FIG. FIG. 4A shows a region to be analyzed. When a region to be analyzed is divided by lattice-like cells, one divided cell is shown in a broken-line circle in FIG. An enlarged view focusing on one of the cells is FIG. In FIG. 2B, the white arrow indicates an electric field, and the black arrow indicates a magnetic field, and a magnetic field is generated by the electric field. Referring to FIG. 3C, a magnetic field Hz is generated on the surface S by the electric field Ey and the electric field Ex. Similarly, a magnetic field is generated by the electric field on the other surfaces constituting the cell. An electric field is generated by the generated magnetic field. This is shown in FIG. In FIG. 4D, an electric field Ez is generated by the magnetic fields Hx and Hy.
Thus, in view of the fact that a magnetic field is generated by an electric field and the electric field is generated by a magnetic field, the FDTD method calculates the difference of the following Maxwell's equations and sequentially calculates the electric field and magnetic field values to change the electromagnetic field. Calculate

An expression for calculating an electric field from a magnetic field and an expression for calculating a magnetic field from the electric field are shown. When calculating the electric field from the magnetic field, the electric field is calculated from the electric field value at the same position one hour before and the surrounding magnetic field (four parameters) and three coefficients (Cex, Cey, Cez, etc.) The magnetic field is calculated from the magnetic field value at the same position one hour before and the electric field (four parameters) and the three coefficients (Chx, Chy, Chz, etc.) positioned so as to surround it.
The calculation formula of the electric field is as follows.

  However, Cex, Cey, Cez, Cexly, Cexlz, Ceylx, Ceylz, Cezlx, and Cezly shown below are constants depending on the position of the cell.

  The calculation formula of the magnetic field is as follows.

  However, Chx, Chy, Chz, Chxly, Chxlz, Chylx, Chylz, Chzlx, and Chzly shown below are constants depending on the position of the cell.

  Here, the numerical values in parentheses indicate the positions of the x coordinate, the y coordinate, and the z coordinate, and the meaning of each variable is as shown in the following table.

Patent Document 1 describes that a radiation pattern was obtained using an electromagnetic field simulator based on the FDTD method when designing a printed circuit board, and the FDTD method is used when designing various products. .
JP 2002-24312 A (paragraph [0066])

When the FDTD method is described and realized in a program language, calculation proceeds by automatic control of a computer, and control regarding memory reading and writing is unnecessary. On the other hand, since it is not parallel calculation, each cell is calculated one by one.
However, since the FDTD method divides the analysis region into fine pieces and sequentially performs calculation for each cell, it is known that a lot of computer resources (memory) are required and the calculation takes a long time.

Therefore, as one method for speeding up, studies have been made on speeding up by implementing an algorithm implemented by a computer in an FPGA (Field Programmable Gate Array) and performing parallel computation.
The FPGA is a general-purpose computing unit that can be used for high-speed processing of large-scale data and as an accelerator for scientific and technical computation. An external memory is provided for storing processing data, and a buffer memory is provided for temporary storage during parallel computation. FIG. 14 shows an outline of the configuration of the FPGA parallel computing unit, and FIG. 15 shows a processing flow when the FDTD method is applied to the FPGA.

  Referring to FIG. 14, the FPGA parallel computing unit includes an external memory 1 for storing the entire data to be computed, and data to be computed once among the data stored in the external memory 1. Are read and stored, and an FPGA unit 3 that functions as a CPU that performs a parallel operation on the data stored in the buffer memory 2 is configured.

Referring to FIG. 15, first, initial data is written in the external memory 1 (step S1). Next, data to be calculated is read from the external memory (step S2), and the data is temporarily stored in the buffer memory 2 (step S3).
In this state, using the data stored in the buffer memory 2, parallel operation is performed by the FPGA (step S4). This calculation result is written in the external memory 1 (step S5). Thereafter, it is determined whether or not the calculation is completed (step S6), and steps S2 to S5 are repeatedly executed until the calculation is completed.

By the way, when the FPGA parallel computing unit is configured as shown in FIG. 14, the access time from the FPGA unit 3 to the external memory 1 is longer than the access time from the FPGA unit 3 to the buffer memory 2. The access time to the external memory 1 occupies most of the processing time. For example, the ratio of the processing time for the entire calculation process is approximately 20: 3: 5 in step S2: step S3: step S4 in FIG. For this reason, there is a problem that it is difficult to shorten the processing time.
The present invention has been made to solve the above-described problems of the prior art, and an object of the present invention is to provide an FDTD arithmetic apparatus and an FDTD arithmetic method that can reduce the arithmetic processing time.

The FDTD arithmetic unit according to claim 1 of the present invention divides an area to be analyzed into a checkered pattern by a plurality of grid-like blocks including a first block group and a second block group, and each of the divided blocks is divided. one of electric and magnetic fields to each side, by performing an operation to solve Maxwell's assigning the other on each side of the blocks, for obtaining a spatial and temporal changes in the electric field and magnetic field in the region FDTD arithmetic unit,
Buffer storage means for storing data read from external memory;
Of the data corresponding to the first block group for a plurality of blocks constituting the region to be analyzed, the data is already stored in the buffer storage means and is calculated for each side of the first block group in the next calculation. Among them, data corresponding to the sides in contact with each side of the second block group adjacent to each other is used as reuse data, and is stored in the data storage means for reading data other than the reuse data and the buffer storage means. And calculating means for performing the calculation using existing data. Among the data corresponding to every other block in the array for the plurality of blocks constituting the analysis target area, data other than the data already stored in the buffer memory and used in the next calculation is read. As a result, the number of accesses to the external memory is reduced and the computation time can be shortened.

  According to a second aspect of the present invention, in the FDTD arithmetic apparatus according to the first aspect, the data reading means is either an odd-numbered one or an even-numbered one of the plurality of blocks located at the end of the region. Data corresponding to one is read, and data corresponding to the other is read the next time. By alternately reading odd-numbered data and even-numbered data, data other than redundantly used data can be read and calculated, the number of accesses to the external memory can be reduced, and calculation time is reduced. it can.

  According to a third aspect of the present invention, the FDTD arithmetic apparatus according to the first or second aspect is characterized in that, in the first or second aspect, the parameters that are used fixedly in the calculation are fixedly stored in the buffer storage means during the calculation. And By storing fixedly used parameters in the buffer memory, the number of accesses to the external memory can be reduced, and the calculation time can be further shortened.

The FDTD calculation method according to claim 4 of the present invention divides a region to be analyzed into a checkered pattern by a plurality of grid-like blocks including a first block group and a second block group, and each of the divided blocks is divided. Controls reading of data into the buffer memory and an external memory having a longer access time than the buffer memory, by assigning one of an electric field and a magnetic field to each side and assigning the other to each side of each block to solve Maxwell's equations An FDTD calculation method for obtaining a spatial and temporal change of an electric field and a magnetic field in the region by performing by a parallel calculator ,
A storage step of storing data read from the external memory in the buffer memory by the parallel computing unit ;
Of the data corresponding to the first block group for the plurality of blocks constituting the region to be analyzed by the parallel computing device, the data is already stored in the buffer memory, and the first block in the next computation Among the sides of the group, the data corresponding to the sides in contact with the sides of the second block group adjacent to each other is used as reuse data, and data other than the reuse data is transferred from the external memory to the buffer memory. A data reading step to be read; and a calculation step of performing the calculation using the data stored in the buffer memory by the parallel calculator . Among the data corresponding to every other block in the array for the plurality of blocks constituting the analysis target area, data other than the data already stored in the buffer memory and used in the next calculation is read. As a result, the number of accesses to the external memory 1 is reduced, and the calculation time can be shortened.

  As described above, according to the present invention, among the data corresponding to every other block in the array, a plurality of blocks constituting the region to be analyzed are already stored in the buffer memory and are calculated in the next calculation. Since data other than the data to be used is read, there is an effect that the calculation time can be shortened.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings referred to in the following description, the same parts as those in the other drawings are denoted by the same reference numerals.
In this embodiment, a case of a cell block configuration of 4 rows and 4 columns (N rows and M columns, N = 4, M = 4) will be described.
(Embodiment)
1 shows a cell block configuration example for calculating the electric field Ez, FIG. 2 shows a cell block configuration example for calculating the electric field Ex, FIG. 3 shows a cell block configuration example for calculating the electric field Ey, and FIG. Is a diagram showing a cell block configuration example for calculating the magnetic field Hz, FIG. 5 is a diagram showing a cell block configuration example for calculating the magnetic field Hx, and FIG. 6 is a diagram showing a cell block configuration example for calculating the magnetic field Hy. is there.

In FIG. 1, black arrows indicate the electric field Ez, white arrows and shaded arrows indicate the magnetic field Hx or the magnetic field Hy. In FIG. 2, black arrows indicate the electric field Ex, white arrows and shaded arrows indicate the magnetic field Hy or the magnetic field Hz. In FIG. 3, black arrows indicate the electric field Ey, white arrows and shaded arrows indicate the magnetic field Hx or the magnetic field Hz.
In FIG. 4, the black arrow indicates the magnetic field Hz, and the white arrow and the shaded arrow indicate the electric field Ex or the electric field Ey. In FIG. 5, black arrows indicate the magnetic field Hx, white arrows and shaded arrows indicate the electric field Ey or the electric field Ez. In FIG. 6, the black arrow indicates the magnetic field Hy, and the white arrow and the shaded arrow indicate the electric field Ex or the electric field Ez.

(Reading data other than duplicate data)
By the way, in the cell block configuration shown in FIGS. 1 to 6, the blocks shown in white and the blocks shown in shaded are alternately arranged in a checkered pattern. Here, paying attention to FIG. 3, after performing the first calculation using data corresponding to the sides constituting all the blocks shown in white, all the blocks shown in shaded are constituted. Consider a case where the second calculation is performed using data corresponding to the edge to be performed, and the calculation is performed on the cell block configuration of FIG.

In that case, there is data that is used redundantly in the first calculation and the second calculation. Since this duplicated data is read from the external memory into the buffer memory before the first calculation, it is used for the second calculation (the value used before one time step is used). Therefore, if data other than redundantly used data is read into the buffer memory before the second calculation, the number of accesses to the external memory is reduced, and the calculation time can be shortened.
The data read from the external memory to the buffer memory before the first calculation will be described with reference to FIG. 7, and the data read from the external memory to the buffer memory before the second calculation will be described with reference to FIG.

Referring to FIG. 7, in the first calculation, since the blocks shown in white are the calculation target, the data read from the external memory to the buffer memory before the calculation is
Magnetic fields Hx (1), Hx (3), Hx (5) to Hx (8), Hx (9) to Hx (12), Hx (13) to Hx (16), Hx (18), and Hx ( 20),
Magnetic fields Hz (1) to Hz (4), Hz (7) to Hz (10), Hz (11) to Hz (14), and Hz (17) to Hz (20),
Electric fields Ey (1), Ey (3), Ey (6), Ey (8), Ey (9), Ey (11), Ey (14), and Ey (16),
It is. All data corresponding to these are read from the external memory into the buffer memory. Here, the data used for the second calculation is a block indicated by shading in FIG. When attention is paid to the block indicated by the shaded area, most of the data is the same as the data used for the first calculation. That is,
Magnetic fields Hx (5) to Hx (8), Hx (9) to Hx (12), Hx (13) to Hx (16),
Magnetic fields Hz (2) to Hz (4), Hz (7) to Hz (9), Hz (12) to Hz (14), Hz (17) to Hz (19),
As for, after being used in the first calculation, the same data is commonly used in the second calculation. Therefore, for the data used in common, the data already stored in the buffer memory is used as it is, instead of reading from the external memory again.

As a result, referring to FIG. 8, in the second calculation, since the block indicated by shading is the calculation target, the data read from the external memory to the buffer memory before the calculation is
Magnetic fields Hx (2), Hx (4), Hx (17), and Hx (19),
Magnetic fields Hz (5), Hz (6), Hz (15), and Hz (16),
Electric fields Ey (2), Ey (4), Ey (5), Ey (7), Ey (10), Ey (12), Ey (13), and Ey (15),
It is. Therefore, in the second calculation, it is only necessary to read much less data from the external memory into the buffer memory than in the first calculation. Therefore, the number of accesses to the external memory can be reduced.

(Processing flow of arithmetic processing)
As shown in FIG. 7 and FIG. 8, the first calculation is performed on the data corresponding to the blocks shown in white, and then the second calculation is performed on the data corresponding to the blocks shown in shading. A processing flow of the arithmetic processing in the case of performing will be described with reference to FIG.
In the figure, the processing from step S2 to S5 corresponds to the first calculation, and the processing from step S6 to S9 corresponds to the second calculation.
Referring to the figure, first, initial data is written into the external memory 1 (step S1). Next, the data corresponding to the above-described blocks shown in white are read from the external memory (step S2), and the data is temporarily stored in the buffer memory 2 (step S3).

In this state, using the data stored in the buffer memory 2, parallel operation is performed by the FPGA (step S4). This calculation result is written in the external memory 1 (step S5).
Next, among the data corresponding to the blocks indicated by the above shaded data, data other than the data read in step S2 (data other than duplicate data) is read from the external memory (step S6), and the data is buffered. Temporarily stored in the memory 2 (step S7).

In this state, using the data stored in the buffer memory 2, parallel operation is performed by the FPGA (step S8). This calculation result is written in the external memory 1 (step S9). Thereafter, it is determined whether or not the calculation is completed (step S10). If the calculation is not finished, the process returns to step S2 to continue the process.
As described above, the calculation for the cell block configuration of FIG. 3 is completed by setting two calculations of steps S2 to S5 and steps S6 to S9 as one set.

Next, an example of data stored in the external memory will be described with reference to FIG. 10, and an example of data read into the buffer memory will be described with reference to FIGS. 11 and 12.
(Contents stored in external memory)
Referring to FIG. 10, data corresponding to Hx, Hy, Hz, Ex, Ey, Ez shown in each of FIGS. 1 to 8 is written and stored in the external memory 1. Prior to the calculation, the FPGA accesses the external memory 1 to read out data necessary for the above calculation and write it into the buffer memory. With respect to data stored in the external memory 1, in this example, it is assumed that a maximum of four unit blocks can be read or written. For example, Hx (1, 2, 1), Hx (2, 2, 1), Hx (3, 2, 1), and Hx (4, 2, 1) are collectively read and Hx (5) to Hx ( 8) Write to the buffer memory.

  Here, referring again to FIG. 7 and FIG. 8, for the four data from Hx (1) to Hx (4), the odd-numbered Hx (1) in FIG. 7 corresponding to the first calculation is shown. ) And Hx (3), and even-numbered Hx (2) and Hx (4) are used in FIG. 8 corresponding to the second calculation. Therefore, for the first four data, the odd number of two data is read into the buffer memory in the first calculation, and the even number of two data is read into the buffer memory in the second calculation. It will be.

  Also, referring to FIG. 7 and FIG. 8, for the four data from Hx (17) to Hx (20), the odd-numbered Hx (18) and Hx (18) in FIG. 7 corresponding to the first calculation are shown. In FIG. 8, which corresponds to the second calculation using Hx (20), even-numbered Hx (17) and Hx (19) are used. Therefore, for the first four data, the even numbered two data are read into the buffer memory in the first calculation (the odd number is not read), and the odd number of the two data in the second calculation. Can be read into the buffer memory (even numbers are not read).

  Returning to FIG. 10, Hx (1,1,1), Hx (2,1,1), Hx (3,1,1) used as the four data from Hx (1) to Hx (4) described above. , Hx (4,1,1) data D13 is read in the first calculation by reading odd-numbered two pieces of data Hx (1,1,1) and Hx (3,1,1). 1), Hx (3) is written in the buffer memory, and even-numbered two pieces of data Hx (2,1,1) and Hx (4,1,1) are read in the second calculation, and Hx (2) , Hx (4) may be written to the buffer memory. Similarly, for the data used as the four data from Hx (17) to Hx (20) described above, the even-numbered two data are read in the first calculation, and Hx (18), Hx (20 ) In the buffer memory, and in the second calculation, the odd-numbered two pieces of data are read out and written into the buffer memory as Hx (17) and Hx (19).

  Similarly for Hz, for the data used as the four data from Hz (1) to Hz (4) described above, the odd-numbered two data are read out in the first calculation, and Hz (1), What is necessary is just to write to the buffer memory as Hz (3), to read two even-numbered data in the second calculation, and to write to the buffer memory as Hx (2) and Hx (4). And about the data used as four data from the above-mentioned Hz (17) to Hz (20), even number two data are read in the 1st calculation, and Hz (18), Hz (20) Is written into the buffer memory, and in the second calculation, the odd-numbered two pieces of data are read out and written into the buffer memory as Hz (17) and Hz (19).

(Contents stored in buffer memory)
Here, FIG. 11 shows the contents of data read into the buffer memory before the first calculation. As shown in the figure, for data used as four data from Hx (1) to Hx (4), two odd-numbered data are read out, and Hx (1), Hx (3 ) Are stored in the buffer memory and used as the four data from Hx (17) to Hx (20), the even-numbered two data are read out as Hx (18) and Hx (20). Stored in buffer memory. For data used as four data from Hz (1) to Hz (4), odd-numbered two data are read and stored in the buffer memory as Hz (1) and Hz (3). For the data used as four data from Hz (17) to Hz (20), two even-numbered data are read and stored in the buffer memory as Hz (18) and Hz (20). In addition, since it calculates about the block shown with the outline in FIG. 7, Ey (1), Ey (3), Ey (6), Ey (8), Ey (9), Ey (11), Ey (14) and Ey (16) are stored in the buffer memory.

FIG. 12 shows the contents of data read into the buffer memory before the second calculation. As shown in the figure, for the data used as four data from Hx (1) to Hx (4), two even-numbered data are read out, and Hx (2), Hx (4 ) Are stored in the buffer memory and used as the four data from Hx (17) to Hx (20), the odd-numbered two data are read out as Hx (17) and Hx (19). Stored in buffer memory. For data used as four data from Hz (1) to Hz (4), even-numbered two data are read and stored in the buffer memory as Hz (2) and Hz (4). For the data used as four data from Hz (17) to Hz (20), the odd-numbered two data are read out and stored in the buffer memory as Hz (17) and Hz (19). In order to calculate the blocks indicated by shading in FIG. 8 , Ey (2), Ey (4), Ey (5), Ey (7), Ey (10), Ey (12), Ey (13) and Ey (15) are stored in the buffer memory.

From the above, reading from the external memory 1 shown in FIG. 10 to the buffer memory is performed as follows.
(1) Search for the address of the first bit of each four unit block.
(2) For the magnetic field Hx and the magnetic field Hz, since 5 unit blocks are read out, for the first block and the last block, the four data are divided into odd and even numbers.
(3) Read odd-numbered data of the first block, all data of the second to fourth unit blocks, and even-numbered data of the last block.
(4) The electric field Ey is read in the order of odd-numbered, odd-numbered, even-numbered, even-numbered, odd-numbered, odd-numbered, even-numbered, even-numbered for each unit block because it is used in a checkered pattern.

(5) Perform the first calculation.
(6) For the magnetic field Hx and the magnetic field Hz, only the even number of the first block and the odd number of the last block are read.
(7) The electric field Ey is read in the order of even-numbered, even-numbered, odd-numbered, odd-numbered, even-numbered, even-numbered, odd-numbered, odd-numbered for each unit block because it is used in a checkered pattern.
(8) The second calculation is performed.
As described above, since the data read from the external memory to the buffer memory before the second calculation is very small, the number of accesses to the external memory can be reduced and the calculation time can be shortened.

In this example, a case where the electric field Ey (y-direction component of the electric field) is calculated and a block of cells is set to 4 × 4 × 1 as a calculation unit will be described.
From the above formula, the parameters used to calculate the electric field Ey are one electric field Ey, two magnetic fields Hx, two magnetic fields Hz, and one each of Cey, Ceylx and Ceylz. It is a parameter.

If 8 parameters are read from the external memory each time, the calculation is executed, and the electric field Ez of the calculation result is written in the external memory, 8 parameters × 16 cells = 128 times of external memory access occurs.
Here, as already described with reference to FIG. 3, when cells are calculated in order, it can be seen that the shaded arrows are used redundantly in calculations in adjacent cells.

Therefore, the calculation of the shaded surfaces arranged at every other interval is executed simultaneously (first calculation), and the calculation of the white surface is executed simultaneously (second calculation). As a result, duplicate parameters can be stored in the buffer memory, and the calculation time can be shortened by reducing the number of accesses to the external memory. In this embodiment, 8 parameters × 16 cells−24 = 104 accesses are required, and a speed increase of 1.23 times can be expected. That is, if the cell block unit is N rows × M columns × 1,
8NM / (5NM- (N. (M-1) + M. (N-1))) (1)
And substituting N = 4 and M = 4 into equation (1),
If the present invention is not adopted (numerator of formula (1)), 8 parameters × 16 cells = 128 accesses to the external memory occur. On the other hand, in this embodiment, it is only necessary to access 8 parameters × 16 cells−24 = 104 times (the denominator of Expression (1)), and a speed increase of 1.23 times can be expected.

  Further, since the three parameters of Cey, Ceylx, and Ceylz are constants depending on the position of the cell, they can be fixedly held as a table in the buffer memory. It is possible to reduce the number of parameters to be read to five by storing them in the buffer memory in a fixed manner during the calculation. Therefore, by combining with the above processing, access to the external memory can be reduced up to 5 parameters × 16 cells−24 = 56 times. In this case, the processing speed can be increased by 2.28 times as compared with the case where the eight parameters are read from the external memory into the buffer memory each time. By setting the cell block unit to N × N × 1, the speed can be increased by 8N / (3N + 2) times.

  By the way, it is desirable that at least one of the values of N and M is an even number. When N and M are both odd numbers, the number of data to be read for use in the calculation is an odd number. Therefore, the first calculation data amount is different from the second calculation data amount, and the FPGA calculation is performed. This is because a period that is not broken occurs and the calculation efficiency decreases.

(Duplicate parameter identification method)
The technique for identifying the parameters used so far as being duplicated so as not to be read multiple times will be described below.
(1) Memory address setting method A flag is added to the memory address where the duplicate parameter is written in the buffer memory area. The parameter of the memory address to which the flag is added is used in two calculations, and then the next parameter is set. Control reading. That is, of the parameters used in the two calculations, only the parameters other than those already stored in the buffer memory and used in the next calculation are read from the external memory.

(2) Edge reading method As can be seen with reference to FIG. 3, non-overlapping parameters are perpendicular to the parameter and calculation plane of the block located at the edge of the N × M × 1 cell blocks. Parameter (Ey in the embodiment of FIG. 3). As a result, only the parameters located at the end and the parameters perpendicular to the calculation plane are identified and read from the external memory.

  According to the present invention, when the FDTD method is applied to a parallel computing machine such as an FPGA, the electromagnetic field computation time can be shortened by reducing the number of accesses to the external memory. For this reason, the electromagnetic environment near the human body, the radiated power of the mobile phone, the indoor electromagnetic environment, and the like can be estimated at high speed, and low power consumption and electromagnetic field environment design efficiency can be improved. In addition, the development efficiency of various products can be dramatically improved.

It is a figure which shows the cell block structural example for calculating the electric field Ez. It is a figure which shows the example of a cell block structure for calculating the electric field Ex. It is a figure which shows the example of a cell block structure for calculating the electric field Ey. It is a figure which shows the example of a cell block structure for calculating the magnetic field Hz. It is a figure which shows the cell block structural example for calculating the magnetic field Hx. It is a figure which shows the cell block structural example for calculating the magnetic field Hy. It is a figure which shows the data read from the external memory to the buffer memory before the 1st calculation. It is a figure which shows the data read from the external memory to the buffer memory before the 2nd calculation. It is a figure which shows the processing flow of the FPGA arithmetic unit by this invention. It is a figure which shows the example of the data memorize | stored in the external memory. It is a figure which shows the content of the data read into the buffer memory before the 1st calculation. It is a figure which shows the content of the data read into the buffer memory before the 2nd calculation. It is a figure which shows the outline | summary of the FDTD method. It is a figure which shows the outline | summary of a structure of a FPGA parallel computing unit. It is a figure which shows the processing flow of an FPGA parallel computing unit.

Explanation of symbols

1 External memory 2 Buffer memory 3 FPGA

Claims (4)

The region to be analyzed is divided into a checkered pattern by a plurality of grid-like blocks including the first block group and the second block group, and one of the electric field and the magnetic field is applied to each side of each of the divided blocks. An FDTD arithmetic unit for obtaining a spatial and temporal change of an electric field and a magnetic field in the region by assigning the other to each surface of a block and performing an operation to solve Maxwell's equation,
Buffer storage means for storing data read from external memory;
Of the data corresponding to the first block group for a plurality of blocks constituting the region to be analyzed, the data is already stored in the buffer storage means and is calculated for each side of the first block group in the next calculation. Among them, data corresponding to the sides in contact with each side of the second block group adjacent to each other is used as reuse data, and is stored in the data storage means for reading data other than the reuse data and the buffer storage means. And an arithmetic means for performing the arithmetic operation using the existing data.   The data reading means reads data corresponding to one of an odd-numbered block and an even-numbered block for a block located at an end of the region among the plurality of blocks, and the next time, data corresponding to the other block The FDTD arithmetic unit according to claim 1, wherein:   3. The FDTD arithmetic apparatus according to claim 1, wherein parameters used in the calculation are fixedly stored in the buffer storage means during the calculation. The region to be analyzed is divided into a checkered pattern by a plurality of grid-like blocks including the first block group and the second block group, and one of the electric field and the magnetic field is applied to each side of each of the divided blocks. An operation for allocating the other to each face of the block and solving Maxwell's equation is performed by a parallel computing unit that controls reading of data into the buffer memory and an external memory having a longer access time than the buffer memory . An FDTD calculation method for obtaining spatial and temporal changes in electric and magnetic fields,
By the parallel operation machine, a storage step of storing the data read from the external memory to the buffer memory,
Of the data corresponding to the first block group for the plurality of blocks constituting the region to be analyzed by the parallel computing device, the data is already stored in the buffer memory, and the first block in the next computation Among the sides of the group, the data corresponding to the sides in contact with the sides of the second block group adjacent to each other is used as reuse data, and data other than the reuse data is transferred from the external memory to the buffer memory. An FDTD calculation method comprising: a data reading step to be read; and a calculation step of performing the calculation using the data stored in the buffer memory by the parallel calculator .

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