JP4599093B2 - Scanning laser microscope equipment - Google Patents

Description

  The present invention relates to a scanning laser microscope apparatus that scans a sample while irradiating the sample with laser light and displays an image of light emitted from the sample.

  Conventionally, a scanning laser microscope apparatus that scans while irradiating a sample with laser light, photoelectrically converts the light emitted from the sample, converts it into an electrical signal, displays the image of the electrical signal, and images the light from the sample Is frequently used. In general, when an electric signal that has been photoelectrically converted is imaged, the electric signal is input to an integration circuit and integrated at a predetermined interval, and the integrated electric signal is converted into a digital signal by A / D conversion. It is imaged. However, when the sensitivity in photoelectric conversion is high or the light intensity of the laser light is high, the photoelectrically converted electrical signal exceeds the output range of A / D conversion, and the digital signal is saturated. When the digital signal is saturated, the image has poor contrast. Therefore, in such a case, the light intensity is detected based on the magnitude of the electric signal input to the integration circuit, and the light exceeding the output range of the A / D conversion is imaged using a two-dimensional image sensor such as a CCD. A technique for realizing this is proposed (see Patent Document 1).

JP 7-67042 A

  However, since the scanning laser microscope apparatus acquires an image by spot scanning of laser light, the technique using the above-described two-dimensional imaging element such as a CCD cannot be applied. Therefore, in a scanning laser microscope apparatus, even when an image with poor contrast is acquired and it is found that the photoelectrically converted electrical signal is too large, how much the sensitivity of photoelectric conversion should be reduced, or the light of the laser beam There is a problem that a quantitative index of how much the intensity should be reduced cannot be obtained, and much labor and time are required to control the sensitivity of photoelectric conversion or the light intensity of laser light.

  The present invention has been made in view of the above, and is a scanning laser that controls an electric signal to be photoelectrically converted so as not to exceed the output range of A / D conversion, and can acquire a high-contrast image in a short time. An object is to provide a microscope apparatus.

In order to achieve the above object, a scanning laser microscope apparatus according to the present invention scans laser light emitted from a laser light source while irradiating the sample while controlling the light intensity by the light intensity control means. The emitted light is converted into an electric signal by a photoelectric conversion means, the electric signal is integrated, and the integrated electric signal is sequentially converted into a digital signal by a digital conversion means, and the integration is performed in synchronization with a display unit in image display. In a scanning laser microscope apparatus that performs processing to reset and displays the digital signal at the time of resetting, when the digital signal exceeds the upper limit of the range of the conversion means, the digital signal until the upper limit of the range is exceeded Extrapolation processing is performed based on the digital signal at the time of resetting, and the estimated digital signal is The controls photoelectric conversion means and / or said light intensity control means, characterized in that said digital signal during said reset with a control means for performing control to converge to the range limit near.

The scanning laser microscope apparatus according to the present invention is characterized in that, in the above invention, the vicinity of the upper limit of the range is not more than the upper limit of the range.

In the scanning laser microscope apparatus according to the present invention , in the above invention, the control unit further includes a counting unit that counts the number of samplings of the digital signal, and the control unit determines the number of samplings at the time of the reset. Dividing by the number of samplings until the upper limit of the range is reached, and a value obtained by multiplying this divided value by the upper limit of the range is used as an estimated value.

In the scanning laser microscope apparatus according to the present invention as set forth in the invention described above, the control means estimates the digital signal at the time of reset by a maximum likelihood estimation method.

In the scanning laser microscope apparatus according to the present invention as set forth in the invention described above, the maximum likelihood estimation method is a least square method.

  When the scanning laser microscope apparatus according to the present invention integrates the photoelectrically converted electrical signal and performs A / D conversion, the integrated value obtained by integrating the electrical signal is saturated beyond the maximum output range of the A / D conversion. An integrated value for one pixel is estimated, and the sensitivity of photoelectric conversion or the light intensity of laser light is controlled based on the estimated integrated value, so that an image with good contrast can be obtained in a short time.

  Exemplary embodiments of a scanning laser microscope apparatus according to the present invention will be explained below in detail with reference to the accompanying drawings.

(Embodiment 1)
In the first embodiment, the laser beam is irradiated onto the sample and the light emitted from the sample is photoelectrically converted and integrated. When the integrated value increases and exceeds the maximum output range of the A / D conversion, this increase occurs. The integral value is increased according to the trend, and the integral value for one pixel is estimated. Based on the estimated integral value for one pixel, the sensitivity of photoelectric conversion or the light intensity of the laser light is controlled, and the integral value Does not exceed the maximum output range of A / D conversion.

  FIG. 1 is a block diagram showing a schematic configuration of a scanning laser microscope apparatus 100 according to Embodiment 1 of the present invention. In FIG. 1, the scanning laser microscope apparatus 100 includes a laser light source 1, a light amount adjusting unit 2, an illumination optical system 3, an observation optical system 5, a photoelectric conversion element 6, a photoelectric conversion element driving unit 7, The switch drive unit 8, the switch 9, the capacitor 10, the operational amplifier 11, the clip diode 12, the control unit 13, and the display unit 14 are included. The control unit 13 further includes a sampling unit 130, a scan control unit 131, a light amount control unit 132, and an image display control unit 133.

  First, the laser light emitted from the laser light source 1 is adjusted in light intensity by a light amount adjusting unit 2 realized by an acousto-optic device (AOTF) or the like, and enters the sample 4 through the illumination optical system 3. The illumination optical system 3 includes a galvano mirror having a function of scanning laser light, an objective lens having a function of condensing the laser light on the sample 4, and the like. The laser light incident on the sample 4 excites, reflects, or transmits the sample 4. Fluorescence, reflected light, or transmitted light is emitted from the sample 4 and enters the photoelectric conversion element 6 through the observation optical system 5.

The photoelectric conversion element 6 is realized by a photomultiplier tube (PMT), an avalanche diode (APD), or the like, converts incident light into an electric signal (current) corresponding to the light intensity, and outputs it to the operational amplifier 11. The photoelectric conversion element 6 is controlled by a photoelectric conversion element driving unit 7 realized by a high-voltage power source or the like, and an output current per unit light amount is controlled by a voltage V _HV applied from the photoelectric conversion element driving unit 7.

The current output from the photoelectric conversion element 6 is input to an integration circuit including a switch 9, a capacitor 10, an operational amplifier 11, a clip diode 12, and the like, and is converted into a voltage signal V _INT . The capacitor 10 accumulates the electric charge of the current output from the photoelectric conversion element 6, the operational amplifier 11 converts the accumulated electric charge into a voltage signal V _INT and outputs it, and the switch 9 is accumulated in the capacitor 10. Controls charge and discharge. The clip diode 12 is arranged so that the voltage signal V _INT output from the operational amplifier 11 does not exceed the predetermined threshold voltage V _MAX and is not input to the control unit 13. The switch driving unit 8 is controlled by the sampling unit 130, drives the opening and closing of the switch 9, and controls charging / discharging of the charge accumulated in the capacitor 10.

The sampling unit 130 is realized by a microprocessor (MPU), a digital signal processor (DSP), an integrated circuit (LSI), or the like, and sends signals to the scanning control unit 131, the light amount control unit 132, and the image display control unit 133, respectively. Output. The scanning control unit 131 controls the illumination system 3, the light amount control unit 132 controls the light amount adjustment unit 2 and the photoelectric conversion element driving unit 7, and the image display control unit 133 controls the display unit 14. . The voltage signal V _INT output to the sampling unit 130 is converted into an image signal by the sampling unit 130 and output and displayed on the display unit 14 via the image display control unit 133.

  Next, the operation of the sampling unit 130 will be described. FIG. 2 is a block diagram illustrating a schematic configuration of the sampling unit 130. The sampling unit 130 includes a timing generator (TG) 1301, a delay unit 1302, an AND circuit 1303, a counter 1304, comparators 1305 and 1310, an A / D converter 1306, latch circuits 1307, 1308, and 1309. A reference clock 1311 and an OR circuit 1312.

  The reference clock 1311 outputs a clock signal CLK that repeats “H” and “L” in a predetermined cycle. When the clock signal CLK is input, the TG 1301 generates a vertical synchronization signal VD, a horizontal synchronization signal HD, and a pixel clock signal PCLK in synchronization with the clock signal CLK, and generates a vertical synchronization signal VD, a horizontal synchronization signal HD, The pixel clock signal PCLK is output to the scanning control unit 131 and the image display control unit 133, and the pixel clock signal PCLK is output to the AND circuit 1303 and the delay unit 1302. The delay device 1302 delays the input pixel clock signal PCLK by one clock and outputs the delayed signal to the AND circuit 1303. The AND circuit 1303 uses the input from the TG 1301 as positive logic and the input from the delay unit 1302 as negative logic. Therefore, the AND circuit 1303 outputs the reset signal RST only for one clock period when the pixel clock signal PCLK rises from “L” to “H”. The reset signal RST is output to the switch driving unit 8, the image display control unit 133, the counter 1304, the latch circuits 1307 and 1308, and the OR circuit 1312. The counter 1304 receives the clock signal CLK, starts counting up in synchronization with the clock signal CLK “H”, and outputs the counted up count signal CNT to the latch circuit 1308. Further, when the counter 1304 receives the reset signal RST “H”, the counter 1304 finishes counting up and resets the counter to “0”.

The voltage signal V _INT output from the operational amplifier 11 is converted into a digital signal DS by the A / D converter 1306. The digital signal DS is output to the latch circuit 1307 and the comparator 1305. When the input digital signal DS reaches the maximum digital signal DS _MAX that is the maximum output range of the A / D converter 1306, the comparator 1305 outputs the threshold over signal OVR _TH “H” to the OR circuit 1312, and When the signal DS is less than the maximum digital signal DS _MAX , the threshold over signal OVR _TH “L” is output to the OR circuit 1312.

Latch circuit 1307 inputs the reset signal RST "H", latches the digital signal DS final digital signal DS _L the output light amount control unit 132 and the image display control unit 133. When either the reset signal RST or the threshold over signal OVR _TH is “H”, the OR circuit 1312 outputs “H” to the latch circuit 1309, and both the reset signal RST and the threshold over signal OVR _TH are “ In the case of “L”, “L” is output to the latch circuit 1309.

When the reset signal RST “H” is input, the latch circuit 1308 latches the count signal CNT input from the counter 1304 and outputs a count end signal CNT _END to the comparator 1310.

When “H” is input from the OR circuit 1312, the latch circuit 1309 latches the count signal CNT input from the counter 1304 and outputs an upper limit value signal CNT _LIM to the comparator 1310 and the light amount control unit 132.

The comparator 1310 compares the value of the count end signal CNT _{END and} the value of the upper limit value signal CNT _{LIM. If} the value of the upper limit value signal CNT _LIM is less than the value of the count end signal CNT _END , the overrange signal OVR “ H ”is output to the light amount control unit 132, and when the value of the upper limit signal CNT _LIM is equal to or greater than the count end signal CNT _END , the overrange signal OVR“ L ”is output to the light amount control unit 132.

3 shows “H” and “L” of the clock signal CLK, “H” and “L” of the pixel clock signal PCLK, “H” and “L” of the reset signal RST, “open” and “closed” of the switch 9, and the count signal. CNT value, voltage signal V _INT (maximum digital signal DS _MAX ) and digital signal DS, threshold over signal OVR _TH “H” “L”, count end signal CNT _END value, upper limit signal CNT _LIM value, over It is a timing chart which shows “H” “L” of range signal OVR.

In FIG. 3, the clock signal CLK is output from the reference clock 1311, and “H” and “L” are output at a period of “H” and “L” at times T <b> 1 to T <b> 2. The pixel clock signal PCLK is output from the TG 1301, and becomes “H” at times T1 and T4 in synchronization with the period in which the laser beam scans one pixel. The reset signal RST is output from the AND circuit 1303 and becomes one clock “H” in synchronization with the times T1 and T4 when the pixel clock signal PCLK rises to “H”. The switch 9 becomes “closed” in synchronization with “H” of the reset signal RST, and discharges the electric charge accumulated in the capacitor 10. The value of the count signal CNT is the value of the count signal CNT output from the counter 1304 and counted up by the counter 1304. The period of one pixel is set to “0” to “39” in the count signal value. The voltage signal V _INT is output from the capacitor 10 and increases with time. The digital signal DS is output from the A / D converter 1306, a signal sampled by the A / D converter 1306 in synchronization with the voltage signal V _INT clock signal CLK. Therefore, the voltage signal V _INT has a continuous value, but the digital signal DS becomes a discrete point on a continuous line of the voltage signal V _INT .

The threshold over signal OVR _TH is output from the comparator 1305, and “H” is output when the voltage signal V _INT reaches the threshold voltage V _MAX , that is, when the digital signal DS reaches the maximum digital signal DS _MAX . The value of the count end signal CNT _{END is} a value output from the latch circuit 1308 and counted up by the digital signal DS in synchronization with “H” of the reset signal RST. Outputs the value of the previously counted up digital signal. In FIG. 3, since the apparatus is started from time T1, the value of the count end signal CNT _END is “0” from time T1 to T4, but the period of one pixel does not change after time T4. As long as the device stops. The value of the upper limit signal CNT _LIM is outputted from the latch circuit 1309, the value of the count-up count signal CNT to the digital signal DS reaches the maximum digital signal DS _MAX. In FIG. 3, since the digital signal DS reaches the maximum digital signal DS _MAX at time T3, the value of the upper limit signal CNT _LIM becomes “29” counted up from time T1 to T3 after time T3. . The overrange signal OVR is output from the comparator 1310, and “H” is output when the value of the upper limit signal CNT _LIM is less than the value of the count end signal CNT _END .

3, the digital signal DS is increased at time T2 to T3, saturated reaches the maximum digital signal DS _MAX at time T3 to T4. Therefore, the final digital signal DS _L at time T4 is a time of one pixel ends has a saturation value to the maximum digital signal DS _MAX. Therefore, light amount control unit 132, a digital signal DS increases the digital signal DS at time T3~T4 at the same rate as the rate was increased at time T2 to T3, and calculates the estimated voltage value V _LAST at time T4. Then, control is performed so that the voltage signal V _INT of the estimated voltage value V _LAST based does not exceed the threshold voltage V _MAX.

Therefore, first, an estimated voltage value _VLAST is obtained. The values “1” to “39” of the count signal CNT counted corresponding to the times T2 to T4 are set as the initial value CNT _MAX, and the values “1” to “1” of the count signal CNT counted corresponding to the times T2 to T3 are set. If “29” is the minimum value CNT _MIN and the minimum value CNT _MIN is the minimum value CNT _LIM that is the minimum in one screen, the estimated voltage value V is obtained by replacing the minimum value CNT _MIN with the minimum value CNT _{LIM. LAST} is determined by the following equation (1).
V _LAST = V _MAX × CNT _MAX / CNT _LIM (1)

Next, an optimum voltage V _{HV (NEW)} to be applied to the photoelectric conversion element 6 is obtained so that the estimated voltage value V _LAST is less than the threshold voltage V _MAX . The optimum voltage V _{HV (NEW)} is obtained by the following equation (2) when the voltage V _HV applied to the photoelectric conversion element 6 when the minimum value CNT _LIM is derived.
V _{HV (NEW)} = V _HV × (V _MAX / V _LAST ) ^{1 / C} (2)
Note that C in Expression (2) is a constant determined by the photoelectric conversion element 6. However, since the photoelectric conversion element 6 functions normally, there is a minimum limit voltage V _{HV (LIM)} , and the optimum voltage V _{HV (NEW)} cannot be set below the minimum limit voltage V _{HV (LIM)} . Therefore, when the optimum voltage V _{HV (NEW)} is equal to or lower than the minimum limit voltage V _{HV (LIM)} , the light quantity control unit 132 sets the minimum limit voltage V _{HV (LIM)} for the photoelectric conversion element 6, The optimum light amount L _{EX (NEW)} is set so that the estimated voltage value V _LAST is less than the threshold voltage V _MAX by controlling the light amount L _EX of the laser light emitted from the laser light source 1 via the light amount adjusting unit 2.

Incidentally, the optimum light amount L _{EX (NEW)} is obtained by the following equation (3) when the light amount L _{EX of the} laser light emitted from the laser light source 1 when the optimum voltage V _{HV (NEW)} is derived.
L _{EX (NEW)} = L _EX × (V _{HV (NEW)} / V _{HV (LIM)} ) ^C・ ・ ・ ・ ・ ・ （3）
Note that C in Expression (3) is a constant having the same value as C used in Expression (2).

Next, operations of the sampling unit 130, the light amount control unit 132, and the image display control unit 133 will be described with reference to the flowchart shown in FIG. First, the light amount control unit 132 determines an initial value CNT _MAX corresponding to one pixel, initializes a minimum value CNT _{LIM in} one screen, and _replaces the minimum value CNT _LIM with the initial value CNT _MAX (step S101). ). Further, the flag FLAG for determining whether or not the overrange signal OVR is generated in one screen is initialized, and the flag FLAG is set to “0” (step S102).

Next, the light amount control unit 132 determines whether or not the reset signal RST is “H” (step S103), and when the reset signal RST is “H” (step S103, YES), the range over signal OVR. Is “H” or not (step S104). When the range over signal OVR is “H” (step S104, YES), the flag FLAG is changed from “0” to “1” (step S105), and whether or not the minimum value CNT _MIN is less than the minimum value CNT _LIM. Is determined (step S106). When the minimum value CNT _MIN is less than the minimum value CNT _LIM (YES in step S106), the minimum value CNT _LIM is replaced with the minimum value CNT _MIN and updated (step S107).

The image display control unit 133 also sets the minimum value CNT when the range over signal OVR is “L” (step S104, NO), when the minimum value CNT _MIN is equal to or _larger than the minimum value CNT _LIM (step S106, NO). _{When the LIM} is updated (step S107), it is determined whether sampling for one screen is completed (step S108). When the reset signal RST is “L” (step S103, NO), or when sampling for one screen is not completed (step S108, NO), the next pixel is sampled (step S103). .

The light quantity control unit 132 determines whether or not the flag FLAG is “1” (step S109). If the flag FLAG is “1” (step S109, YES), the estimated voltage value V is calculated from the minimum value CNT _{LIM. LAST} is obtained (step S110). An optimum voltage V _{HV (NEW)} to be applied to the photoelectric element 6 is obtained from the estimated voltage value V _LAST (step S111).

Next, the light quantity control unit 132 determines whether or not the optimum voltage V _{HV (NEW)} is less than the minimum limit voltage V _{HV (LIM)} (step S112). When the optimum voltage V _{HV (NEW)} is less than the minimum limit voltage V _{HV (LIM)} (step S112, YES), the light quantity control unit 132 applies the minimum limit voltage to the photoelectric conversion element 6 via the photoelectric conversion element driving unit 7. When V _{HV (NEW)} is set (step S113) and the optimum voltage V _{HV (NEW)} is equal to or higher than the minimum limit voltage V _{HV (LIM)} (step S112, NO), the light quantity control unit 132 drives the photoelectric conversion element. The optimum voltage V _{HV (LIM)} is set in the photoelectric conversion element 6 via the unit 7 (step S114).

When the minimum limit voltage V _{HV (LIM)} is set for the photoelectric conversion element 6 via the photoelectric conversion element drive unit 7 (step S114), the light amount control unit 132 sets the optimum light amount L _{EX (NEW )} (= (V _{HV (NEW)} / V _{HV (LIM)} ) ^{1 / C} ) is set (step S115).

In the first embodiment, when the charge accumulated in the capacitor 10 exceeds the output range of the A / D converter 1306 and the A / D converted digital signal is saturated, the estimated voltage value V _LAST is calculated, The amount of light is controlled based on the estimated voltage value _VLAST . If it does in this way, the image controlled to the appropriate light quantity can be acquired from the following screen only by scanning one screen. That is, the light amount can be controlled without much effort in a short time.

  In the first embodiment, both the variable of the applied voltage to the photoelectric conversion element 6 and the control to the light amount adjusting unit 2 are controlled. However, in view of the state of the apparatus and the observation state. Thus, any one of the control of the applied voltage to the photoelectric conversion element 6 and the control to the light amount adjusting unit 2 may be performed.

In the first embodiment, the case where the amount of light exceeds the range of the A / D converter 1306 has been described. However, when the amount of light is below the range in one screen scan, the light amount control unit 132 sets the threshold voltage. it may perform control to increase the amount from the difference between the final digital signal DS _L output from the V _TH and the latch circuit 1307.

(Embodiment 2)
Next, the second embodiment will be described. In the first embodiment, when one screen is scanned and the amount of light exceeds the range of the A / D converter 1306, the estimated voltage value _VLAST is obtained. However, in this second embodiment, the sample When the light from 4 is weak and the digital signal DS converted by the A / D converter 1306 does not increase linearly, the estimated voltage value V _LAST is obtained using the least square method.

In a scanning laser microscope apparatus, when observing a change with time of a sample, it is necessary to scan the laser beam at high speed. In such a case, the pixel clock signal PCLK is shortened, and the amount of charge accumulated in the capacitor 10 is reduced. For this reason, in order to acquire a fluorescence image with sufficient luminance, the applied voltage V _HV to the photoelectric conversion element 6 is increased to increase the detection sensitivity. Further, when the observation sample is a biological specimen that emits weak fluorescence, the absolute amount of photons incident on the photoelectric conversion element 6 is small, and the output current of the photoelectric conversion element is continuous as shown in the schematic diagram of FIG. Instead, it is pulsed. Further, since the current pulse is caused by photons that are probabilistically emitted from the biological specimen, there is a large variation in the total charge amount of the current pulse. Therefore, the estimated voltage V _LAST described in the first embodiment also varies greatly, and if the light amount is controlled based on the estimated voltage V _LAST accompanied by this variation, a large error occurs in the light amount.

FIG. 6 shows “H” and “L” of the clock signal CLK, “H” and “L” of the pixel clock signal PCLK, “H” and “L” of the reset signal RST, “open” and “closed” of the switch 9, voltage signal It is a timing chart showing “H” and “L” of V _INT (maximum digital signal DS _MAX ), digital signal DS, and overrange signal OVR. As shown in FIG. 6, the digital signal DS reaches the threshold voltage V _MAX at time T3, and a line connecting “0” at time T2 and “V _MAX ” at time T3 is derived from the extrapolation line (a). Estimated voltage value Va _LAST and estimated voltage value Vb _LAST derived from extrapolation line (b) connecting a line connecting “0” at time T2 and “V _MAX ” at time T4 one clock after time T3 In comparison, there is a large difference between the estimated voltage values Va _LAST and Vb _LAST even though they are shifted by only one clock. Therefore, in such a case, linear regression calculation is performed by the least square method using the digital signal DS obtained at times T2 to T3, and the estimated voltage value _VLAST is derived from the extrapolated line (c) with the least error. ing.

  FIG. 7 is a block diagram showing a schematic configuration of a scanning laser microscope apparatus 200 according to the second embodiment of the present invention. In FIG. 7, the scanning laser microscope apparatus 200 includes a control unit 15 instead of the control unit 13. The control unit 15 includes a sampling unit 150, a scanning control unit 151, a light amount control unit 152, and an image display control unit 153. In addition, the same code | symbol is attached | subjected to the component same as FIG.

The sampling unit 150 outputs signals to the scanning control unit 151, the light amount control unit 152, and the image display control unit 153, respectively. The scanning control unit 151 controls the illumination system 3, the light amount control unit 152 controls the light amount adjustment unit 2 and the photoelectric conversion element driving unit 7, and the image display control unit 153 controls the display unit 14. . The voltage signal V _INT output to the sampling unit 150 is converted into an image signal by the sampling unit 150 and output and displayed on the display unit 14 via the image display control unit 153.

  Next, the operation of the sampling unit 150 will be described. FIG. 8 is a block diagram illustrating a schematic configuration of the sampling unit 150. The sampling unit 150 includes a toggle flip-flop (T-FF) 1501, a NOR circuit 1502, a NOT circuit 1503, AND circuits 1504 and 1505, and FIFO memories (First-In / First-Out) 1506 and 1507. is doing. In addition, the same code | symbol is attached | subjected to the component same as FIG.

The voltage signal V _INT output from the operational amplifier 11 is converted into a digital signal DS by the A / D converter 1306, and the digital signal DS is output to the latch circuit 1307, the comparator 1305, and the FIFO memories 1506 and 1507. The When the input digital signal DS is equal to or greater than the maximum digital signal DS _MAX of the maximum output of the A / D converter 1306, the comparator 1305 sends the threshold over signal OVR _TH “H” to the NOR circuit 1502 and the light amount control unit 152. When the digital signal DS is less than the digital signal DS _MAX , the threshold over signal OVR _TH “L” is output to the OR circuit 1312 and the light amount control unit 152.

Latch circuit 1307 inputs the reset signal RST "H", and outputs a final digital signal DS _L and light amount control unit 152 and the image display control unit 153 latches the digital signal DS. When receiving the reset signal RST, the T-FF 1501 outputs the select signal S1 to the NOT circuit 1503, the AND circuit 1504, and the FIFO memory 1507 until the next reset signal RST is input.

The select signal S1 becomes “L” when the reset signal RST changes from “L” to “H”, and becomes “H” when the reset signal RST changes from “H” to “L”. When the reset signal RST and the threshold over signal OVR _TH are “L”, the NOR circuit 1502 outputs the write enable signal WE “H” to the FIFO memories 1506 and 1507, and the reset signal RST and the threshold over signal OVR _TH are output. In the case of “H”, the write enable signal WE “L” is output to the FIFO memories 1506 and 1507.

  The NOT circuit 1503 outputs a select signal S2 obtained by inverting the select signal S1 output from the T-FF 1501 to the AND circuit 1505 and the FIFO memory 1506.

  The AND circuit 1504 inputs the reset signal RST and the output from the T-FF 1501, and outputs a clear signal CLR 1 that is a logical product to the FIFO memory 1506. The AND circuit 1505 outputs the reset signal RST and the output from the NOT circuit. And a clear signal CLR2 which is a logical product is output to the FIFO memory 1507.

  When the write enable signal WE is “H” and the select signals S1 and S2 input to the respective write chip select terminals WCS1 and WCS2 are “H”, the FIFO memories 1506 and 1507 receive the digital signal DS as the clock signal CLK. When the read enable signal RE is “H” and the select signals S1 and S2 input to the respective read chip select terminals RCS1 and RCS2 are “H”, the stored digital signal DS is stored. Are output to the light quantity control unit 152 according to the order. Further, when the clear signals CLR1 and CLR2 “H” are input, the FIFO memories 1506 and 1507 clear all the stored contents.

  As shown in FIG. 6, when the pixel clock signal PCLK becomes “H” at time T1, the reset signal RST becomes “H” for one clock period and the switch 9 becomes “closed”, and is accumulated in the capacitor 10. The charge is discharged. At this time, the select signal S1 output from the T-FF 1501 is “H”, and the select signal S1 input to the write chip select terminal WCS1 and the read chip select terminal RCS1 of the FIFO memory 1506 is “H”. The FIFO memory 1506 clears the stored contents.

At time T <b> 2, the reset signal RST becomes “L” and the switch 9 becomes “open”, and charge is accumulated in the capacitor 10. Further, since the reset signal RST is “L” and the threshold over signal OVR _TH is “L” at times T2 to T3, the write enable signal WE becomes “H”. At this time, since the select signal S1 “H” is input to the write chip select terminal WCS1 of the FIFO memory 1506, the digital signal DS output from the A / D converter 1306 is written into the FIFO memory 1506.

At time T 3, the digital signal DS becomes equal to or higher than the threshold voltage V _MAX , the threshold over signal OVR _TH output from the comparator 1305 changes from “L” to “H”, and the write signal output from the NOR circuit 1502. The enable signal WE changes from “H” to “L”, and the writing to the FIFO memory 1506 is completed.

At time T3 to T5, the digital signal DS, saturated threshold voltage V _MAX, at time T5, the pixel clock signal PCLK again becomes "H", the switch 9 with the reset signal RST becomes "H", "closed" Thus, the charge accumulated in the capacitor 10 is discharged.

  When the reset signal RST becomes “H” at time T5, the select signal S1 output from the T-FF 1501 is toggled to change from “H” to “L”, and the select signal S2 is changed from “L” to “H”. To change. At this time, the FIFO memory 1507 receives the clear signal CLR2 from the AND circuit 1505, and clears the contents stored in the FIFO memory 1507. Further, the select signal S2 “H” is input to the write chip select terminal WCS2 of the FIFO memory 1507, and the digital signal DS output from the A / D converter 1306 is written into the FIFO memory 1507.

Next, operations of the sampling unit 150, the light amount control unit 152, and the image display control unit 153 will be described with reference to the flowchart shown in FIG. First, the light amount control unit 152 determines whether or not the threshold over signal OVR _TH is “H” (step S201). This is because while the threshold over signal OVR _TH is “L”, the voltage signal V _INT does not exceed the output range of the A / D converter 1306, and therefore it is not necessary to adjust the light amount. When the threshold over signal OVR _TH is “H” (step S201, YES), it is determined whether or not the reset signal RST is “H” (step S202).

  When the reset signal RST is “H” (step S202, Yes), the light amount control unit 152 performs time-series data DSn (digital signal DS corresponding to one pixel stored in one of the FIFO memories 1506 and 1507). (n = 1, 2,..., N) are read (step S203). In this case, one of the FIFO memories 1506 and 1507 can be written, and the other can be read. That is, while the pixel data for one pixel is being read from one FIFO memory, the next pixel data is written to the other FIFO memory.

Next, the light quantity control unit 152 performs a linear regression operation using the least square method based on the read time-series data DSn (n = 1, 2,..., N), and obtains the estimated voltage value _VLAST . In step S204, it is determined whether or not the estimated voltage value V _LAST for one screen has been acquired (step S205).

If it obtains an estimated voltage value V _LAST for one screen (step S205, YES), and extracts the maximum estimated voltage value V _LAST from the obtained estimated voltage value V _LAST (step S206). The light quantity control unit 152 obtains the optimum voltage value V _{HV (NEW)} from the maximum estimated voltage value V _LAST (step S207).

Next, the light quantity control unit 152 determines whether or not the optimum voltage V _{HV (NEW)} is less than the minimum voltage V _{HV (LIM)} (step S208). When the optimum voltage V _{HV (NEW)} is less than the minimum voltage V _{HV (LIM)} (step S208, YES), the minimum voltage V _{HV (NEW)} is applied to the photoelectric conversion element 6 via the photoelectric conversion element drive unit 7. When set (step S209) and the optimum voltage V _{HV (NEW)} is equal to or higher than the minimum voltage V _{HV (LIM)} (step S208, NO), the optimum voltage is applied to the photoelectric conversion element 6 via the photoelectric conversion element driving unit 7. V _{HV (LIM)} is set (step S210).

When the minimum voltage V _{HV (LIM)} is set to the photoelectric conversion element 6 via the photoelectric conversion element driving unit 7 (step S210), the light amount control unit 132 optimizes the light amount of the laser light via the light amount adjustment unit 2. The light quantity L _{EX (NEW)} (= (V _{HV (NEW)} / V _{HV (LIM)} ) ^{1 / C} ) is set (step S210).

In the second embodiment, when the light from the sample 4 is weak and the digital signal DS converted by the A / D converter 1306 does not increase linearly, the estimated voltage value V _LAST is obtained by using the least square method. Therefore, it is possible to control the amount of light with little error. In this way, noise can be removed in a short time, so that the S / N ratio is high and a bright image signal can be acquired.

  In the first and second embodiments described above, the light amount control units 132 and 152 control the light amount via the light amount adjustment unit 2, but the laser light source 1 is a semiconductor laser (LD). In this case, the light amount control unit 132 and 152 may omit the light amount adjustment unit 2 and directly control the laser light source 1 to control the light amount.

It is a functional block diagram of the scanning laser microscope apparatus concerning Embodiment 1 of this invention. It is a functional block diagram of the sampling part concerning Embodiment 1 of this invention. It is a time chart of each signal and each signal value in the sampling part concerning Embodiment 1 of this invention. It is a flowchart of the control part concerning Embodiment 1 of this invention. It is a schematic diagram which shows the time change of the output current of the photoelectric conversion element concerning Embodiment 2 of this invention. It is a time chart of each signal in the sampling part concerning Embodiment 2 of this invention. It is a functional block diagram of the scanning laser microscope apparatus concerning Embodiment 2 of this invention. It is a functional block diagram of the sampling part concerning Embodiment 2 of this invention. It is a flowchart of the control part concerning Embodiment 2 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Laser light source 2 Light quantity adjustment part 3 Illumination optical system 4 Sample 5 Observation optical system 6 Photoelectric conversion element 7 Photoelectric conversion element drive part 8 Switch drive part 9 Switch 10 Capacitor 11 Operational amplifier 12 Clip diode 13, 15 Control part 100,200 Scan type Laser microscope apparatus 130, 150 Sampling unit 131, 151 Scan control unit 132, 152 Light amount control unit 133, 153 Image display control unit

Claims (4)

The laser light emitted from the laser light source is scanned while irradiating the sample with the light intensity controlled by the light intensity control means, the light emitted from the sample is converted into an electric signal by the photoelectric conversion means, and the electric signal is integrated. In addition, the integrated electric signal is sequentially converted into a digital signal by a digital conversion means, and the integration is reset in synchronization with a display unit in image display, and the digital signal at the time of reset is displayed to display an image. Type laser microscope apparatus,
When the digital signal exceeds the upper limit of the range of the conversion means, extrapolation processing is performed based on the digital signal until the upper limit of the range is exceeded, and the digital signal at the time of reset is estimated. and wherein the digital signal controlling the photoelectric conversion means and / or said light intensity control means on the basis of the digital signal at the time of the reset is provided with a control means for controlling to be less than the range upper limit Scanning laser microscope apparatus. The control means further comprises counting means for counting the number of samplings of the digital signal,
The control means divides the number of samplings at the time of resetting by the number of samplings until the upper limit of the range is reached, and sets a value obtained by multiplying the value of the upper limit of the range by the value of the upper limit of the range. Item 2. A scanning laser microscope apparatus according to Item 1 . The scanning laser microscope apparatus according to claim 1 , wherein the control unit estimates the digital signal at the time of reset by a maximum likelihood estimation method. The scanning laser microscope apparatus according to claim 3 , wherein the maximum likelihood estimation method is a least square method.

Images