JP4606306B2 - Electronic camera - Google Patents

Description

  The present invention relates to an electronic camera, and more particularly, to an electronic camera that creates a single image by combining a plurality of partial images generated in a plurality of imaging regions.

  Another example of a conventional electronic camera of this type is disclosed in Patent Document 1. According to this prior art, the image sensor has a right channel and a left channel. Image information generated in the right region of the imaging surface is output from the right channel, and image information generated in the left region of the imaging surface is output from the left channel. The output image information is subjected to black level correction processing for each channel, and is subjected to gain correction processing so that the gain difference between channels is eliminated. In particular, the gain correction value is determined by paying attention to several pixels straddling the boundary between the right region and the left region. Thereby, it is possible to prevent the boundary line between the right region and the left region from appearing in the reproduced image.

In addition, conventional electronic cameras generally facilitate framing by using an optical viewfinder with a frame and crosshairs, or by displaying the frame and crosshairs on-screen on a through image on the LCD. I am trying.
JP 2002-252808 A [H04N 5/335, 5/16, G06T 1/00, H01L 27/148]

  However, in the related art, if an edge appears around the boundary between the right region and the left region, the gain correction value may deviate from the optimum value, and the appearance of the boundary line may not be effectively prevented. Even the boundary line that is invisible from the through image may greatly deteriorate the quality of the recorded image.

    Further, in the prior art, it is not easy to perform framing in a state where no finder is provided and no on-screen display is performed.

  Therefore, a main object of the present invention is to provide an electronic camera capable of facilitating framing and improving the quality of recorded images.

  An electronic camera (10) according to the invention of claim 1 includes an image pickup means (14) having an image pickup surface in which a plurality of partial image pickup areas that are in contact with each other by boundary lines extending in at least one of a horizontal direction and a vertical direction are formed. Adjustment means (28r, 28g, 28b, 54r) for adjusting the gain of each of the plurality of partial images captured in the region, and combining means (38 for combining a plurality of partial images having gains adjusted by the adjustment means with each other ), Display means (50, 52) for displaying the combined image created by the combining means, recording means (46, S13, S27) for recording the combined image created by the combining means when a recording instruction is issued, recording First control means (S1, S3) for controlling the adjustment operation of the adjustment means so that the gain difference between the plurality of partial images respectively captured in the plurality of partial imaging regions at a specific time corresponding to the recording operation of the means is reduced. , S21, S23), and special Timing and a second control means for controlling an adjustment operation of the adjusting means (S15) so that the gain difference between the plurality of partial images captured each of which is expanded in a plurality of partial imaging areas at different times.

  The imaging means has an imaging surface. The plurality of partial image areas formed on the imaging surface are in contact with each other by a boundary line extending in at least one of the horizontal direction and the vertical direction. The gains of the plurality of partial images respectively captured in the plurality of imaging regions are adjusted by the adjusting unit. The plurality of partial images having the adjusted gain are combined with each other by the combining means. The combined image created by the combining unit is displayed by the display unit. The combined image created by the combining means is also recorded by the recording means when a recording instruction is issued.

  The first control unit controls the adjustment operation of the adjustment unit so that the gain difference between the plurality of partial images captured in the plurality of partial imaging regions at a specific time corresponding to the recording operation of the recording unit is reduced. . The second control unit controls the adjustment operation of the adjustment unit so that the gain difference between the plurality of partial images captured in the plurality of partial imaging regions at a time different from the specific time is enlarged.

  Therefore, when the recording operation is not performed, the gain difference between the plurality of partial images is enlarged, and a combined image in which the boundary line clearly appears is displayed. This facilitates framing. Further, when the recording operation is performed, the gain difference between the plurality of partial images is reduced, and a combined image in which the boundary line is not conspicuous is recorded. This improves the quality of the recorded image.

  An electronic camera according to a second aspect of the present invention is dependent on the first aspect, wherein the adjustment means includes a suppression means (28r, 28g, 28b) for suppressing a gain difference between the plurality of partial images, and a suppression operation of the suppression means. An adding means (54r) for adding a gain difference to a plurality of partial images later is included, the first control means invalidates the adding means at a specific time, and the second control means enables the adding means at a time different from the specific time. .

  The gain difference between the plurality of partial images is suppressed by the gain suppressing unit, and after such suppression operation, the gain difference is added to the plurality of partial images by the adding unit. The adding means is invalidated at a specific time and is activated at a time different from the specific time.

  As a result, the gain difference between the plurality of partial images is reduced at a specific time, and the gain difference between the plurality of partial images is increased at a time different from the specific time.

  An electronic camera according to a third aspect of the invention is dependent on the second aspect, wherein the suppression means executes a suppression process based on the characteristic data, and the first control means has a plurality of partial images subjected to the suppression process by the suppression means. Detection means (S67) for detecting a gain difference between the two, a creation means (S53) for creating correction data based on the gain difference detected by the detection means, and a correction created by the creation means for the characteristic data of the suppression means Update means (S55) for updating based on the data is included.

  Thus, the detection means detects the gain difference between the plurality of partial images, the creation means creates correction data based on the detected gain difference, and the update means uses the created correction data as the suppression means. Since the characteristic data is updated, it is possible to follow the change over time in the gain difference. In addition, since the characteristic data is updated regardless of the specific time or other time, high followability can be obtained. Furthermore, by performing the adding operation of the adding unit after the suppressing operation of the suppressing unit, the influence of the additional operation on the characteristic data can be avoided and the quality degradation of the recorded image can be prevented.

  An electronic camera according to a fourth aspect of the present invention is dependent on the third aspect, wherein the plurality of partial images have color components of a plurality of colors, the detection means executes detection processing for each of the color components of the plurality of colors, and the characteristic data Defines a plurality of operating characteristics respectively corresponding to a plurality of colors.

  As a result, the gain difference between the plurality of partial images is suppressed for each color, and the appearance of the boundary line in the recorded image can be effectively prevented.

  An electronic camera according to a fifth aspect of the present invention is dependent on the fourth aspect, wherein the number of partial imaging areas formed on the imaging surface is 2, and the adding means has a plurality of colors for the partial image captured in one imaging area. The gain of any one of the color components is added.

  Since the color tone of one of the two partial images changes in the displayed combined image, the boundary line can be easily viewed.

  According to the present invention, it is possible to facilitate framing and improve the quality of recorded images.

  The above object, other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

  Referring to FIG. 1, a digital camera (electronic camera) 10 of this embodiment includes an optical lens 12. The optical image of the object scene is irradiated onto the imaging surface of the CCD imager 14 via the optical lens 12. The imaging surface is covered with a color filter 14f in which R (Red), G (Green), or B (Blue) filter elements are arranged in a Bayer manner.

  Therefore, the charge having R color information is generated by the R pixel, which is a light receiving element covered by the R filter element, and the charge having G color information is G, which is the light receiving element covered by the G filter element. A charge generated in the pixel and having B color information is generated in the B pixel which is a light receiving element covered by the B filter element.

  When a power-on operation is performed by the key input device 32, a TG (Timing Generator) 18 is activated by the CPU 30. The switch SW is initially set on the terminal T1 side. The CPU 30 sets the thinning readout mode to TG18. The TG 18 generates a plurality of timing signals including a horizontal synchronization signal Hsync and a vertical synchronization signal Vsync. Each of the drivers 16a and 16b drives the CCD imager 14 in response to the timing signal. As a result, an electric charge corresponding to one frame, that is, a raw image signal is output from the CCD imager 14 in a thinning manner every time the vertical synchronization signal Vsync is generated.

  Referring to FIG. 2, the imaging surface of CCD imager 14 has a left imaging area IML and a right imaging area IMR. The left imaging region IML is formed on the left side of the boundary line BL extending in the vertical direction from the center of the imaging surface, and the right imaging region IMR is formed on the right side of the same boundary line BL. That is, the left imaging area IML and the right imaging area IMR are in contact with each other at the boundary line BL.

  A plurality of vertical transfer registers (not shown) are assigned to each of the left imaging area IML and the right imaging area IMR. Further, a horizontal transfer register HL is assigned to the left imaging area IML, and a horizontal transfer register HR is assigned to the right imaging area IMR. Further, an amplifier APL is provided at the output end of the horizontal transfer register HL, and an amplifier APR is provided at the output end of the horizontal transfer register HR.

  Therefore, the charges generated by the plurality of light receiving elements on the left imaging region IML are output from the channel CH1 via the vertical transfer register, the horizontal transfer register HL, and the amplifier APL (not shown). Similarly, the charges generated by the plurality of light receiving elements on the right imaging region IMR are also output from the channel CH2 via a vertical transfer register, a horizontal transfer register HR, and an amplifier APR (not shown).

  That is, the driver 16a performs raster scanning on the left imaging region IML based on the timing signal from the TG 18, and outputs a left half frame raw image signal from the channel CH1. Similarly, the driver 16b performs raster scanning on the right imaging region IMR based on the timing signal from the TG 18, and outputs the raw image signal of the right half frame from the channel CH2.

  However, the transfer direction of the horizontal transfer register HR is opposite to the transfer direction of the horizontal transfer register HL. For this reason, the raster scanning direction is also reversed between the left imaging area IML and the right imaging area IMR.

  The CDS / AGC / AD circuit 20a performs a series of processes of correlated double sampling, automatic gain adjustment, and A / D conversion on the raw image signal of the channel CH1. Similarly, the CDS / AGC / AD circuit 20b performs a series of processes of correlated double sampling, automatic gain adjustment, and A / D conversion on the raw image signal of the channel CH2. Note that the CDS / AGC / AD circuits 20a and 20b also perform the above-described processing in synchronization with the timing signal output from the TG 18.

  The clamp circuit 22 a matches the reference level of the raw image data output from the CDS / AGC / AD circuit 20 a with the black level set by the level adjustment circuit 24. Similarly, the clamp circuit 22 b adjusts the reference level of the raw image data output from the CDS / AGC / AD circuit 20 b to the black level set by the level adjustment circuit 24.

The raw image data output from the clamp circuit 22 a is written into the SDRAM 36 by the memory control circuit 38. The raw image data output from the clamp circuit 22b undergoes R component gain adjustment by a LUT (Look Up Table) 28r, G component gain adjustment by the LUT 28g, and B component gain adjustment by the LUT 28b, and then the memory control circuit 38. Is written in the SDRAM 36.

  As shown in FIG. 3, the SDRAM 36 has a raw image area 36a, a YUV image area 36b, a compressed image area 36c, and a display image area 36d. The memory control circuit 38 stores the raw image data of the channel CH1 on the left side of the raw image region 36a, and stores the raw image data of the channel CH2 on the right side of the raw image region 36a. The raw image data stored in the raw image area 36a in this way represents a captured one-field scene image. Further, the gain adjustment by the LUTs 28r, 28g, and 28b eliminates the gain difference of the raw image data between the channels CH1 and CH2, and prevents the appearance of the boundary line.

  The raw image data output from each of the clamp circuits 22a and 22b is represented by 12 bits. Therefore, each of the LUTs 28r, 28g, and 28b has 4096 set values.

  The post-processing circuit 40 reads out such raw image data from the SDRAM 36 through the memory control circuit 38, performs processing such as color separation and YUV conversion on the read raw image data, and performs memory control on the YUV format image data. The display image area 36d is written through the circuit 38.

  The video encoder 50 reads YUV format image data from the SDRAM 36 through the memory control circuit 38, converts the read YUV format image data into a composite video signal conforming to the NTSC system, and converts the converted composite video signal to the LCD monitor 52. To give. As a result, a real-time moving image (through image) of the object scene is displayed on the monitor screen.

  When a photographing operation is performed by the key input device 32, the CPU 30 cancels the thinning readout mode set in the TG 18. Thereby, the reading operation of the raw image signal from the CCD imager 14 is switched from the thinning-out reading mode to the all-pixel reading mode. Even after the reading mode is switched, the processing similar to the above is performed in the processing system from the CCD imager 14 to the post-processing circuit 40.

  That is, the left half frame raw image signal is output from the channel CH1, and the right half frame raw image signal is output from the channel CH2. In the CDS / AGC / AD circuit 20a, a series of processes of correlated double sampling, automatic gain adjustment, and A / D conversion are performed on the raw image signal of the channel CH1. In the CDS / AGC / AD circuit 20b, the same processing is performed on the raw image signal of the channel CH2.

  The clamp circuit 22 a matches the reference level of the raw image data output from the CDS / AGC / AD circuit 20 a with the black level set by the level adjustment circuit 24. Similarly, the clamp circuit 22 b adjusts the reference level of the raw image data output from the CDS / AGC / AD circuit 20 b to the black level set by the level adjustment circuit 24.

  The raw image data output from the clamp circuit 22 a is written into the SDRAM 36 by the memory control circuit 38. The raw image data output from the clamp circuit 22b is written into the SDRAM 36 by the memory control circuit 38 after gain adjustment by the LUTs 28r, 28g and 28b.

  The post-processing circuit 40 reads such raw image data from the SDRAM 36 through the memory control circuit 38, and performs processing such as color separation and YUV conversion on the read raw image data. However, the writing destination of the image data in the YUV format by the post-processing circuit 40 is not the display image area 36d but the YUV image area 36b.

  The JPEG codec 42 reads the image data thus stored in the YUV image area 36b through the memory control circuit 38, performs JPEG compression on the read image data, and passes the compressed image data through the memory control circuit 38 to the compressed image area 36c. Write to. Such a compression operation is executed every time the vertical synchronization signal Vsync is generated.

  The CPU 30 reads the compressed image data stored in the compressed image area 36 c through the memory control circuit 38 and records the read compressed image data on the recording medium 46 through the I / F 44. Thus, a moving image file containing a plurality of frames of compressed image data is formed on the recording medium 46.

  Here, the gain adjustment by the LUTs 28r, 28 and 28b will be described in detail. Referring to FIG. 4, when the R component, G component, and B component of the raw image data of channel CH1 input to clamp circuit 22a draw curves C1rin, C1gin, and C1bin with respect to the incident light amount, respectively, from clamp circuit 22a The R component, G component, and B component of the output raw image data of the channel CH1 draw curves C1rout, C1gout, and C1bout with respect to the incident light amount, respectively. Further, when the R component, G component, and B component of the raw image data of the channel CH2 input to the clamp circuit 22b draw curves C2rin, C2gin, and C2bin with respect to the incident light amount, the channel CH2 output from the clamp circuit 22b. The R component, G component, and B component of the raw image data of FIG.

  Due to the difference in amplification characteristics of the amplifiers APL and APR, the black level and gain of the raw image data also differ between the channels CH1 and CH2. Of these, the black level shift is eliminated by the clamp circuits 22 a and 22 b and the level adjustment circuit 24. According to FIG. 4, a plurality of level ranges LV1 to LV4 are assigned to the dynamic range of the raw image data.

  The gain shift between the channels CH1 and CH2 is eliminated in the following manner. The raw image data output from the clamp circuit 22a is applied to the block arithmetic circuit 26a, and the raw image data output from the clamp circuit 22b is applied to the block arithmetic circuit 26b. Referring to FIG. 5, the block arithmetic circuit 26 a performs, for each small image belonging to each of the boundary blocks B <b> 1 </ b> L, B <b> 2 </ b> L,. And an average value for each color of the image level. For the small images belonging to the boundary blocks B1R, B2R,. Find the average value for each color.

  Specifically, each of the block arithmetic circuits 26a and 26b is configured as shown in FIG. The raw image data output from the clamp circuit 22a or 22b is given to the block extraction circuit 60. The block extraction circuit 60 extracts raw image data belonging to each of the boundary blocks B1L to BnL or each of the boundary blocks B1R to BnR.

  The R difference value calculation circuit 62 calculates an R difference value that is a difference value between adjacent R pixels in the extracted raw image data. The G difference value calculation circuit 64 calculates a G difference value that is a difference value between adjacent G pixels in the extracted raw image data. The B difference value calculation circuit 66 calculates a B difference value that is a difference value between adjacent B pixels in the extracted raw image data.

The integration circuit 68 integrates the absolute value of the calculated R difference value for each boundary block, the integration circuit 70 integrates the calculated absolute value of the G difference value for each boundary block, and the integration circuit 72 is calculated. The absolute value of the B difference value is integrated for each boundary block. As a result, integrated values Rh, Gh and Bh corresponding to the same boundary block are output from the integrating circuits 68, 70 and 72, respectively.

  The R average value calculation circuit 74 averages the R pixel levels in the raw image data from the block extraction circuit 60 for each boundary block, and the G average value calculation circuit 76 in the raw image data from the block extraction circuit 60. The level of the G pixel is averaged for each boundary block, and the B average value calculation circuit 78 averages the level of the B pixel in the raw image data from the block extraction circuit 60 for each boundary block. As a result, average values Rav, Gav, and Bav corresponding to the same boundary block are output from the R average value calculation circuit 74, the G average value calculation circuit 76, and the B average value calculation circuit 78, respectively.

  Returning to FIG. 1, each of the block arithmetic circuits 26 a and 26 b gives the integrated values Rh, Gh, Bh and average values Rav, Gav, Bav thus calculated to the CPU 30. First, the CPU 30 determines whether or not the small images of the two boundary blocks BKL and BKR (K: 1 to n) adjacent to each other are flat.

  If the integrated value Rh obtained in each of the two boundary blocks of interest is less than the threshold value TH, it is determined that the R component of the small image belonging to these boundary blocks is flat. If the integrated value Gh obtained in each of the two boundary blocks of interest is less than the threshold value TH, it is determined that the G component of the small image belonging to these boundary blocks is flat. If the integrated value Bh obtained in each of the two boundary blocks of interest is less than the threshold value TH, it is determined that the B component of the small image belonging to these boundary blocks is flat.

  The CPU 30 calculates the difference value ΔRav based on the two average values Rav obtained from the two boundary blocks determined that the R component is flat. Further, a difference value ΔGav is calculated based on two average values Gav respectively obtained from two boundary blocks determined that the G component is flat. Further, a difference value ΔBav is calculated based on two average values Bav respectively obtained from two boundary blocks determined that the B component is flat.

  The difference value ΔRav is obtained by subtracting the average value Rav of the boundary block BKR from the average value Rav of the boundary block BKL, and the difference value ΔGav is obtained by subtracting the average value Gav of the boundary block BKR from the average value Gav of the boundary block BKL. The difference value ΔBav is obtained by subtracting the average value Bav of the boundary block BKR from the average value Bav of the boundary block BKL.

  The difference values ΔRav, ΔGav, ΔBav obtained in this way and the average values Rav, Gav, Bav obtained from the boundary book BKR are written in the register 34 shown in FIG. According to FIG. 7, five columns are assigned to each of the level areas LV1 to LV4. Each of the average values Rav, Gav, and Bav is written in the level area column to which the average value belongs in order from the smallest numerical value. The difference values ΔRav, ΔGav, ΔBav are assigned to the associated average values Rav, Gav, Bav, respectively.

  For example, if the average values Rav, Gav and Bav of the boundary block BKR belong to the level ranges LV3, LV4 and LV1, respectively, the average value Rav and the difference value ΔRav associated therewith are written in the column of the level range LV3 of the register 34, The average value Gav and the difference value ΔGav related thereto are written in the column of the level area LV4 of the register 34, and the average value Bav and the difference value ΔBav related thereto are written in the column of the level area LV1 of the register 34.

  When all the columns of the register 34 are filled with numerical values, the register 34 is completed. The CPU 30 creates an R correction data by performing an interpolation operation on the 20 difference values ΔRav written in the register 34, and performs an interpolation operation on the 20 difference values ΔGav written in the register 34 to obtain the G correction data. The B correction data is generated by performing an interpolation operation on the 20 difference values ΔBav created and written in the register 34.

  The R, G, and B components of the raw image data of the channel CH1 output from the clamp circuit 22a draw the curves C1rout, C1gout, and C1bout shown in FIG. 4, and the raw image data of the channel CH2 output from the clamp circuit 22b When the curves C2rout, C2gout, and C2bout shown in FIG. 4 are drawn, the R correction data, the G correction data, and the B correction data draw the curves Cr, Cg, and Cb shown in FIG. 8, respectively.

  Each of the curves Cr, Cb, and Cg shows how the difference image data obtained by subtracting the raw image data of the channel CH2 from the raw image data of the channel CH1 changes with respect to the raw image data of the channel CH2. Equal to the characteristic curve shown.

  The CPU 30 adds the value of the R correction data to the default setting value of the LUT 28r, adds the value of the G correction data to the default setting value of the LUT 28g, and adds the value of the B correction data to the default setting value of the LUT 28b.

  When the default setting value of the LUT 28r, the default setting value of the LUT 28g, and the default setting value of the LUT 28b draw the curves TSr, TSg, and TSb shown in FIG. 9 with respect to the output of the clamp circuit 22b, the R correction data and G correction data described above are used. When the B correction data and the B correction data are added, the set value of the LUT 28r, the set value of the LUT 28g, and the set value of the LUT 28b respectively draw the curves TMr, TMg, and TMb shown in FIG. As a result, the gains of the raw image data are substantially the same between the channels CH1 and CH2.

  When the boundary display mode ON operation is performed by the key input device 32, the CPU 30 switches the switch SW to the terminal T2 side. As a result, the R gain addition processing by the R gain addition circuit 54r is executed after the gain adjustment processing by the LUTs 28r, 28g and 28b as described above. In the R gain addition processing, an R component gain is added to the raw image data of the channel CH2. As a result, the reproduced image on the channel CH2 side is reddish, and a clear boundary line that bisects the monitor screen vertically appears. By using such a boundary line as a reference, accurate framing with little inclination can be easily performed.

  Subsequently, when a photographing operation is performed, the CPU 30 switches the switch SW to the terminal T1 side, and executes photographing processing and recording processing. As a result, an image with inconspicuous boundaries is recorded on the recording medium 46. After recording, the CPU 30 switches the switch SW to the terminal T2 side. As a result, a through image having a clear boundary line is displayed again on the LCD monitor 52.

  When the boundary display mode off operation is performed by the key input device 32, the CPU 30 switches the switch SW to the terminal T1 side. As a result, the boundary line in the through image disappears.

  The CPU 30 executes the main task shown in FIG. 10 and the table update task shown in FIGS. 11 and 12 in parallel under the control of a multitask OS such as μITRON. The control program corresponding to these flowcharts is stored in the flash memory 48.

  Referring to FIG. 10, when a power-on operation is performed by key input device 32, an initial process is first executed in step S1. The initial processing includes processing such as activation of the TG 18, setting of a thinning readout mode to the TG 18, and setting of the switch SW to the terminal T 1 side. When the initial process is completed, the process proceeds to step S3 to start a table update task. In subsequent step S5, a through shooting start command is issued.

  When a through shooting start command is issued, the TG 18 starts an operation for generating a plurality of timing signals. The driver 16a performs raster scanning on the left imaging area IML (see FIG. 2) based on the timing signal, and outputs the left half frame raw image signal from the channel CH1 in a thinning manner. Similarly, the driver 16b performs raster scanning on the right imaging region IMR based on the timing signal, and outputs the right half frame raw image signal from the channel CH2 in a thinning manner.

  The CDS / AGC / AD circuit 20a performs a series of processes of correlated double sampling, automatic gain adjustment, and A / D conversion on the raw image signal of the channel CH1. The CDS / AGC / AD circuit 20b performs the same series of processing on the raw image signal of the channel CH2. The clamp circuit 22 a matches the reference level of the raw image data output from the CDS / AGC / AD circuit 20 a with the black level set by the level adjustment circuit 24. Similarly, the clamp circuit 22 b adjusts the reference level of the raw image data output from the CDS / AGC / AD circuit 20 b to the black level set by the level adjustment circuit 24.

  The raw image data output from the clamp circuit 22 a is written into the SDRAM 36 by the memory control circuit 38. The raw image data output from the clamp circuit 22b is written into the SDRAM 36 by the memory control circuit 38 after the gains of the R component, G component, and B component are adjusted by the LUTs 28r, 28g, and 28b.

  The raw image data of the channel CH1 is stored on the left side of the raw image region 36a, and the raw image data of the channel CH2 is stored on the right side of the raw image region 36a. The gain difference of the raw image data between the channels CH1 and CH2 is eliminated by the gain adjustment by the LUTs 28r, 28g, and 28b.

  The post-processing circuit 40 reads raw image data from the SDRAM 36 through the memory control circuit 38, performs processing such as color separation and YUV conversion on the read raw image data, and passes the YUV format image data through the memory control circuit 38. Write to the display image area 36d.

  The video encoder 50 reads YUV format image data from the SDRAM 36 through the memory control circuit 38, converts the read YUV format image data into a composite video signal conforming to the NTSC system, and converts the converted composite video signal to the LCD monitor 52. To give. In this way, a through image is displayed on the LCD monitor 52.

  After the through shooting command is issued, the processing of the CPU 30 enters a loop of steps S7 and S9. In step S7, the presence / absence of a photographing operation is determined. In step S9, the presence / absence of a boundary display mode on operation is determined. When a photographing operation is performed by the key input device 32, YES is determined in a step S7, and the process proceeds to a step S11 to issue a photographing command.

  In response to the shooting command, the all-pixel readout mode is set in the TG 18. The driver 16a performs raster scanning on the left imaging area IML based on the timing signal from the TG 18, and outputs the left half frame raw image signal from the channel CH1 in a manner of reading all pixels. Similarly, the driver 16b performs raster scanning on the right imaging region IMR based on the timing signal from the TG 18, and outputs the raw image signal of the right half frame from the channel CH2 in an all-pixel reading manner.

  In the processing system from the CCD imager 14 to the post-processing circuit 40, processing similar to that in the case of thinning readout is performed. However, the post-processing circuit 40 writes YUV format image data not in the display image area 36d but in the YUV image area 36b. The JPEG codec 42 reads the image data stored in the YUV image area 36b through the memory control circuit 38, performs JPEG compression on the read image data, and passes the compressed image data to the compressed image area 36c through the memory control circuit 38. Write.

  When the writing of the compressed image data to the SDRAM 36 is completed, the CPU 30 executes a recording process in step S13. Specifically, the compressed image data stored in the compressed image area 36 c is read through the memory control circuit 38, and the read compressed image data is recorded on the recording medium 46 through the I / F 44. Thus, a moving image file containing a plurality of frames of compressed image data is formed on the recording medium 46. When the recording process is completed, the process returns to step S5.

  When the boundary display mode ON operation is performed by the key input device 32, YES is determined in the step S9, the process proceeds to a step S15, and the switch SW is set to the terminal T2 side. After the setting, a loop of steps S17 and S19 is entered. In step S17, the presence / absence of a photographing operation is determined. In step S19, the presence / absence of a border display mode off operation is determined.

  When a photographing operation is performed by the key input device 32, YES is determined in the step S17, and the process proceeds to a step S23 to set the switch SW to the terminal T1 side. After setting, a shooting command is issued in step S25, and recording processing is executed in step S27. When the recording process is completed, a through shooting start command is issued in step S29, and the process returns to step S15.

  When the boundary display mode off operation is performed by the key input device 32, the switch SW is set to the terminal T1 side in step S21, and the process returns to step S5.

  The table update task follows the flowchart of FIG. Referring to FIG. 11, first, register 34 is cleared in step S41, and variable K is set to “0” in step S43. In step S45, it is determined whether or not the vertical synchronization signal Vsync has been generated. If YES, the variable K is incremented in step S47. In step S49, it is determined whether or not the variable K exceeds a predetermined value n. If “NO” here, the process proceeds to a step S57, and if “YES”, the process proceeds to a step S51.

  Referring to FIG. 12, in step S57, the integrated values Rh, Gh, Bh of the boundary block BKL are taken from the block arithmetic circuit 26a, and in step S59, the integrated values Rh, Gh, Bh of the boundary block BKR are taken from the block arithmetic circuit 26b.

  In step S61, it is determined whether or not the two acquired integrated values Rh satisfy the flatness condition. Specifically, it is determined whether or not both of the two integrated values Rh that have been taken are less than the threshold value TH. If this flatness condition is not satisfied, it is assumed that at least one of the small image reproduced by the R component belonging to the boundary block BKL and the small image reproduced by the R component belonging to the boundary block BKR is not a flat image, step S47. Proceed to On the other hand, if this condition is satisfied, the small image reproduced by the R component belonging to each of the boundary blocks BKL and BKR is regarded as a flat image, and the process proceeds to step S63.

  In step S63, the average values Rav, Gav, Bav of the boundary block BKL are taken from the block arithmetic circuit 26a, and in step S65, the average values Rav, Gav, Bav of the boundary block BKR are taken from the block arithmetic circuit 26b. In step S67, the difference value ΔRav is calculated by subtracting the average value Rav of the boundary block BKR from the average value Rav of the boundary block BKL, and the difference is obtained by subtracting the average value Gav of the boundary block BKR from the average value Gav of the boundary block BKL. A value ΔGav is calculated, and a difference value ΔBav is calculated by subtracting the average value Bav of the boundary block BKR from the average value Bav of the boundary block BKL.

  In step S69, the range to which the average value Rav of the boundary block BKR belongs is detected, and the difference values ΔRav, ΔGav, ΔBav and the average values Rav, Gav, Bav of the boundary block BKR are associated with the detected range and written to the register 34. When the writing is completed, the process returns to step S47.

  Returning to FIG. 11, if YES is determined in the step S49, it is determined whether or not the register 34 is completed in a step S51. The register 34 is completed when numerical values are written in all the columns. If NO is determined here, the process returns to step S45, and if YES is determined, the process proceeds to step S53.

  In step S53, R correction data is created by interpolation calculation of the difference value ΔRav set in the register 34, G correction data is created by interpolation calculation of the difference value ΔGav set in the register 34, and is set in the register 34. B correction data is created by interpolation of the difference value ΔBav.

  In step S55, the created R correction data is added to the default setting value of the LUT 28r, the created G correction data is added to the default setting value of the LUT 28g, and the created B correction data is set to the default setting value of the LUT 28b. to add. When the process of step S55 is completed, the process returns to step S41.

  As can be seen from the above description, in this embodiment, the image sensor 12 includes an imaging surface on which two partial imaging regions IML and IMR for generating two partial images are formed, and two partial imaging regions IML and IMR, respectively. Have two channels CH1 and CH2, respectively. The gain difference between the two partial images output from the two channels CH1 and CH2 is suppressed by the LUTs 28r, 28g, and 28b. The two partial images having the suppressed gain difference are combined with each other by the memory control circuit 38.

  The CPU 30 determines whether or not the two partial images subjected to the suppression process satisfy the flatness condition (S61). If the determination result is affirmative, the CPU 30 detects a gain difference between the plurality of partial images subjected to suppression processing (S67), and operates the LUTs 28r, 28g, and 28b based on the detected gain difference. Correct the characteristics (S55).

  By correcting the operation characteristics of the LUTs 28r, 28g, and 28b, it is possible to prevent the appearance of a boundary line due to a change over time. In addition, by paying attention to the gain difference detected when the flatness condition is satisfied, the operation characteristics can be accurately corrected. That is, it is possible to effectively prevent the appearance of an image boundary line.

  The R correction data, G correction data, and B correction data for correcting the LUTs 28r, 28g, and 28b, respectively, are a plurality of gain differences corresponding to a plurality of ranges LV1 to LV4 allocated on the dynamic range of the raw image data. Created based on As a result, the LUTs 28r, 28g, and 28b can be accurately corrected.

  In this embodiment, a boundary display mode is prepared in which a boundary line appears in the through image displayed on the LCD monitor 52. The above-described gain difference suppression is performed regardless of whether the boundary display mode is on. When the boundary display mode is turned on, processing for adding the gain of the R component (R gain addition processing) is applied to the channel CH2 image after gain difference suppression through the R gain addition circuit 54r (S15). Thereby, the channel CH2 image is reddish, and the boundary line is easily visible. The operator can easily perform framing by using such a boundary line.

  When a photographing operation is performed in this state, the R gain addition process is interrupted (S21, S23), and a combined image in which the boundary line is not conspicuous is recorded on the recording medium 46. When the recording is completed, the R gain addition process is resumed, and a through image having a clear boundary line is displayed.

  In this embodiment, the R component gain is added to the channel CH2 image in the boundary display mode on state. However, even if the G component gain is added to the channel CH2 image, the B component gain is added to the channel CH2 image. It may be added. Any two of R component gain, G component gain, and B component gain may be added, or all three may be added. The gain to be added may be different for each component and may be a negative value. In either method, the color tone or luminance of the channel CH2 image changes, and the boundary line can be easily viewed.

  In this case, in addition to the R gain addition circuit 54r, a G gain addition circuit and / or a B gain addition circuit (not shown) are provided in the subsequent stage of the LUTs 28r, 28g, and 28b. The color tone of the channel CH2 image may be changed according to preference or the color of the object scene by turning on / off each circuit or increasing / decreasing the gain added by each circuit.

  In this embodiment, gain is added to the channel CH2 image at the subsequent stage of the LUTs 28r, 28g, and 28g. However, gain addition can also be performed at the previous stage. However, in this case, there is a possibility that the LUTs 28r, 28g, and 28g are affected by gain addition, and the suppression of the boundary line of the recorded image becomes temporarily insufficient.

  In this embodiment, as the flatness condition, it is required that each of the integrated values Rh, Gh, and Bh obtained by two boundary blocks adjacent to each other is less than a threshold value. However, instead of this, as a flatness condition, it is required that each of sums (Rh + Rh, Gh + Gh, Bh + Bh) of integrated values obtained in two adjacent boundary blocks is less than a threshold value. Also good.

  In this embodiment, the clamp process is performed prior to the gain adjustment process by the LUTs 28r, 28g, and 28b. However, the clamp process may be performed after the gain adjustment process.

  Furthermore, in this embodiment, the processing after step S63 shown in FIG. 12 is not executed unless all of the integration values Rh, Gh, and Bh are below the threshold value. However, the processing after step S63 may be executed for each color.

  In the above description, the digital camera 10 in which the number of partial imaging areas is 2 has been described. However, the present invention can be applied to a digital camera in which the number of partial imaging areas is 3 or more. That is, generally, a plurality of partial imaging areas may be formed on the imaging surface. The plurality of partial imaging regions are in contact with each other by a boundary line extending in at least one of the horizontal direction and the vertical direction. When the boundary display mode is turned on, a combined image in which such a boundary line clearly appears is displayed on the monitor screen. When the recording operation is performed, a combined image in which such a boundary line is not conspicuous is recorded on the recording medium.

It is a block diagram which shows the structure of one Example of this invention. It is an illustration figure which shows an example of a structure of the image sensor applied to FIG. 1 Example. It is an illustration figure which shows an example of the mapping state of SDRAM applied to FIG. 1 Example. It is a graph which shows a part of operation | movement of the clamp circuit applied to FIG. 1 Example. It is an illustration figure which shows a part of operation | movement of FIG. 1 Example. It is a block diagram which shows an example of a structure of the block arithmetic circuit applied to the FIG. 1 Example. FIG. 3 is an illustrative view showing one example of a configuration of a register applied to the embodiment in FIG. 1; It is a graph which shows another part of operation | movement of FIG. 1 Example. It is a graph which shows a part of other operation | movement of FIG. 1 Example. It is a flowchart which shows a part of operation | movement of CPU applied to the FIG. 1 Example. It is a flowchart which shows a part of other operation | movement of CPU applied to the FIG. 1 Example. It is a flowchart which shows a part of other operation | movement of CPU applied to the FIG. 1 Example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Digital camera 14 ... Image sensor 26a, 26b ... Block arithmetic circuit 28r, 28g, 28b ... LUT
30 ... CPU
34 ... Register 46 ... Recording medium 52 ... LCD monitor 54r ... R gain addition circuit

Claims (5)

An imaging unit having an imaging surface in which a plurality of partial imaging regions that are in contact with each other by a boundary line extending in at least one of the horizontal direction and the vertical direction;
Adjusting means for adjusting the gain of each of the plurality of partial images respectively captured in the plurality of imaging regions;
Combining means for combining a plurality of partial images having gains adjusted by the adjusting means;
Display means for displaying a combined image created by the combining means;
Recording means for recording the combined image created by the combining means when a recording instruction is issued;
First control means for controlling the adjustment operation of the adjustment means so as to reduce the gain difference between the plurality of partial images respectively captured in the plurality of partial imaging regions at a specific time corresponding to the recording operation of the recording means. And a second control means for controlling the adjusting operation of the adjusting means so that the gain difference between the plurality of partial images captured in the plurality of partial imaging regions at a time different from the specific time is enlarged. , Electronic camera. The adjustment unit includes a suppression unit that suppresses a gain difference between the plurality of partial images, and an adding unit that adds a gain difference to the plurality of partial images after a suppression operation of the suppression unit,
The first control means invalidates the adding means at the specific time,
The electronic camera according to claim 1, wherein the second control unit activates the adding unit at a time different from the specific time. The suppression means executes a suppression process based on the characteristic data,
The first control unit detects a gain difference between a plurality of partial images subjected to suppression processing by the suppression unit, and creates correction data based on the gain difference detected by the detection unit The electronic camera according to claim 2, further comprising: updating means for updating the characteristic data of the means and the suppression means based on the correction data created by the creating means. The plurality of partial images have a plurality of color components,
The detection means executes detection processing for each of the color components of the plurality of colors,
The electronic camera according to claim 3, wherein the characteristic data defines a plurality of operation characteristics respectively corresponding to the plurality of colors. The number of partial imaging areas formed on the imaging surface is 2,
The electronic camera according to claim 4, wherein the adding unit adds a gain of any one color component of the plurality of colors to a partial image captured in one imaging region.

Images