JP4609038B2 - Reception synchronization signal generator - Google Patents

Description

The present invention is incorporated into household electrical appliances or the like, and relates to the received synchronization signal generating device of a wireless communication system for constructing a home communication network.

  In recent years, white appliances such as air conditioners and refrigerators and security devices such as human sensors are connected to a home controller installed in the home, and connected to a mobile phone via the home controller. In-home network systems have been developed that control devices such as the Internet and notify security information in a home to a home away from home via a mobile phone.

  In order to receive a signal exchanged in the home network system, it is necessary to generate a reception synchronization signal called a sampling clock from the reception signal in order to correctly recognize a data string of the reception signal. As such a sampling clock generation method, there is a method disclosed in Patent Document 1.

  FIG. 9 is a block diagram showing a configuration of a clock signal extraction circuit which is an example of a conventional reception synchronization signal generator.

  The phase comparator 1, the loop filter 2 and the VCO 3 in FIG. 9 are part of the PLL circuit and have a function of generating a bit synchronous clock signal. A phase difference voltage conversion circuit 4 and a phase shifter circuit 5 are cascaded on the output side of the phase comparator 1, and an output signal of the VCO 3 is supplied to the phase shifter circuit 5 from the phase shifter circuit 5 to obtain a sampling clock for data sampling. It is configured to take out.

  The phase comparator 1 compares the received signal with the clock phase of the VCO 3 to detect a phase difference signal, and the loop filter 2 applies a predetermined frequency band limitation to the detected phase difference signal. The oscillation frequency of the VCO 3 is controlled by the output signal from the loop filter 2. The tracking speed with respect to the phase change of the PLL circuit is adjusted by the loop filter 2.

Here, as shown in FIG. 10, if there is a phase difference between the received signal 101 and the output signal 102 of the VCO 3, the phase difference is detected by the phase comparator 1, and the detected phase difference is detected as the phase difference. The phase difference voltage 103 is input to the phase shifter circuit 5 through the voltage conversion circuit 4. This phase difference voltage conversion circuit 4 has a voltage smoothing function that allows the phase shifter circuit 5 to stably operate the phase difference signal output from the phase comparator 1, and a conversion coefficient adjustment function that adjusts the amount of voltage change. And have. The phase shifter circuit 5 generates a signal (sampling clock 104 in FIG. 10) obtained by shifting the phase of the bit synchronization clock 102 from the VCO 3 in accordance with the phase difference voltage 103. The sampling clock 104 is a reception synchronization signal for capturing reception data.
Japanese Patent Laid-Open No. 06-31155

  The conventional configuration requires a PLL circuit and includes an analog circuit, so that there is a problem that mass production at low cost is difficult.

  Furthermore, since synchronization takes time, there is a problem that a long preamble is required before data.

  The present invention solves the above-described conventional problems, and with a simple configuration, the length of 1 bit from the rising edge to the falling edge of the received signal is different from the length of 1 bit from the falling edge to the rising edge in a short time. It is an object of the present invention to provide a reception synchronization signal generator that can accurately capture a 1-bit long center position.

  Rising change point detecting means for detecting a rising change point of a signal, falling change point detecting means for detecting a falling change point of the signal, and time measurement at the rising timing of the signal detected by the rising change point detecting means And start time measurement at the falling timing of the signal detected by the falling change point detecting means, or start time measurement at the falling timing of the signal detected by the falling change point detecting means, and detect the rising change point. Generating a sampling clock using two of the pulse width measuring means for ending the time measurement at the rising timing of the signal detected by the means, the rising timing or falling timing information, and the measuring time information measured by the pulse width measuring means This is a configuration of clock generation means for determining the position.

  As a result, the center position of each bit of the received signal can be captured in a short time with a simple configuration.

  By using the reception synchronization signal generator and program of the present invention, it is possible to capture the center position of each bit of the reception signal in a short time.

  According to a first aspect of the invention, there is provided a rising change point detecting means for detecting a rising change point of a signal, a falling change point detecting means for detecting a falling change point of the signal, and a signal detected by the rising change point detecting means. Time measurement starts at the rise timing of the signal and ends time measurement at the fall timing of the signal detected by the falling change point detection means, or starts time measurement at the fall timing of the signal detected by the falling change point detection means The pulse width measuring means for ending the time measurement at the rising timing of the signal detected by the rising change point detecting means, the rising timing or falling timing information, and the measuring time information measured by the pulse width measuring means. By using the clock generation means that determines the generation position of the sampling clock, the bit of each bit of the received signal can be shortened with a simple configuration. It is possible to take in the centers position.

  According to a second aspect of the present invention, as a rising change point detecting means or a falling change point detecting means, an adder group comprising a slot group consisting of a plurality of time slots and an adder corresponding to 1: 1 for each time slot. And change point output means that operates in accordance with the output of the adder group, and changes the value of the adder connected to the time slot corresponding to the timing at which the change of the signal occurs by one, and the addition When the value of any one adder in the group becomes a predetermined value, an output indicating a change point at the timing of the time slot corresponding to the adder having the predetermined value is output from the change point output means. Since it is configured to output, the center position of each bit of the received signal can be accurately captured in a short time with a simple configuration.

  According to a third aspect of the present invention, as detection output generating means, when the value of any one adder in the adder group reaches a predetermined value, detection of a change point is output and all the adders in the adder group are added. Since the control is performed so that the value of the device is reset to a predetermined value, it is possible to prevent the reception synchronization signal from being disturbed by noise.

  According to a fourth aspect of the present invention, the sampling period of the clock generation means for determining the generation position of the sampling clock is such that the first timer means for starting the operation at a predetermined timing, the change point detection means for detecting the change point of the received signal, A second timer means for measuring the time from the change point detected by the change point detection means to the next change point, and whether the time measured by the second timer means is within a predetermined range. A determination means, a counter means for counting up when the measurement time is within the predetermined range by the determination means, and reading from the first timer means when the count value of the counter means reaches a predetermined value The configuration is set based on the transmission rate determined by the configuration including the transmission rate determining means for determining the transmission rate based on the timer value. Ri, it is possible to determine the frequency of the received synchronization signal with a simple configuration.

  According to a fifth aspect of the present invention, the predetermined sampling period of the clock generation means for determining the generation position of the sampling clock is the first timer means for starting the operation at a predetermined timing, and the change point detection for detecting the change point of the received signal. Means, second timer means for measuring the time from the change point detected by the change point detection means to the next change point, and whether the time measured by the second timer means is within a predetermined range. A determination means for determining, a counter means for counting up when the measurement time is within the predetermined range by the determination means, and a counter means for clearing the count value when the measurement time is not within the predetermined range; A transmission speed for determining a transmission speed based on the timer value read from the first timer means when the count value of the counter means reaches a predetermined value. With the construction set the transmission rate determined by the configuration comprising a determining means on the basis of, you can determine the frequency of the received synchronization signal in a short time with a simple configuration.

  In the sixth aspect of the present invention, the circuit configuration can be further simplified by adopting a configuration for detecting only the rising or falling change point of the received signal as the change point detecting means.

  The seventh invention is characterized in that the initial value of the transmission rate of the transmission rate determining means is set to the lower limit value of the expected transmission rate, so that the operation until the frequency of the reception synchronization signal is determined is stable. Can be made.

  According to an eighth aspect of the invention, in the transmission rate determining means, the operation of the transmission rate determining means is stopped when the transmission rate is determined from the count value from the counter means and the timer value of the first timer means. As a result, it is possible to prevent the reception synchronization signal from fluctuating during data reception.

  In the ninth aspect of the present invention, the relationship between the expected first transmission rate A and the expected second transmission rate B of the received signal is B = (n + 1) A (n: natural number). The frequency can be easily determined.

  The tenth aspect of the invention is to configure the processing contents by a program so that all or part of the functions are realized by the computer, and since it is a program, it cooperates with hardware resources such as electrical / information equipment, computers, servers, etc. Thus, at least a part of the reception synchronization signal generator of the present invention can be easily realized. In addition, the program can be distributed / updated and installed easily by recording on a recording medium or distributing the program using a communication line.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that the present invention is not limited to the embodiments.

(Embodiment 1)
201 in FIG. 1 is a block diagram of a reception synchronization signal generator in the first embodiment of the present invention. In FIG. 1, reference numeral 11 denotes a receiving unit. The reception synchronization signal generating apparatus 201 includes a rising change point detecting unit 202, a falling change point detecting unit 203, a pulse width measuring unit 204, and a clock generating unit 205.

  When the rising change point detecting means 202 detects a rising change point of the received signal a demodulated by the receiving unit 11 and converted into a rectangular wave, that is, a change point at which the received signal changes from Low level to High level, The information b is output to the width measuring means 204.

  Similarly, the falling change point detecting means 203 detects a falling change point of the received signal demodulated by the receiving unit 11 and converted into a rectangular wave, that is, a change point where the received signal changes from the High level to the Low level. At that time, the information c is output to the pulse width measuring means 204.

  The pulse width measuring means 204 measures the time from the rising edge to the falling edge of the received signal using the two pieces of information.

  The clock generation means 205 determines the generation position of the sampling clock e using the time information d measured by the pulse width measurement means 204 and the rising timing information b detected by the rising change point detection means 202. .

  FIG. 2 is a block diagram showing the configuration of the rising change point detecting means 202 or the falling change point detecting means 203 in FIG.

  An example of the rising change point detection unit 202 will be described. In FIG. 2, 206 is a slot group composed of 32 time slots from 209 to 212, and 207 is an adder group composed of 32 adders from 213 to 216. Reference numeral 208 denotes change point output means for outputting rise timing information b.

  The operation of FIG. 2 will be described with reference to FIG. 3, (1) is a signal waveform of the received signal a, (2) is a time array of slot groups, (3) is a time array of adder groups, (4) is an added value of each adder, (5) Indicates timing information b.

  The slot group 206 includes 32 slots obtained by dividing one period of the received signal a into 32 equal parts. The operation will be described below.

  (A) The addition value of the adder corresponding to the slot is incremented one by one through the slot located at the rising time of the reception signal a. In the example of FIG. 3, the addition value (4) of the adder 2 corresponding to the slot 2 is incremented one by one.

  (B) When the added value (4) reaches a predetermined value (for example, 3), timing information b (501 in FIG. 3) is output at the timing of slot 2.

  (C) At the same time, the addition value (4) of all the adders is reset to zero, and the operation from (A) is repeated.

  (D) Until the addition value (4) of any adder in the adder group becomes 3 again, the timing information b is continuously output at the slot position where the previous addition value reached 3. In the example of FIG. 3, the timing information b is continuously output at the position of the slot 2 (502 and 503 in FIG. 3).

  FIG. 4 is a signal waveform diagram showing the relationship between the signal waveforms in FIG. (1) is the received signal b, (2) is the rise timing information b, (3) is the pulse width measurement information d, and (4) is the sampling clock e. The operation will be described below.

  (A) A sampling clock (e-1) is generated with a delay of Y time from timing information (b-1) generated at the rising timing of the received signal b (1 in FIG. 4). The default value of Y is 8 slots, which is 1/4 of 32 slots. Accordingly, the sampling clock (e-1) is delayed by 8 slots from the timing information (b-1).

  (B) The pulse width T1 of the received signal b is measured, and pulse width measurement information (d-1) is output at the falling timing.

  (C) The next sampling clock (e-2) is generated 16 slots later than (e-1).

  (D) When the pulse width measurement information (d-1) is T1 <2 × Y slot length, Y = (Y−Z) slot length. When the pulse width measurement information (d-1) satisfies T1> 2 × Y slot length, Y = (Y + Z) slot length. Here, Z = 1. In the example of FIG. 4, since T1 <2 × Y = 16 slots, the next sampling clock (e-3) is delayed by Y = (8-1) = 7 slots from the timing information (b-2). appear.

  (E) The next sampling clock (e-4) is delayed by 16 slots from (e-3) as in the case of (e-2).

  (F) Since the pulse width measurement information (d-2) is T2 <(2 × Y = 14) slot length, the next sampling clock (e-5) is calculated from the timing information (b-3) to Y = (7-1) = Occurs after 6 slots.

  With the above operation, the pulse width T of the received signal a converges to T≈2 × Y. That is, it converges so that the sampling clock e is generated at the center of the pulse width of the received signal a.

  Note that although Z = 1 slot length, the value of Z is not particular and Z = 2 may be used. If the value of Z is increased, the convergence time can be shortened, but the deviation between the position of the sampling clock e after convergence and the center of the pulse width of the received signal a becomes large.

  Therefore, it is also possible to use a method in which the value of Z is initially increased and the value of Z is switched to a smaller value, for example, 2 to 1, depending on a certain event. The certain event is, for example, after 32 × n slot time (n = 4) has elapsed since the rise timing information (b-1) occurred, or the pulse widths T and Y are within a predetermined range. Or when the bit synchronization signal or frame synchronization signal included in the received signal a is received.

  In addition, although the time from the rising to the next rising is divided into 32 slots, the half of the time from the rising to the rising may be divided into 32 slots. The number of slots to be divided is not limited to 32.

  Further, although the output is made when the addition value of the adder reaches 3, it is not limited to 3.

(Embodiment 2)
FIG. 5 is a block diagram of a reception synchronization signal generator in the second embodiment of the present invention. In FIG. 5, reference numeral 201 denotes a reception synchronization signal generator. The difference from the first embodiment shown in FIG. 1 is that the reception synchronization signal generator 201 uses the transmission rate information f from the bit rate detection unit 101. It is controlled by information and the clock cycle of the sampling clock e output from the clock generation means 205 is determined. The operation will be described below.

  The bit rate detection unit 101 includes a change point detection unit 102, a second timer unit 103, a determination unit 104, a first timer unit 105, a transmission rate determination unit 106, and a counter unit 107. Yes.

  The operation of the bit rate detection unit 101 in FIG. 5 will be described with reference to FIG.

  FIG. 6A shows an example in which the signal from the receiving unit 11 is 2400 bps and the data string is “101010101”. FIG. 6B shows an example in which the signal from the receiving unit 11 is 4800 bps and the data string is “11001100101010101”.

  First, an example in which the signal from the receiving unit 11 in FIG. 6A is 2400 bps and the data string is “101010101” will be described.

  The change point a of the rising edge of (4) signal waveform from the receiving unit 11 is detected by the change point detecting means 102, and the second timer means 103 is activated. The second timer means 103 is activated by the change point detecting means 102 (4) a time T2 from the rising point a of the signal waveform to the next rising change point b ((3) second timer in FIG. 6). ). When the measurement of T2 is completed, the second timer means 103 starts time measurement until the next rising change point, and sends T2 after the measurement to the determination means 104.

  In the judging means 104, T2 is in the time range (hereinafter referred to as 2400bps range) ± 30% (for 2 bits of 2400bps) or ± 30% time range (hereinafter 4800bps). Whether it is in the range). Then, the counter value of the counter means 107 is incremented regardless of which of the above ranges.

  The (5) count value in FIG. 6 indicates the count value of the counter means 107. In the example of FIG. 6A, since it is in the range of 2400 bps, the counter means 107 is incremented (0 → 1).

  The time T2 from the change point b to the change point c is considerably shorter than 1 bit length of 2400 bps because noise is mixed. And it is not in the range of 4800bps. Therefore, the determination means 104 determines that T2 is not in either range, and does not increment the counter means 107 (1 → 1).

  Similarly, it is determined that the time T2 from the rising change point c to the rising change point d is not in either range, and the counter means 107 is not incremented (1 → 1).

  Since the time T2 from the change point d to the change point e and the time T2 from the change point e to the change point f are both in the range of 2400 bps, the counter means 107 is incremented.

  When the count value (5) reaches 3, the counter means 107 activates the transmission rate determination means 106. The transmission speed determining means 106 determines the transmission speed of the signal waveform (4) based on the information of the count value 3 from the counter means 107 and the time information from the first timer means 105.

  The first timer means 105 measures the time T1 from the change point a to the change point f as shown by the first timer in FIG.

In the transmission speed determination means 105,
(6 bits of 2400 bps-α) <T1 <(8 bits of 2400 bps + α)
Here, if α is an allowance time considering the jitter of the signal waveform, it is determined that a (4) signal waveform of 2400 bps has been received.

(6 bits of 4800 bps-α) <T1 <(8 bits of 4800 bps + α)
Here, if α is a margin time considering the jitter of the signal waveform, it is determined that a 4800 bps (4) signal waveform has been received.

  In the example of FIG. 6A, it is determined that a signal waveform (4) of 2400 bps has been received.

  Next, an example in which the signal from the receiving unit 11 in FIG. 6B is 4800 bps and the data string “11001100101010101” will be described.

  The change point g at the rising edge of the signal waveform (9) from the receiving unit 11 is detected by the change point detection means 102, and the second timer means 103 is started. The second timer means 103 is activated by the change point detecting means 102 to obtain a time T2 from the rising change point g of the signal waveform (9) to the next rising change point h ((8) second timer in FIG. 6). ). When the measurement of T2 is completed, the second timer means 103 starts time measurement until the next rising change point, and sends T2 after the measurement to the determination means 104.

  In the judging means 104, T2 is in the time range (hereinafter referred to as 2400bps range) ± 30% (2400bps 2 bits) or ± 30% time range (hereinafter 4800bps range) It is called). Then, the counter value of the counter means 107 is incremented regardless of which of the above ranges. The (10) count value in FIG. 6 indicates the count value of the counter means 107. In the example of FIG. 6B, since it is in the range of 2400 bps, the counter means 107 is incremented (0 → 1).

  Since the time T2 from the next change point h to the change point i is also in the range of 2400 bps, the counter means 107 is incremented (1 → 2).

  Since the time T2 from the next rising change point i to the rising change point j is in the range of 4800 bps, the counter means 107 is incremented (2 → 3).

  When the count value (10) reaches 3, the counter means 107 activates the transmission rate determination means 106. The transmission speed determining means 106 determines the transmission speed of the signal waveform (9) based on the information of the count value 3 from the counter means 107 and the time information from the first timer means 105.

  The first timer means 105 measures the time T1 from the change point g to the change point j as shown by the first timer (7) in FIG.

In the transmission speed determination means 105,
(6 bits of 2400 bps-α) <T1 <(8 bits of 2400 bps + α)
Here, if α is a margin time considering the jitter of the signal waveform, it is determined that a (9) signal waveform of 2400 bps has been received.

(6 bits of 4800 bps-α) <T1 <(8 bits of 4800 bps + α)
Here, if α is a margin time considering the jitter of the signal waveform, it is determined that the (9) signal waveform of 4800 bps has been received.

  In the example of FIG. 6B, T1 does not hold either of the above two inequalities. Accordingly, the count value of the counter means 107 is cleared and the first timer means 105 is restarted.

  Since the time T2 from the next change point j to the change point k is in the range of 4800 bps, the count value of the counter means 107 is incremented (0 → 1). Since both the time T2 from the change point k to the change point l and the time T2 from the change point 1 to the change point m are within the range of 4800 bps, the counter means 107 is incremented (1 → 2).

  When the count value (10) reaches 3, the counter means 107 activates the transmission rate determination means 106. The transmission speed determining means 106 determines the transmission speed of the signal waveform (9) based on the information of the count value 3 from the counter means 107 and the time information from the first timer means 105.

  The first timer means 105 measures the time T1 from the change point j to the change point m as shown by the first timer in FIG. 6 (7).

In the transmission speed determination means 105,
(6 bits of 2400 bps-α) <T1 <(8 bits of 2400 bps + α)
Here, if α is a margin time considering the jitter of the signal waveform, it is determined that a (9) signal waveform of 2400 bps has been received.

(6 bits of 4800 bps-α) <T1 <(8 bits of 4800 bps + α)
Here, if α is a margin time considering the jitter of the signal waveform, it is determined that the (9) signal waveform of 4800 bps has been received.

  In the example of FIG. 6B, it is determined that a 4800 bps signal waveform (9) has been received.

  As described above, the transmission rate of the received signal can be determined with a simple configuration.

  As described above, when the transmission rate is determined by the bit rate detection unit 101, the transmission rate information f is output from the transmission rate determination unit 106 constituting the bit rate detection unit 101 to the synchronization signal generator 201. . When the synchronization signal generator 201 receives the transmission rate information f, it performs slot division according to the transmission rate, and performs the sampling of the period corresponding to the transmission rate information f from the clock generator 205 by the operation described in the first embodiment. The clock e is output. The outline of the operation is shown below.

  1) Divide into 32 slots, with 1/4800 seconds as one cycle.

  2) The rising edge of the signal is detected, and the value of the adder at the slot position of the edge is incremented by one.

  3) When the value of any one adder reaches 3, all adder values are cleared and the processing of 4) is performed. If the addition value does not reach 3, repeat from 2).

  4) When 4800 bps is already received as the transmission rate information f from the bit rate detection unit 101, the 4800 bps sampling clock e is generated at the timing Y = 8 slots after the timing when the added value reaches 3. If the transmission rate information f has not been received or has been received but is 2400 bps, a 2400 bps sampling clock e is generated at the timing Y = 16 slots after the timing when the added value reaches 3. Thereafter, when 4800 bps is received as the transmission rate information f from the bit rate detection unit 101, a 4800 bps sampling clock e is generated. At that time, if Y> 8, Y = 8.

  5) The operation described in the first embodiment is performed.

(Embodiment 3)
FIG. 5 shows a block diagram of a synchronization signal generator in the third embodiment, as in the second embodiment of the present invention.

  The operation of the bit rate detection unit 101 in the third embodiment will be described with reference to FIG.

  FIG. 7A shows an example in which the signal from the receiving unit 11 is 2400 bps and the data string is “101010101”. FIG. 7B shows an example in which the signal from the receiving unit 11 is 4800 bps and the data string is “11001100101010101”.

  First, an example in which the signal from the reception unit 11 in FIG. 7A is 2400 bps and the data string is “101010101” will be described.

  The changing point a of the rising edge of the signal waveform (4) from the receiving unit 11 is detected by the changing point detecting unit 102, and the second timer unit 103 is started. In the second timer means 103, the time T2 from the rising change point a of the signal waveform (4) to the next rising change point b by the activation from the change point detecting means 102 ((3) second timer in FIG. 6). ). When the measurement of T2 is completed, the second timer means 103 starts time measurement until the next rising change point, and sends T2 after the measurement to the determination means 104.

  In the judging means 104, T2 is in the time range (hereinafter referred to as 2400bps range) ± 30% (2400bps 2 bits) or ± 30% time range (hereinafter 4800bps range) It is called).

  The count value (5) in FIG. 7 indicates the count value of the counter means 107. In the example of FIG. 7A, the counter means 107 is incremented (0 → 1) because it is within the range of 2400 bps. In the subsequent determination of T2 in the determination means 104, the counter means 107 is incremented only when it is within the range of 2400 bps, and when it is not within the range of 2400 bps, the counter means 107 is cleared.

  The time T2 from the change point b to the change point c is considerably shorter than 1 bit length of 2400 bps because noise is mixed. Therefore, the determination means 104 determines that T2 is not within the range of 2400 bps, and clears the count value of the counter means 107 to zero (1 → 0). Then, the first timer means 105 starts measuring the time T1 at the change point a as shown by the first timer in FIG. 6 (7), but resets at the change point c.

  Similarly, it is determined that the time T2 from the rising change point c to the rising change point d is not within the range of 2400 bps, and the count value (5) of the counter means 107 is cleared to zero. Then, the first timer means 105 is reset and started.

  Since the time T2 from the change point d to the change point e is in the range of 2400 bps, the count value of the counter means 107 is incremented (0 → 1). In the subsequent determination of T2 in the determination means 104, the counter means 107 is incremented only when it is within the range of 2400 bps, and when it is not within the range of 2400 bps, the counter means 107 is cleared.

  Since the time T2 from the change point e to the change point f is in the range of 2400 bps, the counter means 107 is incremented (1 → 2). When the count value (5) displayed in FIG. 7A reaches 3, the counter means 107 activates the transmission rate determination means 106. The counter means 107 is informed by the judging means 104 that the count value is a count value indicating that the count value is in the range of 2400 bps. The transmission rate determining unit 106 determines the transmission rate of the signal waveform (4) based on the information that the counter unit 107 is 2400 bps and the time information from the first timer unit 105.

  The first timer means 105 measures the time T1 from the change point d to the change point g as shown by the first timer in FIG. 7 (2).

In the transmission speed determination means 105,
(6 bits of 2400bps-α) <T1 <(6 bits of 2400bps + α)
Here, if α is an allowance time considering the jitter of the signal waveform, it is determined that a (4) signal waveform of 2400 bps has been received.

Next, an example in which the signal from the receiving unit 11 in FIG. 7B is 4800 bps and the data string “11001100101010101” will be described. A change point h at the rising edge of the signal waveform (10) from the receiving unit 11 is detected by the change point detecting means 102, and the second timer means 103 is activated. In the second timer means 103, the time T2 from the rising change point h of the signal waveform (10) to the next rising change point i (second timer (9) in FIG. 7) is activated by the change point detecting means 102. ). When the measurement of T2 is completed, the second timer means 103 starts time measurement until the next rising change point, and sends T2 after the measurement to the determination means 104.
In the judging means 104, T2 is in the time range (hereinafter referred to as 2400bps range) ± 30% (2400bps 2 bits) or ± 30% time range (hereinafter 4800bps range) It is called).

  The count value (11) in FIG. 7 indicates the count value of the counter means 107. In the example of FIG. 7B, since it is in the range of 2400 bps, the counter means 107 is incremented (0 → 1). In the subsequent determination of T2 in the determination means 104, the counter means 107 is incremented only when it is within the range of 2400 bps, and when it is not within the range of 2400 bps, the counter means 107 is cleared.

  Since the time T2 from the next change point i to the change point j is also in the range of 2400 bps, the counter means 107 is incremented (1 → 2).

  Since the time T2 from the next rising change point j to the rising change point k is not within the range of 2400 bps, the count value of the counter means 107 is cleared to zero (2 → 0).

  The first timer means 105 starts measuring the time T1 at the change h as shown by the first timer in FIG. 7 (8), but starts resetting at the change point k.

  Since the time T2 from the next change point k to the change point 1 is in the range of 4800 bps, the count value (11) of the counter means 107 is incremented (0 → 1). In the subsequent determination of T2 in the determination means 104, the counter means 107 is incremented only when it is within the range of 4800 bps, and the counter means 107 is cleared when it is not within the range of 4800 bps.

  Since both the time T2 from the change point l to the change point m and the time T2 from the change point m to the change point n are within the range of 4800 bps, the counter means 107 is incremented (1 → 2, 2 → 3). .

  When the count value (11) reaches 3, the counter means 107 activates the transmission rate determination means 106. The counter means 107 is informed from the judging means 104 that the count value indicates that the count value is within the range of 4800 bps. The transmission rate determining unit 106 determines the transmission rate of the signal waveform (10) based on the information that the 4800 bps is received from the counter unit 107 and the time information from the first timer unit 105.

  The first timer means 105 measures the time T1 from the change point k to the change point n as shown by the first timer in FIG. 7 (8).

In the transmission rate determination means 106,
(6 bits of 4800 bps-α) <T1 <(6 bits of 4800 bps + α)
Here, if α is an allowance time considering the jitter of the signal waveform, it is determined that a 4800 bps signal waveform (10) has been received.

  As described above, the transmission rate of the received signal can be determined with a simple configuration.

  When the transmission rate is determined, the subsequent operation is exactly the same as in the second embodiment, and the transmission rate information f is transmitted from the transmission rate determination means 106 constituting the bit rate detection unit 101 to the synchronization signal generator 201. Is output. When the synchronization signal generator 201 receives the transmission rate information f, it performs slot division according to the transmission rate, and performs the sampling of the period corresponding to the transmission rate information f from the clock generator 205 by the operation described in the first embodiment. The clock e is output.

(Embodiment 4)
A fourth embodiment of the present invention will be described with reference to FIG.

  The initial value of the transmission rate determining means 106 is set to 2400 bps, which is the lower transmission rate. The transmission rate information from the transmission rate determining means 106 is transmitted to the synchronization signal generating device 201 in FIG. 5, and the sampling clock e is output from the clock generating means 206. In the example of FIG. 7A, the reception synchronization signal (6) is output from the clock generation means 205, and in the example of FIG. 7B, the reception synchronization signal (12) is the sampling clock e.

  As is apparent from FIG. 7, the reception synchronization signal is output at 2400 bps designated by the initial value of the transmission rate determining means 106. Then, as indicated by the reception synchronization signal (12), the transmission speed of the reception synchronization signal is switched to 4800 bps from the time when the transmission speed is determined to be 4800 bps by the transmission speed determination means 106. Thereafter, the operation of the transmission rate determination means 106 is stopped, and the transmission rate of the reception synchronization signal is fixed.

  When the signal waveform (10) is 4800 bps, when the data string is “1100110011001100...”, The transmission rate may seem to be 2400 bps. Therefore, when the signal waveform (10) is 4800 bps, if the initial value of the transmission rate determining means 106 is set to 4800 bps, there is a possibility that it is erroneously determined to be 2400 bps and the reception synchronization signal (12) is switched to 2400 bps. Yes, adversely affects data reception operation.

  On the other hand, when the signal waveform (10) is 2400 bps, the transmission rate does not look like 4800 bps in any data string. Therefore, even when the signal waveform (10) is 2400 bps, if the initial value of the transmission rate determining means 106 is set to 2400 bps, it is impossible to erroneously determine that it is 4800 bps and switch the reception synchronization signal (12) to 2400 bps. Therefore, there is no mistake in switching the transmission rate.

  Since there is always a bit synchronization signal in which “1010” is repeated a predetermined number of times as shown in FIG. 8 to be described later, when the signal waveform (10) is 4800 bps, the transmission speed is surely transmitted at the bit synchronization signal 1. It can be determined to be 4800bps.

  In addition, after the transmission speed of the reception synchronization signal (12) is switched to 4800 bps, the operation of the transmission speed determination means 106 is stopped. Therefore, even if a data string such as “1100110011001100. ) Will not switch to 2400bps.

  FIG. 8 shows a signal format in which the radio wave input to the receiving unit 11 in FIG. 5 is modulated.

  23 is a bit synchronization signal 1 and 24 in which “1010” is repeated a predetermined number of times, 31 is a frame synchronization signal 1 and 25 consisting of 31 bits for identifying the head of the signal, and 25 is an identification code unit 1 and 26 for identifying a communication partner It is a control information part which has information required for various communications. 23 to 26 are set as one basic unit 27. A unit obtained by repeating the basic unit 27 a plurality of times is called a header portion 21.

  Following the header part is 22 parts of data. The data part 22 is composed of 28 bit synchronization signals 2, 29 frame synchronization signals 2 and 30, identification code parts 30, and 31 data.

  The signal format shown in FIG. 8 is transmitted from the communication partner at 2400 bps or 4800 bps. The receiving unit 11 sequentially senses a plurality of channels, for example, three channels, and if there is a carrier, determines whether the signal is addressed to itself within a predetermined time Tx. Then continue carrier sense operation.

  The operation when there is a carrier is the operation described in FIG. That is, when there is a carrier, the transmission rate is determined, and a reception synchronization signal having the determined transmission rate is generated. The signal waveform is sampled by the generated reception synchronization signal to detect the frame synchronization signal 1. Then, it is determined whether or not it is addressed to itself by the identification code unit 1 sent following the frame synchronization signal 1.

  Since the basic unit 27 is repeatedly sent a predetermined number of times, even if it is determined that there is a carrier at an arbitrary timing of the basic unit 27, if the predetermined time Tx is set slightly larger than the time of the basic unit 27, there are always 23 bit synchronization signals The identification information portions of the frame synchronization signals 2 and 25 of 1 and 24 can be detected.

  In the above description, the two transmission rates A and B have been described as B = (n + 1) A (n: natural number, here n = 1). The transmission rates are 2400 bps and 4800 bps. It doesn't matter.

  6 and FIG. 7, the change point of the rising edge of the signal waveform is detected. However, the change point of the falling edge may be detected, or both the rising and falling change points may be detected. good.

  However, if there is an offset in the threshold value of the waveform shaping circuit that generates the signal waveform of FIG. 6 or 7 in the receiving unit 11, the length of the 1 period and the 0 period of the signal waveform are different. Therefore, when detecting both rising and falling transition points, it is necessary to consider that it becomes difficult to distinguish between cases where the 1 level of 4800 bps becomes longer and those where the 1 level of 2400 bps becomes shorter. There is. When only the rising or falling change point is detected, the time between the change points is not affected by the offset.

  Therefore, there is an advantage that it is easier to distinguish between 2400 bps and 4800 bps than detecting both rising and falling transition points.

  In this embodiment, the counter 3 is determined based on the time T1 corresponding to 6 bits. However, the determination is not limited to this, and the time may be determined based on n bits (n is a natural number).

  Note that the means described in this embodiment causes hardware resources such as a CPU (or microcomputer), a RAM, a ROM, a storage / recording device, an electrical / information device including an I / O, a computer, a server, and the like to cooperate. You may implement with the form of a program. In the form of a program, new functions can be easily distributed / updated and installed by recording them on a recording medium such as magnetic media or optical media or distributing them using a communication line such as the Internet.

As described above, the reception synchronization signal generator according to the present invention accurately determines the transmission speed of the received signal and receives data regardless of which of the two transmission speeds is received with a simple configuration. A sampling clock for sampling can be generated.

Block diagram of reception synchronization signal generating apparatus in Embodiment 1 of the present invention The block diagram of the rising change point detection means in Embodiment 1 of this invention Operation explanatory diagram for explaining the operation in the first embodiment of the present invention. Operation explanatory diagram for explaining the operation in the first embodiment of the present invention. Block diagram of reception synchronization signal generator in Embodiments 2, 3, and 4 of the present invention Operation explanatory diagram for explaining the operation in the second embodiment of the present invention. Operation explanatory diagram for explaining the operation in the third and fourth embodiments of the present invention. The figure explaining the received signal format in Embodiment 1, 2, 3, 4 of this invention Block diagram of a conventional reception synchronization signal generator Operation explanatory diagram for explaining the operation of a conventional reception synchronization signal generator

Explanation of symbols

DESCRIPTION OF SYMBOLS 102 Change point detection means 103 2nd timer means 104 Judgment means 105 1st timer means 106 Transmission speed determination means 107 Counter means 201 Reception synchronous signal generator 202 Rising change point detection means 203 Falling change point detection means 204 Pulse width Measurement means 205 Clock generation means 206 Slot group 207 Adder group 208 Change point output means

Claims (8)

Rising change point detecting means for detecting a rising point of the signal; and
A falling change point detecting means for detecting a change point of the falling of the signal;
Time measurement is started at the rise timing of the signal detected by the rising change point detection means, and time measurement is terminated at the fall timing of the signal detected by the falling change point detection means, or detected by the falling change point detection means Pulse width measuring means for starting time measurement at the falling timing of the signal and ending time measurement at the rising timing of the signal detected by the rising change point detecting means; the rising timing or falling timing information; and the pulse width measuring means in a clock generating means for determining the occurrence position of the sampling clock by using two of the measured measurement time information,
The rising change point detection means or the falling change point detection means,
A slot group consisting of a plurality of time slots;
An adder group consisting of adders corresponding to 1: 1 for each time slot;
It is composed of change point output means that operates according to the output of the adder group,
The value of the adder connected to the time slot corresponding to the timing at which the signal change occurred is changed by one, and the value of any one of the adders in the adder group becomes a predetermined value. Sometimes, the change point output means outputs the change point at the timing of the time slot corresponding to the adder having the predetermined value,
The clock generation means includes
If the measurement time information measured by the pulse width measurement means is less than a predetermined value, the sampling clock generation position is made earlier than the previous generation position,
If the measurement time information measured by the pulse width measurement means is greater than the predetermined value, the sampling clock generation position is made slower than the previous generation position.
Reception synchronization signal generator. The change point output means outputs detection of a change point when the value of any one adder in the adder group reaches a predetermined value, and outputs the values of all the adders in the adder group to a predetermined value. 2. The reception synchronization signal generator according to claim 1 , wherein control is performed so as to reset the value. The sampling period of the clock generation means for determining the generation position of the sampling clock includes first timer means for starting operation at a predetermined timing, change point detection means for detecting a change point of the received signal, and the change point detection means Second timer means for measuring the time from the change point detected in step 1 to the next change point, determination means for determining whether the time measured by the second timer means is within a predetermined range, and the determination Counter means for counting up when the measuring time is within the predetermined range by the means, and the transmission rate by the timer value read from the first timer means when the count value of the counter means reaches a predetermined value configurations that are set on the basis of the transmission rate determined by the configuration comprising a transmission rate determining means for determining the claims 1 or 2, wherein Receiving the synchronization signal generating device. The predetermined sampling period of the clock generation means for determining the generation position of the sampling clock includes a first timer means for starting operation at a predetermined timing, a change point detection means for detecting a change point of the received signal, and the change check. Second timer means for measuring the time from the change point detected by the output means to the next change point, and determination means for determining whether the time measured by the second timer means is within a predetermined range; When the measurement time is within the predetermined range by the determination means, the counter means counts up when the measurement time is not within the predetermined range, and the count value of the counter means From transmission rate determining means for determining a transmission rate according to the timer value read from the first timer means when the value reaches a predetermined value Receiving the synchronization signal generating apparatus according to claim 1 or 2 wherein where the structure is set on the basis of the transmission rate determined by the configuration that. 5. The reception synchronization signal generator according to claim 3 , wherein the change point detecting means is configured to detect only a change point of either rising or falling of the received signal. 6. The reception synchronization signal generator according to claim 3 , wherein the initial value of the transmission rate of the transmission rate determining means is set to a lower limit value of an expected transmission rate. 7. The transmission speed determining means is configured to stop the operation of the transmission speed determining means when the transmission speed is determined from the count value from the counter means and the timer value of the first timer means . The reception synchronization signal generator according to any one of the preceding claims. 8. A reception synchronization signal generating apparatus according to claim 6, wherein a relationship between an expected first transmission rate A and an expected second transmission rate B of the received signal is B = (n + 1) A (n: natural number). .

Images