JP4609702B2 - Data processing system and control method thereof - Google Patents

Description

  The present invention relates to a data processing system capable of flexibly executing a program including instructions or instruction sets for data processing systems having different architectures, and a control method thereof.

The functional structure or physical structure of a computer is called an architecture, and is one of the important factors that determine the functions of the software and hardware of a computer system as a whole. If the hardware configuration is different, the software instructions for controlling it are also different. Efforts to share instructions are constantly being made to facilitate software design, use of assets, etc., but control hardware with new functions or install hardware with different functions. Different commands may be employed to control. The same instruction may request execution of different processing from the hardware. In particular, since an instruction close to a machine language that directly controls hardware is affected by the architecture, there are few cases where the instructions are all the same.
JP 2003-167730 A

  There is a desire to execute an application program on hardware of a different architecture. There is also a desire to develop an application program more easily or to design a part of the application program to be executed by a different architecture suitable for executing the processing.

  In Japanese Patent Laid-Open No. 2003-167730, a microprocessor that can perform processing with an instruction set optimized for each application has a data path unit and a control unit on the same chip. It is disclosed to provide a microprocessor that is configured by programmable logic such as FPGA and the data path unit is configured by hardware logic that is not programmable logic. If this technique is used, the programmable logic of the microprocessor can be rewritten so that processing is performed with an instruction set corresponding to the application program. However, since it is necessary to interrupt the process in order to rewrite the programmable logic of the FPGA, it is impossible to include instructions of a plurality of architectures in one application program.

  In recent years, dynamically reconfigurable processors have been developed, and logic can be rewritten in one cycle. Therefore, by using a dynamically reconfigurable processor instead of the FPGA, there is a possibility that instructions of an instruction set of a plurality of architectures can be included in one application program. However, many microprocessors are designed so that processing proceeds by pipeline operation in order to shorten the substantial processing time. There are various methods for dividing the pipeline. In Japanese Patent Laid-Open No. 2003-167730, the pipeline is divided into five stages: instruction fetch IF, instruction decode ID, operation execution EX, memory access MEM, and register write WB. Thus, the contents that must be processed per clock cycle are simplified, or the processing speed is increased by raising the clock frequency.

  Therefore, even if the logic of the control unit can be rewritten in one clock cycle, instructions in the program need to control the pipeline operation. For this reason, instructions of different architectures are required until the pipeline operation by one instruction is completed. The control cannot be rewritten so that the set can be decoded. Therefore, in order to rewrite the logic of the control unit, it is necessary to finish the pipeline operation once and restart it. Therefore, there will be a delay of the clock cycle consumed by the pipeline for restart, and the function as the scheduled application program cannot be obtained, or the program for different architecture cannot be completely emulated. A problem occurs.

  Therefore, in the present invention, data that can execute an application program in which instructions corresponding to different architectures, that is, instructions belonging to different instruction sets are mixed without restarting the pipeline operation and without causing an obstacle to the pipeline operation. It aims to provide a processing system.

One aspect of the present invention is a data processing system that fetches and processes an instruction by a pipeline operation, and includes a plurality of circuit elements, a connection between the plurality of circuit elements, and / or in each circuit element. A plurality of circuit elements for dynamically reconfiguring a circuit by arbitrarily changing the setting of the circuit in a predetermined range, and a pipeline at least part of which is configured by the plurality of circuit elements. Fetched at the fetch stage, fetch stage sequentially fetching instructions from the application program under the control of the program counter, architecture determination stage determining the architecture type information corresponding to the instruction fetched at the fetch stage A decode stage for decoding an instruction and the fetch stage; An execution stage for executing an operation based on the instruction fetched in the register, and a WB stage for performing a register write by the instruction fetched in the fetch stage, and further, connection between the plurality of circuit elements and / or A configuration for performing control for dynamically reconfiguring the configurations of the decode stage, the execution stage, and the WB stage by changing the setting in the circuit element based on the architecture type information determined in the architecture determination stage. The architecture type information determined in the architecture determination stage includes a control unit, and the instruction is fetched between the decode stage, the execution stage, and the stage of the WB stage together with the instruction fetched in order by the fetch stage. In response, the configuration control unit transfers the decode stage in accordance with the timing at which the instructions fetched in order by the fetch stage are executed in the decode stage, the execution stage, and the WB stage. , A data processing system for performing control to reconfigure at least a part of the execution stage and the WB stage.
Furthermore, another aspect of the present invention is a data processing system that fetches and processes an instruction by pipeline operation, and includes a plurality of circuit elements, and a connection between the plurality of circuit elements and / or each of the circuit elements. A plurality of circuit elements for dynamically reconfiguring the circuit by arbitrarily changing a setting in the circuit element within a predetermined range, and a pipeline at least partially configured by the plurality of circuit elements; The pipeline sequentially fetches instructions from an application program under the control of a program counter, and also determines a fetch stage that determines architecture type information in units of fetched instructions, and a decode that decodes instructions fetched in the fetch stage. A stage and an operation by an instruction fetched in the fetch stage. An execution stage for executing a write operation, and a WB stage for performing a register write by an instruction fetched in the fetch stage, and further, a connection between the plurality of circuit elements and / or a setting in each circuit element is set in the fetch stage. A configuration control unit that performs control for dynamically reconfiguring the configurations of the decode stage, the execution stage, and the WB stage by changing based on the architecture type information determined in step Information on the determined architecture type is transferred between the decode stage, the execution stage, and the WB stage in the pipeline cycle corresponding to the instruction together with the instruction fetched in order by the fetch stage. The migration control unit may include at least one of the decode stage, the execution stage, and the WB stage in accordance with a timing at which instructions fetched in order by the fetch stage are executed in the decode stage, the execution stage, and the WB stage. A data processing system that performs control to reconfigure a part of the configuration.
The configuration control unit has a plurality of stage configuration memories that transfer architecture type information in accordance with the pipeline cycle, and the configurations of the decode stage, the execution stage, and the WB stage in the respective stage configuration memories. It is desirable to include a plurality of stage control units that are controlled by architecture type information. In this data processing system, the configuration of each stage of the pipeline can be changed at the timing of processing the fetched instruction. Therefore, an application program in which instructions of instruction sets of different architectures are mixed can be executed without resetting or interrupting the pipeline operation.

Another aspect of the present invention is a data processing system control method for fetching and processing an instruction by a pipeline operation, and the data processing system includes a plurality of circuit elements, and the plurality of circuits A plurality of circuit elements for dynamically reconfiguring the circuit by arbitrarily changing a connection between the elements and / or a setting in each circuit element within a predetermined range, and at least a part of the plurality of circuit elements A pipeline configured, and the pipeline determines a fetch stage for sequentially fetching instructions from an application program under the control of a program counter, and architecture type information corresponding to the instructions fetched in the fetch stage The architecture determination stage to be decoded and the instruction fetched in the fetch stage are decoded. A decode stage, an execution stage for executing an operation based on an instruction fetched in the fetch stage, and a WB stage for performing a register write by an instruction fetched in the fetch stage, and further comprising: The configuration of the decode stage, the execution stage, and the WB stage is dynamically changed by changing the connection between them and / or the setting in each circuit element based on the architecture type information determined in the architecture determination stage. A configuration control unit that performs reconfiguration control, and the control method is configured such that the information on the architecture type determined in the architecture determination stage is between the decode stage, the execution stage, and the WB stage. The fetch stage is transferred together with the instruction fetched in order by the pipeline cycle corresponding to the instruction, and the configuration control unit reads the instruction fetched in order by the fetch stage in the decode stage, the execution stage, Control is performed to reconfigure at least part of the configuration of the decode stage, the execution stage, and the WB stage in accordance with the timing executed in the WB stage.
Another aspect of the present invention is a data processing system control method for fetching and processing an instruction by a pipeline operation, and the data processing system includes a plurality of circuit elements, and the plurality of circuits A plurality of circuit elements for dynamically reconfiguring the circuit by arbitrarily changing a connection between the elements and / or a setting in each circuit element within a predetermined range, and at least a part of the plurality of circuit elements A pipeline configured, wherein the pipeline fetches instructions from an application program in order under the control of a program counter and determines architecture type information in units of fetched instructions; and the fetch A decode stage for decoding an instruction fetched in the stage; and the fetch stage And an WB stage for performing a register write with the instruction fetched at the fetch stage, and a connection between the plurality of circuit elements and / or respective circuits. A configuration control unit that performs control to dynamically reconfigure the configurations of the decode stage, the execution stage, and the WB stage by changing the setting in the element based on the architecture type information determined in the fetch stage. And the architecture type information determined at the fetch stage includes the instruction fetched in order by the fetch stage between the decode stage, the execution stage, and the WB stage. Correspondingly Transferred by a pipeline cycle, and the configuration control unit executes the decode stage and the execution in accordance with the timing at which the instructions fetched in order by the fetch stage are executed in the decode stage, the execution stage, and the WB stage. And performing control for reconfiguring at least a part of the configuration of the stage and the WB stage . What is to be changed is a data path configuration mainly for realizing the processing of each stage, and changes the function of an arithmetic unit such as ALU or changes the contents of a lookup table (LUT). It is also included.

  When the type of instruction set to which an instruction included in an application program belongs differs in block units or function unit units, the pipeline architecture may be exchanged in block units or function units. Therefore, information including the architecture type may also be determined in units of blocks or functions. However, in this case, in order to determine the architecture type, the data processing system needs to have a function of determining a group of instructions in units of blocks or units of functions, and the structure and control become complicated. Furthermore, an application program in which instructions belonging to different instruction sets are mixed for each instruction cannot be processed. On the other hand, by changing the data path configuration so that each stage of the pipeline matches the architecture type of the instruction in accordance with the timing of processing the fetched instruction, by simple circuit configuration and control, An application program in which instructions belonging to different instruction sets are mixed in units of instructions can be processed.

  One form of obtaining information about the architecture type corresponding to the fetched instruction is that the pipeline includes an architecture determination stage for determining the architecture type corresponding to the fetched instruction. It is possible to provide an application program in which an instruction and information of an architecture type corresponding to the instruction are stored in advance. In this case, the pipeline includes a fetch stage that fetches the architecture type information corresponding to the instruction together with the instruction, so that the architecture type information can be acquired.

  By transferring the architecture type information in the pipeline cycle, the configuration of each stage of the pipeline can be changed in accordance with the timing at which the fetched instruction is executed in each stage. In a clock-synchronized pipeline operation, each stage of the pipeline is controlled according to the pipeline cycle, and the cycles consumed in each stage are known in advance. Therefore, by changing the configuration of each stage according to the pipeline cycle, it is possible to independently control the operation of each stage and control the configuration of each stage, like a data flow computer. It is not necessary to control firing by providing a waiting mechanism for each processing unit.

  When the pipeline includes at least a decode stage for decoding the fetched instruction, an execution stage for executing an operation based on the fetched instruction, and a WB stage for writing a register using the fetched instruction, the configuration control unit The configuration of at least one of the decode stage, the execution stage, and the WB stage is changed. By changing the configuration of the decode stage, it is possible to interpret instructions belonging to instruction sets having different structures such as different flag positions. By changing the configuration of the execution stage or the configuration of the WB stage, it is possible to select whether or not to execute the compound instruction and whether or not to automatically update the flag.

  The hardware constituting each stage of the pipeline may be designed in advance so as to correspond to the architecture of several instruction sets included in the application program. In this case, the configuration control unit selects a predetermined data path configuration in accordance with the architecture type information in the configuration change step.

  At least some of the plurality of circuit elements use hardware capable of dynamically reconfiguring the connection between the circuit elements and / or the setting in each circuit element, which can be arbitrarily changed within a predetermined range. It is possible to realize a stage in which a configuration change is required depending on the architecture type by hardware that can be dynamically reconfigured. The configuration control unit can dynamically change the stage of the pipeline by changing the connection between the plurality of circuit elements and / or the setting in each circuit element in the configuration changing process. By reconfiguring the stage configuration, it is not necessary to previously implement a plurality of data path configurations corresponding to a plurality of architectures, and a selector for selecting a plurality of data paths is also unnecessary. Therefore, a stage that requires a configuration change can be generated with a small amount of hardware resources, and the time and power consumed by a selector or the like can be reduced. Therefore, the data processing system of the present invention can be realized in a compact manner, and power consumption can be reduced.

  FIG. 1 shows a schematic configuration of an example of the data processing system of the present invention. The data processing system 1 is a processor that performs a process of fetching and processing an instruction using a pipeline. A pipeline 10 of the processor 1 includes a fetch stage (IF) 11 that fetches instructions from an application program 3 including several instructions, which are recorded in an external or internal memory 2, in order under the control of a program counter 16; An architecture determination stage (TR) 12 that determines an architecture type corresponding to the fetched instruction from the configuration of the fetched instruction, a decode stage (DEC) 13 that decodes the fetched instruction, and an operation based on the fetched instruction is executed. An execution stage (EX) 14 and a WB stage (WB) 15 for writing a register by a fetched instruction are provided. Although the pipeline register is not shown in FIG. 1, the configuration of each of the stages 11 to 15 includes a register that functions as a pipeline register. In the DEC stage 13, the fetched instruction 19 is decoded, and control information 31 of the EX stage 14 and control information 32 of the WB stage 15 are generated and set in the EX control unit 33 and the WB control unit 34, respectively. Control information 32 is supplied to the WB control unit 34 via a pipeline delay register 35 that generates a delay of the same cycle as that of the EX stage 14. Therefore, in the processor 1, the processing of the instruction 19 fetched by the IF stage 11 is sequentially executed in a predetermined cycle in these stages 11 to 15.

  The DEC stage 13, the EX stage 14, and the WB stage 15 are generated using hardware capable of dynamically reconfiguring a circuit. An example of dynamically reconfigurable hardware is one in which connections between a plurality of circuit elements and / or settings in each circuit element can be arbitrarily changed within a predetermined range. The applicant of the present application discloses an example of reconfigurable hardware in International Publication No. WO2002-095946, and basically the circuit configuration can be changed in one clock cycle. The processor 1 of this example can be realized by mounting the entire processor 1 on reconfigurable hardware. It is also possible to mount the DEC stage 13, the EX stage 14 and the WB stage 15 on reconfigurable hardware, and to mount a stage with other configurations fixed by an ASIC or the like. In the present invention, the IF stage 11 and the TR stage 12 do not need to be limited to those having a fixed configuration. The configuration of 12 may be changed. For example, for a program in which a fixed-length instruction set and a variable-length instruction set are mixed, it is also effective to change the configuration of the IF stage 11.

  The processor 1 controls a configuration of the DEC stage 13, the EX stage 14, and the WB stage 15 based on architecture type information (hereinafter, architecture information) 29 determined by the TR stage 12. It has. The configuration control unit 20 stores the configuration information of the stage control units 21a to 21c for controlling the configurations of the DEC stage 13, the EX stage 14 and the WB stage 15 and the configurations of the DEC stage 13, the EX stage 14 and the WB stage 15, respectively. Recorded stage configuration memories 22a to 22c are provided. The stage control units 21 a to 21 c are connected via pipeline registers, and each stage control unit 21 a and 21 b transfers the architecture information 29 after consuming the same cycle as the DEC stage 13 and EX stage 14. . Therefore, in the configuration control unit 20, the architecture information 29 is transferred between the stage control units 21a to 21c by the cycle of the pipeline 10, and each of the stage control units 21a to 21c includes the DEC stage 13 and the EX stage 14 respectively. The configuration of the WB stage 15 is reconfigured based on the architecture information 29 of the fetched instruction 19 in accordance with the timing at which the instruction 19 fetched by each stage is processed.

  In order to execute the instructions included in the program 3 as intended by the creator of the program 3, it is necessary to decode and execute the instructions as intended by the creator of the program 3. That is, if the instruction of the program 3 is not executed by a processor having the same or common architecture as the architecture in which the instruction is to be executed, the application provided by the program 3 does not operate as specified. At present, the processor architecture is largely divided into CISC and RISC, and even if it is a little bit together with the RISC processor, the architecture differs depending on each manufacturer such as ARM, MIPS, SPARC, PowerPC, Alpha and the like. Therefore, many RISC instructions show common contents, but there are cases where the processing contents are different depending on each architecture or the instructions themselves are different. In many cases, each architecture employs a slightly different instruction set, that is, an instruction format, and the TR stage 12 can often determine the architecture by analyzing the fetched instruction. Therefore, in the processor 1 of this example, even if instructions of a plurality of architectures are mixed in the program 3, each instruction can be executed by the architecture intended by the creator.

  However, some architectures have a common instruction set depending on the architecture. In such a case, it is desirable to indicate architecture information for each instruction when the architecture is mixed on the program 3 side. In the program code 3a shown in FIG. 2, architecture information (architecture codes C-0 to C-2) 29 is indicated in units of fetched instructions 19 (In0 to In4). In the processor of the present invention targeting such a program 3a, the IF stage 11 can obtain the architecture information 29 corresponding to the fetched instruction 19. Therefore, the TR stage 12 can be omitted, and the TR stage may be omitted in the following description.

  FIG. 3 schematically shows how the configurations of the DEC stage 13, the EX stage 14, and the WB stage 15 change in units of pipeline cycles and the fetched instruction is executed. Each of the stages 13 to 15 of the processor 1 changes its configuration based on the architecture information 29 corresponding to the fetched instruction 19 in accordance with the timing at which the fetched instruction 19 is processed, that is, the pipeline cycle. Controlled by a control method including a process (configuration change process) 25 to be performed. The basic process of each stage is to perform a desired process on the input data and output it, and the data path structure for that is the object of change. When the data path includes an arithmetic unit such as ALU, the function is changed, and when the output is obtained by a lookup table (LUT), the contents are changed.

  Further, the stages 13 to 15 of the processor 1 are controlled by a control method including a step 26 of transferring the architecture information 29 by the cycle of the pipeline 10. Therefore, instructions having different architectures can be executed without once stopping or restarting (resetting) the flow of the pipeline 10. In FIG. 3, the architecture information 29 is transferred between the stages as indicated by the alternate long and short dash line, and at the same time, the fetched instruction 19 is transferred. Therefore, in each stage, reconfiguration and instruction execution are repeated, and the pipeline 10 can process the instruction 19 having a different architecture without causing the pipeline operation to fail. FIG. 3 shows the fetched instruction 19 and the architecture information 29 in an easily distinguishable state. The timing at which the architecture information 29 is supplied to each stage is the instruction in which data is fetched at each stage by the pipeline 10. It suffices if it matches the timing processed at step 19. Therefore, before the pipeline register at each stage latches the data processed by the data path, the architecture information 29 is stored at the timing at which the fetched instruction 19 is executed at each stage reconstructed by the architecture information 29. It may be supplied to the stage. In the stages located downstream of the DEC stage 13 such as the EX stage 14 and the WB stage 15, the fetched instruction 19 is supplied to the respective stages as the control information 31 and 32 obtained by decoding the instruction 19 as described above. Just as you did.

  FIG. 4 shows how the architecture can be changed without breaking the pipeline. As shown in FIG. 4A, when executing the program 3 including the instructions of the architecture C-1 and the architecture C-2, if the processor 1 of this example, each stage 11 of the pipeline 10 is executed. Since the configuration can be changed along the progress of ˜15, instructions of different architectures can be executed without stopping the pipeline 10. Therefore, according to the processor 1 of the present invention, it is possible to create a program by mixing instructions having different architectures at the same level as instructions having the same architecture, and an application using mixed functions of processors of various architectures. Can be easily developed.

  On the other hand, assuming a processor whose configuration is changed collectively by the architecture information 29, as shown in FIG. 4B, the architecture C-2 is processed after the completion of the instruction processing of the architecture C-1. It is necessary to execute the instruction of the architecture C-2. Therefore, it is necessary to stop the operation of the pipeline 10 and restart it when it is reconfigured. For this reason, a delay of one pipeline cycle occurs at the stage of executing an instruction with a different architecture, and the program 3 that does not assume such a delay cannot be executed as specified. Furthermore, if the reconfigurable hardware can change the configuration with a single clock, the delay is only one pipeline cycle. However, hardware that spends a significant amount of time in ms to change the circuit configuration, such as an FPGA. In some cases, it is impossible to mix instructions with different architectures in one program.

  FIG. 5 shows an example of changing the configuration of the EX stage 14. The architecture C-2 has the following setting of an addition instruction, and it is assumed that the architecture C-1 does not have such an addition instruction.

Instruction: ADD Rd, Rn, Rm, LSL # 5bit_Immed
Operation: Rd = Rn + (Rm <<# 5bit_Immed)
In the architecture C-1, the same processing as the above-described instruction can be executed by the following two instructions. Therefore, it is possible to completely replace the instruction of architecture C-1 by the compiler.
LSL Rm, Rm, # 5bit_Immed
ADDU Rd, Rn, Rm

  However, by using two instructions, the number of execution clocks increases, so the processing time is extended. Furthermore, by dividing into two instructions, there is a possibility that an interrupt may occur between those instructions, and it does not completely conform to the specifications of the original program. On the other hand, if the configuration related to the ADD instruction of architecture C-1 is replaced with architecture C-2, the instruction of architecture C-1 cannot be executed. In the processor 1 of this example, this problem can be solved by changing the configuration of the EX stage 14 by the architecture information 29. That is, the stage configuration memory 22b of the EX stage 14 is prepared with the configuration of the architecture C-1 shown in FIG. 5A and the configuration of the architecture C-2 shown in FIG. The data path configuration of the EX stage 14 may be reconfigured to the architecture C-2 at the timing when the C-2 ADD instruction is executed in the EX stage 14.

  FIG. 6 shows a different example in which the configuration of the EX stage 14 is changed. In this example, a data path of architecture C-1 and a data path of architecture C-2 are prepared in advance in the EX stage 14, and a selector 14s for switching these data paths is prepared. Therefore, the stage control unit 21b switches the selector 14s based on the architecture information 29, so that the ADD instruction of the architecture C-2 can be executed as planned by the ADD instruction. In this example, no hardware capable of dynamically reconfiguring the circuit is required to obtain the function as the stage 14. However, in addition to the amount of hardware capable of configuring the circuits of the two architectures, hardware such as a selector for switching between them is required. Therefore, the amount of hardware increases and the selector is interposed in the data path, so that the execution cycle in the stage may increase more than the original architecture. This problem is further increased when the number of architectures that can be executed in the processor 1 is increased. This problem can be prevented by employing hardware that can dynamically reconfigure the circuit.

  FIG. 7 shows an example of changing the configuration of the WB stage 15. FIG. 7 shows an example of switching by the selector, but the configuration of the WB stage 15 can be changed by reconfigurable hardware as described above. In this example, in the architecture C-2, in addition to alu_opr, there is an instruction alu_oprS, and the flag is updated in alu_oprS, whereas the flag is not updated in alu_opr. On the other hand, in architecture C-1, there is an instruction alu_opr and there is no alu_oprS, but the flag is updated by executing alu_opr. Therefore, when the fetched instruction 19 executed at this stage is the architecture C-1 according to the architecture information 29, the stage control unit 21c sets the selector 15s so that the flag is updated by alu_opr. On the other hand, when the fetched instruction 19 executed at this stage is the architecture C-2 by the architecture information 29, the stage control unit 21c sets the selector 15s so that the flag is updated by alu_oprS.

  FIG. 8 shows an example of changing the configuration of the DEC stage 13. This example is also shown as a configuration that is switched by the selector, but as described above, the data path configuration can be reconfigured by reconfigurable hardware. As described above, the format of the instruction set may differ depending on the architecture. As shown in FIG. 8A, when the position of the carry bit differs depending on the architecture, as shown in FIG. 8B, the stage control unit 21a controls the selector 13s based on the architecture information 29 and the flag of the DEC stage 13 is displayed. The lead configuration can be changed. FIG. 8C shows an example of the DEC stage 13 in which the meaning of the flag bit can be changed for each architecture. It is possible to decode the instruction 19 fetched as a bit indicating carry in the architecture C-1 and a bit having a different meaning in the architecture C-2, and to control the EX stage 14 and / or the WB stage 15.

  In the processor 1 of this example, the IF stage 11, the DEC stage 13, the EX stage 14 and the WB stage 15 constitute the pipeline 10, but the EX stage or the WB stage is divided into a plurality of stages, The present invention can also be applied to a processor having pipelines with different configurations, such as independent memory read stages. Further, the number of pipelines included in the processor is not limited to one. Furthermore, the processor or data processing system to which the present invention is applied is not limited to a product formed as a chip as a general-purpose processor, but also includes a product group called SoC or system LSI in which the processor is embedded.

It is a block diagram which shows schematic structure of an example of the processor of this invention. It is a figure which shows an example of the different program which can give architecture information. It is a figure which shows typically a mode that the structure of the stage of a pipeline changes. FIG. 4A is a diagram illustrating a state in which an instruction is executed by changing the configuration of a pipeline stage. FIG. 4A illustrates a state when the configuration of the pipeline is changed according to the present invention, and FIG. It shows how the line configuration is changed all at once. It is a figure which shows the example which changes the structure of EX stage using the reconfigurable hardware. It is a figure which shows the example which changes the structure of EX stage by a selector. It is a figure which shows the example which changes the structure of a WB stage by a selector. It is a figure which shows the example which changes the structure of a DEC stage by a selector.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Processor, 2 Memory, 3 Program 10 Pipeline, 11 IF stage, 12 TR stage 13 DEC stage, 14 EX stage, 15 WB stage 19 Fetched instruction 20 Configuration control unit 21a-21c Stage control unit 22a-22c Stage structure Memory 29 Architecture information

Claims (5)

A data processing system that fetches and processes instructions by pipeline operation,
A plurality of circuit elements, wherein the circuit is dynamically reconfigured by arbitrarily changing a connection between the plurality of circuit elements and / or a setting in each circuit element within a predetermined range. And
Having at least a part of the pipeline constituted by the plurality of circuit elements,
The pipeline is a fetch stage that fetches instructions from an application program in order under the control of a program counter;
An architecture determination stage for determining information of an architecture type corresponding to the instruction fetched in the fetch stage;
A decode stage for decoding an instruction fetched in the fetch stage;
An execution stage for performing an operation based on the instruction fetched in the fetch stage;
A WB stage for writing a register by an instruction fetched in the fetch stage,
Further, the decoding stage, the execution stage, and the WB are changed by changing the connection between the plurality of circuit elements and / or the setting in each circuit element based on the architecture type information determined in the architecture determination stage. It has a configuration control unit that performs control to dynamically reconfigure each stage configuration,
The architecture type information determined in the architecture determination stage includes the instructions fetched in order by the fetch stage between the decode stage, the execution stage, and the WB stage in accordance with the pipeline cycle corresponding to the instruction. The configuration control unit is transferred to the decode stage, the execution stage, and the WB stage in accordance with the timing at which instructions fetched in order by the fetch stage are executed in the decode stage, the execution stage, and the WB stage. A data processing system that performs control to reconfigure at least part of the configuration . A data processing system that fetches and processes instructions by pipeline operation,
A plurality of circuit elements, wherein the circuit is dynamically reconfigured by arbitrarily changing a connection between the plurality of circuit elements and / or a setting in each circuit element within a predetermined range. And
Having at least a part of the pipeline constituted by the plurality of circuit elements,
The pipeline fetches instructions from an application program in order under the control of a program counter and fetches architecture type information in units of fetched instructions; and
A decode stage for decoding an instruction fetched in the fetch stage;
An execution stage for performing an operation based on the instruction fetched in the fetch stage;
A WB stage for writing a register by an instruction fetched in the fetch stage,
Further, the decoding stage, the execution stage, and the WB stage are changed by changing the connection between the plurality of circuit elements and / or the setting in each circuit element based on the architecture type information determined in the fetch stage. A configuration control unit that performs control to dynamically reconfigure each of the
The architecture type information determined in the fetch stage is transferred between the decode stage, the execution stage, and the WB stage in a pipeline cycle corresponding to the instruction together with the instruction fetched in order by the fetch stage. The configuration control unit is configured so that instructions fetched in order by the fetch stage are executed in the decode stage, the execution stage, and the WB stage in accordance with the timing of the decode stage, the execution stage, and the WB stage. A data processing system that performs control to reconfigure at least part of the configuration . In claim 1 or 2,
The configuration control unit has a plurality of stage configuration memories that transfer architecture type information in accordance with the pipeline cycle, and the configurations of the decode stage, the execution stage, and the WB stage in the respective stage configuration memories. A data processing system comprising a plurality of stage control units controlled by architecture type information. A control method of a data processing system for fetching and processing an instruction by pipeline operation,
The data processing system includes a plurality of circuit elements, and dynamically reconnects the circuits by arbitrarily changing connections between the plurality of circuit elements and / or settings in the respective circuit elements within a predetermined range. A plurality of circuit elements comprising ;
Having at least a part of the pipeline constituted by the plurality of circuit elements,
The pipeline is a fetch stage that fetches instructions from an application program in order under the control of a program counter;
An architecture determination stage for determining information of an architecture type corresponding to the instruction fetched in the fetch stage;
A decode stage for decoding an instruction fetched in the fetch stage;
An execution stage for performing an operation based on the instruction fetched in the fetch stage;
A WB stage for writing a register by an instruction fetched in the fetch stage,
Further, the decoding stage, the execution stage, and the WB are changed by changing the connection between the plurality of circuit elements and / or the setting in each circuit element based on the architecture type information determined in the architecture determination stage. It has a configuration control unit that performs control to dynamically reconfigure each stage configuration,
The control method is
The architecture type information determined in the architecture determination stage is determined by the pipeline cycle corresponding to the instruction together with the instruction fetched in order by the fetch stage between the decode stage, the execution stage, and the WB stage. The configuration control unit transfers the instructions fetched in order by the fetch stage in accordance with the timing at which the instructions are executed in the decode stage, the execution stage, and the WB stage, and the decode stage, the execution stage, and the WB. A control method comprising performing control for reconfiguring at least a part of the configuration of the stage . A control method of a data processing system for fetching and processing an instruction by pipeline operation,
The data processing system includes a plurality of circuit elements, and dynamically reconnects the circuits by arbitrarily changing connections between the plurality of circuit elements and / or settings in the respective circuit elements within a predetermined range. A plurality of circuit elements comprising ;
Having at least a part of the pipeline constituted by the plurality of circuit elements,
The pipeline fetches instructions from an application program in order under the control of a program counter and fetches architecture type information in units of fetched instructions; and
A decode stage for decoding an instruction fetched in the fetch stage;
An execution stage for performing an operation based on the instruction fetched in the fetch stage;
A WB stage for writing a register by an instruction fetched in the fetch stage,
Further, the decoding stage, the execution stage, and the WB stage are changed by changing the connection between the plurality of circuit elements and / or the setting in each circuit element based on the architecture type information determined in the fetch stage. A configuration control unit that performs control to dynamically reconfigure each of the
The control method is
The architecture type information determined at the fetch stage is transferred between the decode stage, the execution stage, and the WB stage in a pipeline cycle corresponding to the instruction together with the instruction fetched in order by the fetch stage. The configuration control unit is configured so that the instructions fetched in order by the fetch stage are executed in the decode stage, the execution stage, and the WB stage according to the timing of the decode stage, the execution stage, and the WB stage. A control method comprising performing control to reconfigure at least a part of the configuration .

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