JP4610488B2 - Electronic camera - Google Patents

Description

  The present invention relates to an electronic camera, and more particularly to an electronic camera that captures a moving image according to any of a plurality of different frame rates.

An example of a conventional electronic camera of this type is disclosed in Patent Document 1. According to this prior art, the frame rate of a moving image to be shot is switched between 15 fps and 30 fps by a key operation.
JP 2004-236290 A [H04N 5/92, 1/21, 1/41, 5/91]

  However, if the mapping of the evaluation area assigned to the imaging surface for adjustment of image quality-related conditions such as exposure amount and white balance is common for all frame rates, the following problem occurs. That is, if the number of evaluation areas is large, there is a possibility of causing a processing failure when the frame rate is increased. On the other hand, when the number of evaluation areas is small, the adjustment accuracy decreases.

  Therefore, a main object of the present invention is to provide an electronic camera capable of adjusting image quality-related conditions with high accuracy while avoiding processing failure.

  An electronic camera (10) according to the invention of claim 1 includes an imaging means (16) having an imaging surface on which an optical image of an object scene is irradiated, a plurality of periods including a first period and a second period longer than the first period. Generating means (30) for generating a timing signal according to any one of the above, a reading means (28) for reading out the object scene image generated on the imaging surface from the imaging means in response to the timing signal generated by the generating means, First extraction means (58c, 60c, 62c) for extracting image information of L partial images (L: integer greater than or equal to 2) forming the object scene image read by the reading means, read by the reading means Second extracting means (58b, 60b, 62b) for extracting image information of M partial images (M: an integer greater than L) forming the processed object scene image, when the generating means pays attention to the first period When the first extraction means is selected and the generation means pays attention to the second period, the second extraction is performed. Selection means for selecting the stages (S13, S15), and a first adjusting means for adjusting the image quality related condition based on the extraction result of the extraction means selected by the selecting means (S45, S49, S51, S53).

  The imaging means has an imaging surface on which an optical image of the object scene is irradiated. The generating means generates a timing signal according to any one of a plurality of periods including a first period and a second period longer than the first period. The object scene image generated on the imaging surface is read by the reading unit in response to the timing signal generated by the generating unit.

  The first extraction unit extracts image information of L partial images that form the object scene image read by the reading unit. The second extracting unit extracts image information of M partial images forming the object scene image read by the reading unit.

  The first extracting means is selected by the selecting means when the generating means pays attention to the first period, and the second extracting means is selected by the selecting means when the generating means pays attention to the second period. The first adjustment unit adjusts the image quality related condition based on the extraction result of the extraction unit selected by the selection unit.

  Therefore, when the timing signal is generated in the first period, the image quality related condition is adjusted based on the image information of the L partial images. On the other hand, when the timing signal is generated in the second period, the image quality related condition is adjusted based on the image information of the M partial images. Here, since the second period is longer than the first period and M exceeds L, more partial images are referred to as the period of the timing signal is longer.

  As a result, in moving image shooting according to the first cycle, priority is given to shortening the time required for adjustment processing over improvement in the adjustment accuracy of image quality related conditions, and in moving image shooting according to the second cycle, adjustment processing for image quality related conditions is prioritized. The improvement of the adjustment accuracy is prioritized over the time required. As a result, it is possible to avoid the failure of the processing and improve the adjustment accuracy of the image quality related conditions.

  An electronic camera according to a second aspect of the invention is dependent on the first aspect, and the extraction process of the second extraction means is independent of the extraction process of the first extraction means. Thereby, the extraction result extracted by the first extraction unit is generated at the same timing as the extraction result extracted by the second extraction unit.

  The electronic camera according to the invention of claim 3 is dependent on claim 1 or 2, and each of the first extraction means and the second extraction means includes an integration circuit for extracting image quality information by hardware processing. As a result, the image quality information is quickly generated.

  The electronic camera according to the invention of claim 4 is dependent on any one of claims 1 to 3, and includes first recording means (S55) for recording the object scene image periodically read by the reading means as a moving image. Further prepare. In this way, a moving image is recorded.

  An electronic camera according to a fifth aspect of the present invention is dependent on any one of the first to fourth aspects, wherein the first adjustment means includes a plurality of parameter adjustment means (S49, S53) for adjusting a plurality of image quality related parameters, respectively, and generation Activating means for alternatively activating a plurality of parameter adjusting means (S45, S51) in response to a timing signal generated by the means. Thus, the image quality related condition adjustment process is intermittently executed.

  An electronic camera according to a sixth aspect of the present invention is dependent on any one of the first to fifth aspects, wherein N (N: integer greater than M) partial images forming the object scene image read by the read-out means. Third extraction means (58a, 60a, 62a) for extracting image information, second adjustment means (S33) for adjusting image quality related conditions based on the extraction result of the third extraction means when a still image recording operation is performed, And second recording means (S37) for recording an object scene image that matches the image quality-related condition adjusted by the second adjusting means.

  The third extracting unit extracts image information of N partial images forming the object scene image read by the reading unit. The second adjusting means adjusts the image quality related condition based on the extraction result of the third extracting means when the still image recording operation is performed. An object scene image that matches the image quality-related condition adjusted by the second adjusting means is recorded by the second recording means. Here, the second recording means is started after being adjusted by the second adjusting means.

  Therefore, at the time of recording a still image, priority is given to improving the adjustment accuracy over the time required for adjusting the image quality-related conditions.

  An electronic camera according to a seventh aspect of the invention is dependent on the sixth aspect, and the third extracting means includes an integrating circuit for extracting image quality information by hardware processing. As a result, image quality information at the time of still image shooting is quickly generated.

  According to the present invention, when moving images according to the first cycle, reduction of the time required for adjustment processing is prioritized over improvement of the adjustment accuracy of the image quality related conditions, and when moving images according to the second cycle, The improvement of the adjustment accuracy is prioritized over the time required for the adjustment process. As a result, it is possible to avoid the failure of the processing and improve the adjustment accuracy of the image quality related conditions.

  The above object, other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

  Referring to FIG. 1, the camera 10 of this embodiment includes an optical lens 12. The optical image of the object scene is irradiated to the imaging surface of the image sensor 16 through the optical lens 12 and subjected to photoelectric conversion. The aperture unit 14 is driven by a driver 26, whereby the aperture amount is adjusted. The imaging surface of the image sensor 16 is covered by a primary color filter (not shown) of a Bayer array, and the amount of charge generated in each pixel depends on the light intensity of R, G, or B color.

  When the still image shooting mode is selected by the mode switch 36 and a still image shooting operation, that is, an operation of pressing a shutter button (not shown) formed on the camera 10 is performed, a still image shooting process is executed. At this time, 256 divided blocks (see FIG. 2A) divided into 16 in each of the horizontal direction and the vertical direction are allocated to the imaging surface.

  Further, when the moving image shooting mode is selected by the mode switch 36 and the moving image shooting operation, that is, the operation of pressing the shutter button is performed, the moving image shooting processing is executed. If the 15 fps moving image shooting mode, that is, the switching button 38 formed on the camera 10 is in the ON mode, the 15 fps moving image shooting process is performed. At this time, 128 divided blocks (see FIG. 2B) divided into 8 in the horizontal direction and 16 in the vertical direction are assigned to the imaging surface.

  On the other hand, if the 30 fps moving image shooting mode, that is, the switching button 38 is in the off mode, 30 fps moving image shooting processing is performed. At this time, 64 divided blocks (see FIG. 2C) divided into 8 in each of the horizontal direction and the vertical direction are assigned to the imaging surface.

  When a still image shooting operation is performed and the timing generator (TG) 30 generates the vertical synchronization signal Vsync, as shown in FIG. 3A, an adjustment process suitable for the image quality-related condition is performed, and the adjustment result is Based on this, a recording process is performed. The recording process is started after the vertical synchronization signal Vsync is generated 3 to 9 times after the still image shooting operation is performed.

  Specifically, returning to FIG. 1, the CPU 34 first sets an imaging surface for still image shooting, and gives a command to the TG 30 to issue a vertical synchronization signal Vsync every 1/30 seconds. The driver 28 reads the object scene image generated on the imaging surface in response to the vertical synchronization signal Vsync generated every 1/30 seconds, and the raw image signal generated thereby is the raster scanning mode in the image sensor 16. Is output from. The CDS / AGC / AD circuit 18 performs a series of processes of correlated double sampling, automatic gain adjustment, and A / D conversion on the raw image signal output from the image sensor 16, and outputs raw image data that is a digital signal. . The raw image data is subjected to color separation by the color separation circuit 20, and R data, G data, and B data are simultaneously output from the color separation circuit 20. The white balance adjustment circuit 22 performs white balance adjustment on the R data and B data, and outputs the R data, G data, and B data thus obtained to the YUV conversion circuit 24 and the evaluation circuit 32 simultaneously. The YUV conversion circuit 24 performs a matrix operation on the R data, G data, and B data input from the white balance adjustment circuit 22. As a result, image data in the YUV format is generated.

  The evaluation circuit 32 performs evaluation processing on the R data, G data, and B data output from the white balance adjustment circuit 22, and outputs the R evaluation value, the G evaluation value, and the B evaluation value thus obtained to the CPU 34. The CPU 34 performs exposure adjustment and white balance adjustment based on the R evaluation value, the G evaluation value, and the B evaluation value. In this way, the image quality-related conditions are adjusted to suit the recording process.

  When the vertical synchronization signal Vsync is generated from the TG 30 after such adjustment processing is completed, the CPU 34 instructs the TG 30 to perform the main exposure, and the image sensor 16 performs the main exposure by the TG 30. Image data in the YUV format based on the raw image signal obtained by the main exposure is temporarily stored in the SDRAM 42 by the memory control circuit 40, subjected to compression processing by the JPEG codec 48, and recorded on the recording medium via the I / F circuit 52. 54. Thus, the still image shooting process is realized.

  When a moving image shooting operation is performed in the 15 fps moving image shooting mode, as shown in FIG. 3B, in response to a vertical synchronization signal Vsync generated every 1/15 second, shooting condition adjustment processing, that is, exposure adjustment processing and white The balance adjustment process is executed periodically.

  Specifically, returning to FIG. 1, the CPU 34 sets an imaging plane for 15 fps moving image shooting, and gives a command to generate a vertical synchronization signal Vsync every 1/15 seconds to the TG 30. When the vertical synchronization signal Vsync is generated from the TG 30, the object scene image generated on the imaging surface is read out by the driver 28 every 1/15 second, and the generated raw image signal is converted into an image sensor in a raster scanning manner. 16 is output. Then, the same processing as described above is executed, and image data based on the raw image signal obtained by exposure is stored in the SDRAM 42 by the memory control circuit 40.

  The video encoder 44 gives a read request to the memory control circuit 40. In response to this request, the memory control circuit 40 converts the image data from the SDRAM 42 into a composite video signal conforming to the NTSC format, and supplies the converted composite video signal to the LCD monitor 46. As a result, a through image every 1/15 seconds is displayed on the monitor screen.

  The CPU 34 also activates the MPEG-4 codec 50. Each time the vertical synchronization signal Vsync is generated, the MPEG-4 codec 50 reads the image data of each frame from the SDRAM 42 and performs a compression process according to the MPEG-4 format on the read image data. The image data is intra-encoded at a rate of about once every 15 frames, and inter-encoded with the remaining frames. The compressed moving image data generated by the compression process, that is, MPEG data is written in the SDRAM 42. The compressed moving image data stored in the SDRAN 42 is recorded on the recording medium 54 via the I / F circuit 52. In this way, moving image shooting processing at 15 fps is realized.

  The transfer speed of the image data on the bus 56 is much faster than the processing speed of each of the YUV conversion circuit 24, the video encoder 44, the JPEG codec 48, and the MPEG-4 codec 50. For this reason, the image data does not collide on the bus 56, and the data transfer process does not fail.

  According to FIG. 3B, the reference value i is “0”, “1”, “2”, “0”, “1”, “2”... Every time the vertical synchronization signal Vsync is generated. Repeated cyclically. When the reference value i is “0”, the CPU 34 calculates a Y evaluation value from the R evaluation value, the G evaluation value, and the B evaluation value obtained from the evaluation circuit 32, and performs exposure adjustment based on the Y evaluation value. . When the reference value i is “1”, the CPU 34 performs white balance adjustment based on the R evaluation value, the G evaluation value, and the B evaluation value obtained from the evaluation circuit 32. When the reference value i is “2”, the CPU 34 waits for synchronization. In this way, the image quality-related conditions are adjusted as appropriate to suit the recording process.

  Also, when a moving image shooting operation is performed in a 30 fps moving image shooting mode, shooting condition adjustment processing is periodically performed in response to a vertical synchronization signal Vsync generated every 1/30 seconds, as shown in FIG. Executed.

  Specifically, returning to FIG. 1, the CPU 34 sets the imaging surface for 30 fps moving image shooting, and gives a command to the TG 30 to generate the vertical synchronization signal Vsync every 1/30 seconds. When the vertical synchronization signal Vsync is generated from the TG 30, the object scene image generated on the imaging surface is read by the driver 28 every 1/30 seconds, and the same processing as described above is executed every 1/30 seconds. Is done. The image data is intra-encoded at a rate of about once every 30 frames, and inter-encoded with the remaining frames.

  Referring to FIG. 4, evaluation circuit 32 is configured by hardware, integrating circuits 58a-58c, selector 58d, buffer 58e, integrating circuits 60a-60c, selector 60d, buffer 60e, integrating circuits 62a-62c, selector 62d. , A buffer 62e, and a selector 64.

  Each of the integration circuits 58a, 60a, and 62a pays attention to 256 divided blocks allocated to the imaging surface in the manner shown in FIG. Each of the integration circuits 58b, 60b and 62b pays attention to 128 divided blocks allocated to the imaging surface in the manner shown in FIG. Each of the integration circuits 58c, 60c and 62c pays attention to the 64 divided blocks allocated to the imaging surface in the manner shown in FIG.

  The integration circuit 58a integrates the data values of the R data belonging to each of the 256 divided blocks to obtain 256 R evaluation values, and the integration circuit 58b performs the data of the R data belonging to each of the 128 divided blocks. The values are integrated to obtain 128 R evaluation values, and the integration circuit 58c integrates the data values of the R data belonging to each of the 64 divided blocks to obtain 64 R evaluation values.

  The integrating circuit 60a integrates the data values of the G data belonging to each of the 256 divided blocks to obtain 256 G evaluation values, and the integrating circuit 60b performs the data of the G data belonging to each of the 128 divided blocks. The values are integrated to obtain 128 G evaluation values, and the integration circuit 60c integrates the data values of the G data belonging to each of the 64 divided blocks to obtain 64 G evaluation values.

  The integrating circuit 62a integrates the data values of B data belonging to each of the 256 divided blocks to obtain 256 B evaluation values, and the integrating circuit 62b provides data of B data belonging to each of the 128 divided blocks. The values are integrated to obtain 128 B evaluation values, and the integration circuit 62c integrates the data values of the B data belonging to each of the 64 divided blocks to obtain 64 B evaluation values.

  All of the integration circuits 58a to 58c, 60a to 60c, and 62a to 62c execute the above integration by hardware processing.

  As described above, the extraction processing of the integration circuits 58a to 58c is independent of the extraction processing of the integration circuits 60a to 60c and the extraction processing of the integration circuits 62a to 62c, and the extraction processing of the integration circuits 60a to 60c is the integration circuits 62a to 62c. Independent from the extraction process. Thus, the R evaluation value integrated by the integration circuits 58a to 58c is generated at the same timing as the G evaluation value integrated by the integration circuits 60a to 60c and the B evaluation value integrated by the integration circuits 62a to 62c.

  When a still image shooting operation is performed, the CPU 34 issues a command for selecting the integration circuits 58a, 60a, and 62a to the selectors 58d, 60d, and 62d to set the imaging surface for still image shooting. The selector 58d stores the R evaluation value output from the integration circuit 58a in the buffer 58e, the selector 60d stores the G evaluation value output from the integration circuit 60a in the buffer 60e, and the selector 62d is output from the integration circuit 62a. The B evaluation value is stored in the buffer 58e.

  The selector 64 outputs the R evaluation value stored in the buffer 58e, the G evaluation value stored in the buffer 60e, and the B evaluation value stored in the buffer 62e to the register 34r formed in the CPU 34 at a time. As a result, image information based on 256 divided blocks is obtained.

  On the other hand, when a moving image shooting operation is performed with the switching button 38 turned on, the CPU 34 issues a command for selecting the integrating circuits 58b, 60b and 62b to set the imaging surface for 15 fps moving image shooting, and the selectors 58d, 60d and Issued to 62d. Then, the same processing as described above is executed.

  The selector 64 also outputs the G evaluation value stored in the buffer 60e, the R evaluation value stored in the buffer 58e, and the B evaluation value stored in the buffer 62e to the register 34r at a time. As a result, image information based on 128 divided blocks is obtained.

  Further, when the moving image shooting operation is performed with the switching button 38 in the off state, the CPU 34 issues a command for selecting the integrating circuits 58c, 60c and 62c to set the imaging surface for 30 fps moving image shooting, and the selectors 58d, 60d and Issued to 62d. Then, the same processing as described above is executed, and as a result, image information based on 64 divided blocks is obtained.

  Adjustment processing performed intermittently in the moving image shooting mode will be specifically described with reference to FIGS. 5 (A) and 5 (B). According to FIG. 5A, when a first vertical synchronization signal Vsync is generated among the vertical synchronization signals Vsync generated every 1/15 seconds, the second vertical synchronization signal Vsync is generated after the first vertical synchronization signal Vsync is generated. Exposure is performed before the vertical synchronization signal Vsync is generated. When the second vertical synchronization signal Vsync is generated, R data belonging to each of 128 divided blocks, G data belonging to each of 128 divided blocks, and B data belonging to each of 128 divided blocks based on this exposure. Are transferred to the evaluation circuit 32 until the third vertical synchronization signal Vsync is generated. When the third vertical synchronization signal Vsync is generated, the CPU 34 fetches 128 R evaluation values, 128 G evaluation values, and 128 B evaluation values from the evaluation circuit 32, and the 128 R evaluations thus taken in. The image quality-related condition is adjusted based on the value, 128 G evaluation values, and 128 B evaluation values.

  According to FIG. 5B, when a first vertical synchronization signal Vsync is generated among the vertical synchronization signals Vsync generated every 1/30 seconds, the second vertical synchronization signal Vsync is generated after the first generation. Exposure is performed before the vertical synchronization signal Vsync is generated. When the second vertical synchronization signal Vsync is generated, R data belonging to each of the 64 divided blocks, G data belonging to each of the 64 divided blocks, and B data belonging to each of the 64 divided blocks based on this exposure. Are transferred to the evaluation circuit 32 until the third vertical synchronization signal Vsync is generated. When the third vertical synchronization signal Vsync is generated, the CPU 34 fetches 64 R evaluation values, 64 G evaluation values, and 64 B evaluation values from the evaluation circuit 32, and the 64 R evaluations thus fetched. The image quality-related condition is adjusted based on the value, the 64 G evaluation values, and the 64 B evaluation values.

  As described above, the integration circuits 58c, 60c, and 62c extract the image information of the 64 divided blocks that form the object scene image read by the driver 28. Further, the integration circuits 58b, 60b and 62b extract the image information of 128 divided blocks forming the object scene image read by the driver 28.

  The integration circuits 58c, 60c and 62c are selected by the CPU 34 when the TG 30 generates the vertical synchronization signal Vsync every 1/30 seconds, and the integration circuits 58b, 60b and 62b are selected by the TG 30 for the vertical synchronization signal Vsync every 1/15 seconds. Is selected by the CPU 34. The CPU 34 adjusts the image quality related condition based on the image information output from the evaluation circuit 32.

  Therefore, when the vertical synchronization signal Vsync is generated at 1/30 seconds, the image quality related condition is adjusted based on the image information of the 64 divided blocks. On the other hand, when the vertical synchronization signal Vsync is generated at 1/15 seconds, the image quality related condition is adjusted based on the image information of 128 divided blocks. Here, since 1/15 seconds is longer than 1/30 seconds and 128 exceeds 64, more divided blocks are referred to as the period of the vertical synchronization signal Vsync is longer.

  As a result, when moving images at 30 fps, priority is given to reducing the time required for adjustment processing over improvement of the adjustment accuracy of image quality-related conditions, and when moving images at 15 fps, the time required for adjustment processing of image quality-related conditions. Improvement of adjustment accuracy is prioritized. As a result, it is possible to avoid the failure of the processing and improve the adjustment accuracy of the image quality related conditions.

  When the photographing operation is performed, the CPU 34 specifically performs processing according to the flowcharts shown in FIGS. A control program corresponding to this flow is stored in a flash memory (not shown).

  First, it is determined in step S1 shown in FIG. 6 whether or not a still image shooting operation has been performed. If the still image shooting operation is not performed, the process proceeds to step S7. If the still image shooting operation is performed, a command for selecting the integration circuits 58a, 60a, and 62a is issued to the evaluation circuit 32 in step S3. At this time, the selectors 58d, 60d and 62d store the R evaluation value, G evaluation value and B evaluation value output from the integration circuits 58a, 60a and 62a in the buffers 58e, 60e and 62e, respectively. As a result, the R evaluation value, the G evaluation value, and the B evaluation value of each of the 256 divided blocks are generated by the evaluation circuit 32.

  In step S5, still image processing is executed. Thereby, high-resolution image data based on the still image shooting operation is generated.

  In step S7, it is determined whether or not a moving image shooting operation has been selected. If the moving image shooting operation is not performed, other processing is performed in step S9. When this processing is completed, the process returns to step S1. On the other hand, when the moving image shooting operation is performed, it is determined in step S11 whether or not the 15 fps moving image shooting mode is set.

  If the switch button 38 is in the ON state, a command for selecting the integration circuits 58b, 60b, and 62b is issued to the evaluation circuit 32 in step S13. At this time, the selectors 58d, 58d and 62d store the R evaluation value, the G evaluation value and the B evaluation value output from the integration circuits 58b, 60b and 62b in the buffers 58e, 60e and 62e, respectively. As a result, the R evaluation value, the G evaluation value, and the B evaluation value of each of the 128 divided blocks are generated by the evaluation circuit 32.

  On the other hand, if the switching button 38 is in the OFF state, a command for selecting the integration circuits 58c, 60c and 62c is issued to the evaluation circuit 32 in step S15. At this time, the selectors 58d, 60d, and 62d store the R evaluation value, the G evaluation value, and the B evaluation value output from the integration circuits 58c, 60c, and 62c in the buffers 58e, 60e, and 62e, respectively. As a result, the R evaluation value, the G evaluation value, and the B evaluation value of each of the 64 divided blocks are generated by the evaluation circuit 32.

  In step S17, initialization is performed. At this time, the reference value i is set to “0”. In step S19, a moving image shooting process is performed. When this process is finished, it is determined in step S21 whether a moving image shooting end operation has been performed. If the determination result is NO, the process returns to step S19, and if the determination result is YES, the process returns to step S1.

  The still image shooting process in step S5 follows a subroutine shown in FIG. In step S31, the process waits until the vertical synchronization signal Vsync is given. When the vertical synchronization signal Vsync is given, an adjustment process suitable for the image quality-related condition is performed in step S33. When this adjustment process is completed, the process waits until the vertical synchronization signal Vsync is given in step S35. When the vertical synchronization signal Vsync is given, a recording process based on the adjustment result is performed in step S37. When the recording process is completed, the process returns to the upper routine.

  The moving image shooting process in step S19 follows a subroutine shown in FIG. In step S41, the process waits until the vertical synchronization signal Vsync is given. When the vertical synchronization signal Vsync is given, the R evaluation value, the G evaluation value, and the B evaluation value are fetched from the evaluation circuit 32 in step S43. At this time, the selector 64 outputs the R evaluation value stored in the buffer 58e to the register 34r, the G evaluation value stored in the buffer 60e to the register 34r, and the B evaluation value stored in the buffer 62e. Output to the register 34r.

  In step S45, it is determined whether or not the reference value i is “0”. If the determination result is NO, the process proceeds to step S51. If the determination result is YES, the Y evaluation value is calculated from the acquired R evaluation value, G evaluation value, and B evaluation value in step S47. In step S49, an exposure adjustment process is executed based on the Y evaluation value. Thereby, the shutter speed and the aperture amount at which the exposure is optimal at this point are adjusted.

  In step S51, it is determined whether or not the reference value i is “1”. If the determination result is NO, the reference value i is determined to be “2”, and the process proceeds to step S55. If the determination result is YES, the captured R evaluation value, G evaluation value, and B evaluation value are acquired in step S53. The white balance adjustment process is executed based on the above. As a result, the R gain and B gain at which the white balance is optimal at this point are set.

  In step S55, the object scene image periodically read by the driver 28 is recorded as a moving image. In this way, a moving image is recorded on the recording medium 54.

  In step S57, the reference value i is incremented, and in step S59, it is determined whether or not the reference value i exceeds “2”. If the determination result is NO, the process returns to the upper routine. If the determination result is YES, the reference value i is set to “0” in step S61, and then the process returns to the upper routine.

It is a block diagram which shows the structure of one Example of this invention. (A) is an illustrative view showing an example of divided areas formed on the screen, (B) is an illustrative view showing another example of divided areas formed on the screen, and (C) is formed on the screen. It is an illustration figure which shows another example of the divided area made. (A) is an illustrative view showing an example of operation during still image shooting processing, (B) is an illustrative view showing an example of operation during 15 fps moving image shooting processing, and (C) is during 30 fps moving image shooting processing. It is an illustration figure which shows an example of operation | movement of. It is an illustration figure which shows an example of a structure of the evaluation circuit applied to the FIG. 1 Example. (A) is an illustrative view showing an example of an operation during a 15 fps moving image shooting process, and (B) is an illustrative view showing an example of an operation during a 30 fps moving image shooting process. It is a flowchart which shows a part of operation | movement of CPU applied to the FIG. 1 Example. It is a flowchart which shows a part of other operation | movement of CPU applied to the FIG. 1 Example. It is a flowchart which shows a part of other operation | movement of CPU applied to the FIG. 1 Example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Camera 16 ... Image sensor 22 ... White balance adjustment circuit 28 ... Driver 30 ... Timing generator 32 ... Evaluation circuit 34 ... CPU
42 ... SDRAM
58a to 58c, 60a to 60c, 62a to 62c ... integration circuit 58e, 60e, 62e, 64 ... selector 58e, 60e, 62e ... buffer

Claims (8)

An imaging means having an imaging surface on which an optical image of the object scene is irradiated;
Generating means for generating a timing signal according to any one of a plurality of periods including a first period and a second period longer than the first period;
A reading means for reading out the object scene image generated on the imaging surface from the imaging means in response to a timing signal generated by the generating means;
First extraction means for extracting image information of L (L: integer greater than or equal to 2) partial images forming the scene image read by the reading means;
Second extraction means for extracting image information of M (M: integer greater than or equal to 2) partial images forming the scene image read by the reading means;
Selection means for selecting the first extraction means when the generation means pays attention to the first period, selection means for selecting the second extraction means when the generation means pays attention to the second period, and selection by the selection means An electronic camera comprising first adjusting means for adjusting image quality related conditions based on the extraction result of the extracted extracting means.   The electronic camera according to claim 1, wherein the extraction process of the second extraction unit is independent of the extraction process of the first extraction unit. The reading means reads the object scene image in a raster scanning manner,
The electronic camera according to claim 1, wherein the adjustment unit adjusts the image quality related condition during a vertical blanking period.   4. The electronic camera according to claim 1, wherein each of the first extraction unit and the second extraction unit includes an integration circuit for extracting the image quality information by hardware processing. 5.   5. The electronic camera according to claim 1, further comprising a first recording unit configured to record the object scene image periodically read by the reading unit as a moving image.   The adjusting unit includes a plurality of parameter adjusting units that respectively adjust a plurality of image quality-related parameters, and an activation unit that alternatively starts the plurality of parameter adjusting units in response to a timing signal generated by the generating unit. The electronic camera according to claim 1, further comprising: Third extraction means for extracting image information of N (N: integer greater than M) partial images forming the object scene image read by the reading means;
A second adjustment unit that adjusts the image quality-related condition based on an extraction result of the third extraction unit when a still image recording operation is performed; and a subject that satisfies the image quality-related condition adjusted by the second adjustment unit The electronic camera according to claim 1, further comprising second recording means for recording a field image.   The electronic camera according to claim 7, wherein the third extraction unit includes an integration circuit for extracting the image quality information by hardware processing.

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