JP4618957B2 - Crystalline silicon film forming method, semiconductor device, and display device - Google Patents

Description

【００５０】
表１及び図１１のグラフをそれぞれ参照すると、試料１における優先配向結晶方位は（１１１）であり、その占有面積は、６８％である。
【００５１】
膜中水素濃度が試料１より低減された試料２では、優先配向結晶方位は、試料１と同じく（１１１）であるが、その占有面積は５４％であり、試料１の占有面積よりも低下している。
【００５２】
膜中水素濃度が試料２よりも低減された試料３では、優先配向結晶方位は、（１１１）ではなく、（１１０）となっており、その占有面積は４７％となっている。
【００５３】
図１１を参照して明らかなように、膜中水素濃度が低減すると共に、（１１１）の結晶方位が、低減され、（１１０）の結晶方位が増加している。その原因としては、以下のように考えられる。
【００５４】
触媒物質導入領域４３に導入されたニッケルが、非晶質シリコン膜４１中のシリコンと結合して形成されるニッケルシリサイドは、非晶質シリコン膜４１を結晶化させながら横方向に移動し、移動方向の後ろ側には、結晶性のシリコン膜が形成される。このようにして形成される結晶性シリコン膜４１の基板垂直方向の結晶方位は、（１１０）になることが、Ｈａｙｚｅｌｄｅｎ等によってＪ．Ａｐｐｌ．Ｐｈｙｓ．Ｖｏｌ．７３，Ｎｏ．１２，１９９３に報告されている。
【００５５】
一方、ガラス基板４０上に、成膜温度３５０℃で、ＳｉＨ₄ガスを用いたプラズマＣＶＤ法を行うことによって膜厚５０ｎｍに形成された非晶質シリコン膜４１を、５７０℃の温度で、２０時間にわたって加熱処理すると、非晶質シリコン膜４１中に自然核が発生し、この自然核に基づいて結晶化が進行する。このように結晶化された試料について、Ｘ線解析測定法により結晶方位を測定したところ、（１１１）の結晶方位に基づく回折ピークのみが観察された。この結果は、自然核及びこの自然核に基づいて成長された結晶は、（１１１）面の結晶方位に優先的に配向することを示す。
【００５６】
上記の試料１及び２では、非晶質シリコン膜４１中に含まれる水素濃度が高いので、加熱処理により水素が抜けた後のダングリングボンドの歪みにより、自然核が発生し易くなっており、この自然核によって、形成される結晶性シリコンの結晶方位が、（１１１）に優先的に配向していると考えられる。この場合、試料１及び２におけるニッケルシリサイドは、結晶化速度を早めるのみの作用を有していると考えられる。
【００５７】
これに対して、試料３では、非晶質シリコン膜４１中に含まれる水素濃度が低くなっているために自然核の発生が少なく、ニッケルシリサイドを結晶核とする結晶化が支配的になっていると考えられる。その結果、ニッケルシリサイドの影響によって、形成される結晶性シリコンの結晶方位が、（１１０）に優先的に配向していると考えられる。
【００５８】
上記に説明したように、試料１では、形成される結晶性シリコン膜は、（１１１）面の占有面積が高く、基板垂直方向の結晶方位は、大略（１１１）に揃えることができる。
【００５９】
ただし、このように、膜中に含まれる水素濃度が高くなるようにして、基板垂直方向の結晶方位を大略（１１１）面に揃えても、基板の横方向（図１０のＸ及びＹ方向）の結晶方位は揃わない。
【００６０】
このため、基板の垂直方向の結晶方位を揃えると共に、基板の横方向にも結晶方位を揃える場合には、図１０（ｃ）のように、結晶の成長方向に対して、直交する方向の寸法が狭小になるようにくびれた連結部を有するように、非晶質シリコン膜をパターニングする。このようにすれば、結晶成長するそれぞれの結晶方位を有する複数の結晶粒のうち、連結部にて、単一の結晶粒が選択され、結晶成長方向に対して連結部の前方部では、選択された単一の結晶粒によって結晶成長された結晶粒界のない単結晶領域を形成することができる。
【００６１】
この場合、結晶成長は、触媒物質によって促進されるため、連結部に過度の温度上昇を生じさせる程の高温熱処理を実施する必要がないので、耐熱性に優れていないガラス基板を用いても、結晶化を行うことができる。
【００６２】
このようにして、基板垂直方向の結晶方位が、大略（１１１）に揃っていると共に、基板の横方向の結晶方位も、大略揃った結晶性のシリコン膜を形成することができる。
【００６３】
以下、本発明の結晶性半導体膜の形成方法の具体的な形態について、図面に基づいて説明する。
【００６４】
（実施の形態１）
図１（ａ）及び（ｂ）は、それぞれ、本実施の形態１の結晶性半導体膜の形成方法を工程毎に説明する斜視図である。
【００６５】
まず、プラズマＣＶＤ法によって、ガラス基板４０上の全面にわたって、非晶質シリコン膜４１を５０ｎｍの膜厚に均一に形成する。成膜に用いる材料ガスとして、ＳｉＨ₄を用い、基板温度は３００℃とする。
【００６６】
次に、ガラス基板４０上に形成された非晶質シリコン膜４１に対して、ＣＦ₄ガスとＯ₂ガスとを用いた反応性イオンエッチング（ＲＩＥ）法によって、エッチングし、図１（ａ）に示すように、ガラス基板４０の長手方向に対して直交する幅方向の寸法が一定になっている第一主領域４１ａ及び第二主領域４１ｃの間に、幅方向寸法が狭小になっている連結領域４１ｂを有するようにパターニングする。連結領域４１ｂは、幅方向の寸法が５μｍ、長手方向に沿った長手方向寸法が２０μｍとした。
【００６７】
次に、ＳｉＨ₄ガスとＯ₂ガスとを用いた常圧ＣＶＤ法によって、非晶質シリコン膜４１を成膜したガラス基板４０の全面にわたって、ＳｉＯ₂膜４２を１００ｎｍの膜厚に形成する。続いて、ＲＩＥ法によって、ＳｉＯ₂膜４２において、非晶質シリコン膜４１の第一主領域４１ａ上に該当する位置を、図１（ｂ）に示すように、矩形状にエッチングして除去し、触媒物質が導入される触媒物質導入領域４３とする。
【００６８】
次に、スパッタリング法を用いて、全面にわたってニッケル（Ｎｉ）を蒸着する。本実施の形態１では、ニッケルの表面原子濃度は、１×１０¹³〜５×１０¹³個／ｃｍ²とした。
【００６９】
次に、電気炉を用いて熱処理を実施する。この熱処理の条件は、例えば、５５０℃、４時間とする。この熱処理により、最初に触媒物質導入領域４３に結晶核が発生し、この結晶核を種として結晶成長が進行する。
【００７０】
本実施の形態１では、ガラス基板４０上に形成された非晶質シリコン膜４１が、３００℃の温度条件で成膜され、膜中に含まれる水素濃度が高くなっているため、基板の垂直方向の結晶方位は、大略（１１１）に揃っている。
【００７１】
また、この触媒物質導入領域４３に発生した多数の結晶核は、横方向に結晶成長が進行する際に、連結領域４１ｂにて、単一の結晶粒が選択される。
【００７２】
したがって、第一主領域４１ａの触媒物質導入領域４３にて発生した結晶核が、連結領域４１ｂを経て、第二主領域４１ｃに結晶成長が進行すると、第二主領域４１ｃでは、ガラス基板４０の垂直方向の結晶方位が、大略（１１１）に揃っており、且つ、ガラス基板４０の横方向の結晶方位も大略揃った結晶性のシリコン膜に結晶化される。
【００７３】
次に、ほぼ全面にわたって形成されたＳｉＯ₂膜４２をエッチングにより除去した後、レーザ照射による結晶化を行い、加熱により結晶化されたシリコン膜４１をさらに完全に結晶化する。このレーザ照射に用いられるレーザのエネルギーは、３５０〜４００ｍＪ／ｃｍ²の範囲に設定される。
【００７４】
このようにして形成された結晶性シリコン膜４１の結晶方位をＥＢＳＰ法により測定すると、第二主領域４１ｃにおける結晶性シリコン膜の基板垂直方向の結晶方位は、大略（１１１）に揃っていた。
【００７５】
連結領域４１ｂを設置することによるガラス基板４０の横方向の結晶方位の選択性を向上するためには、第一主領域４１ａにおいて、触媒物質導入領域４３の端部から連結領域４１ｂまでに、所定の間隔が形成される。図２は、この間隔ａを説明するための平面図である。間隔ａは、０．５〜５０μｍに設定される。間隔ａが、０．５μｍより小さい場合には、連結領域４１ｂによる結晶方位の選択性が低くなる。
【００７６】
（実施の形態２）
図３（ａ）及び（ｂ）は、それぞれ、本実施の形態２の結晶性半導体膜の形成方法を説明する斜視図である。
【００７７】
本実施の形態２は、前述の実施の形態１の結晶性半導体膜の形成方法と概略同様の工程にて行われるが、連結領域４１ｂから第二主領域４１ｃにかけて、エッジ形状が生じないように滑らかに連続するように、非晶質シリコン膜４１をパターニングしている点が、実施の形態１と異なっている。
【００７８】
以下、具体的に説明する。
【００７９】
まず、実施の形態１と同様にして、ガラス基板４０上に非晶質シリコン膜４１を５０ｎｍの膜厚に均一に形成する。
【００８０】
次に、ガラス基板４０上に形成された非晶質シリコン膜４１に対して、ＣＦ₄ガスとＯ₂ガスとを用いたＲＩＥ法によって、エッチングし、図３（ａ）に示すように、ガラス基板４０の長手方向に対して直交する幅方向の寸法が一定になっている第一主領域４１ａ及び第二主領域４１ｃの間に、幅方向寸法が狭小になっている連結領域４１ｂを有するようにパターニングする。連結領域４１ｂは、幅方向の寸法が５μｍ、長手方向に沿った長手方向寸法が２０μｍとした。本実施の形態２では、さらに、連結領域４１ｂから第二主領域４１ｃにかけて、連結領域４１ｂの幅寸法が、滑らかな湾曲形状を形成しながら徐々に幅方向寸法が大きくなっていき、連結領域４１ｂと第二主領域４１ｃとの間でエッジ形状が生じないように非晶質シリコン膜４１をパターニングしている。
【００８１】
図４には、このようにパターニングされた非晶質シリコン膜４１の平面図を示している。このような連結領域４１ｂと第二主領域４１ｃとの間に形成される滑らかな湾曲形状は、例えば、略円周の１／４の湾曲部を２つ連続してつなぎ合わせることにより形成される。
【００８２】
次に、ＳｉＨ₄ガスとＯ₂ガスとを用いた常圧ＣＶＤ法によって、非晶質シリコン膜４１を成膜したガラス基板の全面にわたって、ＳｉＯ₂膜４２を１００ｎｍの膜厚に形成する。続いて、ＲＩＥ法によって、非晶質シリコン膜４１の第一主領域４１ａ上に該当する位置のＳｉＯ₂膜４２を、図３（ｂ）に示すように、矩形状にエッチングして、触媒物質が導入される触媒物質導入領域４３とする。
【００８３】
次に、スパッタリング法を用いて、全面にわたってニッケル（Ｎｉ）を蒸着する。本実施の形態２では、ニッケルの表面原子濃度は、１×１０¹³〜５×１０¹³個／ｃｍ²とした。
【００８４】
次に、電気炉を使用して熱処理を実施する。この熱処理の条件は、５５０℃、４時間とする。この熱処理により、最初に触媒物質導入領域４３に結晶核が発生し、この結晶核を種として結晶成長が進行する。
【００８５】
本実施の形態２では、ガラス基板４０上に形成された非晶質シリコン膜４１が、３００℃の温度条件で成膜され、膜中に含まれる水素濃度が高くなっているため、基板の垂直方向の結晶方位は、大略（１１１）に揃っている。
【００８６】
また、この触媒物質導入領域４３に発生した多数の結晶核は、横方向に結晶成長が進行するに際して、連結領域４１ｂにて単一の結晶粒が選択される。
【００８７】
したがって、第一主領域４１ａの触媒物質導入領域４３にて発生した結晶核が、連結領域４１ｂを経て、第二主領域４１ｃに結晶成長が進行すると、第二主領域４１ｃでは、基板の垂直方向の結晶方位が、大略（１１１）に揃っており、且つ、基板の横方向の結晶方位も大略揃った結晶性のシリコン膜に結晶化される。
【００８８】
さらに、本実施の形態２では、連結領域４１ｂから第二主領域４１ｃにかけて、連結領域４１ｂの幅寸法が、滑らかな湾曲形状を形成しながら徐々に幅方向寸法が大きくなっていき、連結領域４１ｂと第二主領域４１ｃとの間でエッジ形状が生じないように滑らかに連続しているので、エッジ形状が形成された部分で不規則な結晶核が発生することを抑制することができる。
【００８９】
図５には、本実施の形態２とは異なり、連結領域４１ｂと第二主領域４１ｃとが、滑らかに連続せず、エッジ形状を有するように非晶質シリコン膜４１がパターニングされた場合を示す平面図である。このように、連結領域４１ｂと第二主領域４１ｃとの間で、エッジ形状が生じている場合には、連結領域４１ｂにて、単一の結晶方位を有する結晶粒１０１が選択されても、エッジ部で発生した不規則な核、具体的には、（１１２）面、（１１４）面、（１２３）面、（３３４）面、（３４５）面等の非（１１１）面方位を持った結晶核が発生して、第二主領域４１ｃにおいて、非（１１１）面方位を有する結晶粒１０２と、連結領域４１ｂにて選択された（１１１）面方位を有する結晶粒１０１とが結晶成長して、各結晶粒間に、結晶粒界１０３が発生する。このため、図５に示すように、非晶質シリコン膜４１をパターニングすると、結晶方位が大略揃った結晶性のシリコン膜を得ることができなくなる。
【００９０】
次に、ほぼ全面にわたって形成されたＳｉＯ₂膜４２をエッチングにより除去した後、レーザ照射による結晶化を行い、加熱により結晶化されたシリコン膜をさらに完全に結晶化する。
（実施の形態３）
図６（ａ）〜（ｃ）は、それぞれ、本実施の形態３の結晶性半導体膜の形成方法を説明する斜視図である。
【００９１】
本実施の形態３は、前述の実施の形態１の結晶性半導体膜の形成方法と概略同様の工程によって行われるが、結晶化される非晶質シリコン膜が、基板上に形成された溝部に埋め込まれた状態に形成され、非晶質シリコン膜の第一及び第二主領域及び連結領域のそれぞれの側面部と底面部とが滑らかに連続する形状を有している点が、実施の形態１と異なっている。
【００９２】
以下、具体的に説明する。
【００９３】
まず、ＣＦ₄ガスを用いたＲＩＥ法と緩衝フッ酸による湿式エッチングとを組み合わせて行うことにより、ガラス基板４０の表面上に、溝部４４を形成する。この溝部４４は、図６（ａ）に示すように、ガラス基板４０の長手方向に対して直交する幅方向の寸法が一定になっている第一主領域４４ａ及び第二主領域４４ｃの間に、幅方向寸法が狭小になっている連結領域４４ｂを有するようにパターニングされて形成される。
【００９４】
図７には、溝部４４が形成されたガラス基板４０の長手方向に直交する方向の断面図を示している。このように形成された溝部４４は、側面部と底面部をが滑らかに連続する湾曲形状に形成される。この溝部４４の湾曲形状は、例えば、溝部４４の側面部を略円周の１／４となるように形成される。
【００９５】
次に、実施の形態１と同様にして、非晶質シリコン膜４１を５０ｎｍの膜厚に均一に形成する。
【００９６】
次に、ガラス基板４０上に形成された非晶質シリコン膜４１に対して、ＣＦ₄ガスとＯ₂ガスとを用いたＲＩＥ法によってエッチングし、図６（ｂ）に示すように、溝部４４に埋め込まれた状態になっている非晶質シリコン膜４１以外の部分の非晶質シリコン膜を除去する。
【００９７】
次に、ＳｉＨ₄ガスとＯ₂ガスとを用いた常圧ＣＶＤ法によって、非晶質シリコン膜４１が、ガラス基板４０の表面上に形成された溝部４４に埋め込まれているガラス基板４０の全面にわたって、ＳｉＯ₂膜４２を１００ｎｍの膜厚に形成する。続いて、ＲＩＥ法によって、非晶質シリコン膜４１の第一主領域４１ａに該当する位置のＳｉＯ₂膜４２を、図６（ｃ）に示すように、矩形状にエッチングして除去し、触媒物質が導入される触媒物質導入領域４３とする。
【００９８】
次に、スパッタリング法を用いて、全面にわたってニッケル（Ｎｉ）を蒸着する。本実施の形態３では、ニッケルの表面原子濃度は、１×１０¹³〜５×１０¹³個／ｃｍ²とした。
【００９９】
次に、電気炉を用いて熱処理を実施する。この熱処理の条件は、例えば、５５０℃、４時間とする。この熱処理により、最初に触媒物質導入領域４３に結晶核が発生し、この結晶核を種として結晶成長が進行する。
【０１００】
本実施の形態３では、ガラス基板４０上の溝部４４に埋め込まれた非晶質シリコン膜４１が、３００℃の温度条件で成膜され、膜中に含まれる水素濃度が高くなっているため、基板の垂直方向の結晶方位は、大略（１１１）に揃っている。
【０１０１】
また、この触媒物質導入領域４３に発生した多数の結晶核は、横方向に結晶成長が進行する際に、連結領域４１ｂにて、単一の結晶粒が選択される。
【０１０２】
したがって、第一主領域４１ａの触媒物質導入領域４３にて発生した結晶核が、連結領域４１ｂを経て、第二主領域４１ｃに結晶成長が進行すると、第二主領域４１ｃでは、ガラス基板４０の垂直方向の結晶方位が、大略（１１１）に揃っており、且つ、ガラス基板４０の横方向の結晶方位も大略揃った結晶性のシリコン膜に結晶化される。
【０１０３】
さらに、本実施の形態３では、非晶質シリコン膜４１が、ガラス基板４０上に形成された溝部４４に埋め込まれるように形成されており、第一主領域４１ａ及び連結領域４１ｂ及び第二主領域４１ｃの各領域にわたって、その側面部と底面部とが滑らかに連続する湾曲形状に形成されているので、非晶質シリコン膜４１の側面及び底面との連続部でエッジ形状が形成されない。したがって、エッジ形状が形成された部分で不規則な結晶核、具体的には、（１１２）面、（１１４）面、（１２３）面、（３３４）面、（３４５）面等各種面方位を持った結晶核が発生することを抑制することができる。
【０１０４】
次に、ほぼ全面にわたって形成されたＳｉＯ₂膜４２をエッチングにより除去した後、レーザ照射による結晶化を行い、加熱により結晶化されたシリコン膜をさらに完全に結晶化する。
（実施の形態４）
図８（ａ）〜（ｃ）は、それぞれ、本実施の形態４の結晶性半導体膜の形成方法を説明する斜視図である。
【０１０５】
本実施の形態４は、前述の実施の形態１の結晶性半導体膜の形成方法と概略同様の工程によって行われるが、結晶化される非晶質シリコン膜が、基板上に形成された溝部に埋め込まれた状態に形成され、非晶質シリコン膜の第一及び第二主領域及び連結領域のそれぞれの側面部と底面部とが滑らかに連続する形状を有している。また、連結領域から第二主領域にかけて、エッジ形状が生じないように滑らかに連続するように、溝部が形成されている。すなわち、本実施の形態４は、前述の実施の形態２と実施の形態３とを組み合わせた非晶質シリコン膜の形状を有するようにしたものである。
【０１０６】
以下、具体的に説明する。
【０１０７】
まず、ＣＦ₄ガスを用いたＲＩＥ法と緩衝フッ酸による湿式エッチングを組み合わせて行うことにより、ガラス基板４０の表面上に、溝部４４を形成する。この溝部４４は、図８（ａ）に示すように、ガラス基板４０の長手方向に対して直交する幅方向の寸法が一定になっている第一主領域４４ａ及び第二主領域４４ｃの間に、幅方向寸法が狭小になっている連結領域４４ｂを有するようにパターニングされて形成されている。連結領域４４ｂは、幅方向の寸法が５μｍ、長手方向に沿った長手方向寸法が２０μｍとした。このように形成された溝部４４は、側面部と底面部とが滑らかに連続する湾曲形状に形成され、側面部と底面部との境界部分でエッジ形状が生じない形状になっている。本実施の形態４では、さらに、連結領域４４ｂから第二主領域４４ｃにかけて、連結領域４４ｂの幅寸法が、滑らかな湾曲形状を形成しながら徐々に幅方向寸法が大きくなっていき、連結領域４４ｂと第二主領域４４ｃとの間でエッジ形状が生じないように滑らかに連続するようにパターニングされている。
【０１０８】
次に、実施の形態１と同様にして、非晶質シリコン膜４１を５０ｎｍの膜厚に均一に形成する。
【０１０９】
次に、ガラス基板４０に形成された非晶質シリコン膜４１に対して、ＣＦ₄ガスとＯ₂ガスとを用いたＲＩＥ法によってエッチングし、図８（ｂ）に示すように、溝部４４に埋め込まれた状態になっている非晶質シリコン膜４１以外の部分の非晶質シリコン膜を除去する。
【０１１０】
次に、ＳｉＨ₄ガスとＯ₂ガスとを用いた常圧ＣＶＤ法によって、非晶質シリコン膜４１が、ガラス基板４０の表面上に形成された溝部４４に埋め込まれているガラス基板４０の全面にわたって、ＳｉＯ₂膜４２を１００ｎｍの膜厚に形成する。続いて、ＲＩＥ法によって、非晶質シリコン膜４１の第一主領域４１ａに該当する位置のＳｉＯ₂膜４２を、図８（ｃ）に示すように、矩形状にエッチングして除去し、触媒物質が導入される触媒物質導入領域４３とする。
【０１１１】
次に、スパッタリング法を用いて、全面にわたってニッケル（Ｎｉ）を蒸着する。本実施の形態４では、ニッケルの表面原子濃度は、１×１０¹³〜５×１０¹³個／ｃｍ²とした。
【０１１２】
次に、電気炉を用いて熱処理を実施する。この熱処理の条件は、例えば５５０℃、４時間とする。この熱処理により、最初に触媒物質導入領域４３に結晶核が発生し、この結晶核を種として結晶成長が進行する。
【０１１３】
本実施の形態４では、ガラス基板４０上の溝部４４に埋め込まれた非晶質シリコン膜４１が、３００℃の温度条件で成膜され、膜中に含まれる水素濃度が高くなっているため、ガラス基板４０の垂直方向の結晶方位は、大略（１１１）に揃っている。
【０１１４】
また、この触媒物質導入領域４３に発生した多数の結晶核は、横方向に結晶成長が進行する際に、連結領域４１ｂにて、単一の結晶粒が選択される。
【０１１５】
したがって、第一主領域４１ａの触媒物質導入領域４３にて発生した結晶核が、連結領域４１ｂを経て、第二主領域４１ｃに結晶成長が進行すると、第二主領域４１ｃでは、ガラス基板４０の垂直方向の結晶方位が、大略（１１１）に揃っており、且つ、ガラス基板４０の横方向の結晶方位も大略揃った結晶性のシリコン膜に結晶化される。
【０１１６】
さらに、本実施の形態４では、非晶質シリコン膜４１が、ガラス基板４０上に形成された溝部４４に埋め込まれるように形成されており、第一主領域４１ａ及び連結領域４１ｂ及び第二主領域４１ｃの各領域にわたって、その側面部と底面部とが滑らかに連続する湾曲形状に形成されているので、非晶質シリコン膜４１の側面及び底面との連続部でエッジ形状が形成されない。また、連結領域４１ｂから第二主領域４１ｃにかけて、連結領域４１ｂの幅寸法が、滑らかな湾曲形状を形成しながら徐々に幅方向寸法が大きくなっていき、連結領域４１ｂと第二主領域４１ｃとの間でエッジ形状が生じないように、滑らかに連続している。
【０１１７】
したがって、本実施の形態４では、エッジ形状が形成された部分で不規則な結晶核、具体的には、（１１２）面、（１１４）面、（１２３）面、（３３４）面、（３４５）面等の各種面方位を持った結晶核が発生することを抑制することができる。
【０１１８】
次に、ほぼ全面にわたって形成されたＳｉＯ₂膜４２をエッチングにより除去した後、レーザ照射による結晶化を行い、加熱により結晶化されたシリコン膜をさらに完全に結晶化する。
【０１１９】
また、本実施の形態４では、ガラス基板４０の表面上に形成された溝部４４が、連結領域４４ｂから第二主領域４４ｃにかけて、連結領域４４ｂの幅寸法が、滑らかな湾曲形状を形成しながら徐々に幅方向寸法が大きくなっていき、連結領域４４ｂと第二主領域４４ｃとの間でエッジ形状が生じないように滑らかに連続するように形成されているが、このような滑らかな湾曲形状は、図９に示すように、第一主流域４４ａから連結領域４４ｂにかけた部分にも形成してもよい。このようにすれば、さらに、エッジ形状が低減されて、不規則な結晶核の発生を抑制することができる。
（実施の形態５）
図１２は、本実施の形態５の半導体装置の製造方法を示す断面図である。
【０１２０】
本実施の形態５では、上述した実施の形態１〜４のいずれかにおいて説明した結晶性半導体膜によって薄膜トランジスタ等の半導体装置を製造する方法について説明する。本実施の形態５の製造方法により製造された半導体装置は、液晶ドライバー、半導体メモリー、半導体論理回路等に用いることが可能である。
【０１２１】
以下、具体的に図１２を参照しながら説明する。
【０１２２】
まず、ガラス基板５１上に、上述した実施の形態１〜４のいずれかに記載の結晶性半導体膜の形成方法により、結晶性のシリコン膜を５０ｎｍの膜厚に形成し、続けて、この結晶性シリコン膜をＣＦ₄ガスとＯ₂ガスとを用いたＲＩＥ法によって、所定形状にパターニングし、島状の結晶性シリコン膜５２を形成する。その後、この結晶性シリコン膜５２が形成された基板面の全体にわたって、ＴＥＯＳ（テトラエトキシシラン）ガスとＯ₃ガスとを用いたプラズマＣＶＤ法によって、ゲートＳｉＯ₂膜５３を形成する。
【０１２３】
次に、スパッタリング法によって、ゲートＳｉＯ₂膜５３が形成されたガラス基板５１の全面にわたって、ＷＳｉ₂層を成膜した後、ＣＦ₄ガスとＯ₂ガスとを用いたＲＩＥ法によって、結晶性シリコン膜５２上の略中央部分にのみＷＳｉ₂層が残るようなパターニングとなるようなエッチングを行い、ＷＳｉ₂多結晶ゲート電極５４を形成する。
【０１２４】
次に、薄膜トランジスタのソース・ドレイン領域を形成するために結晶性シリコン膜５２上に不純物を導入する。本実施の形態５の場合、上記のＷＳｉ₂多結晶ゲート電極５４が不純物を導入する際のマスクとなっており、ＷＳｉ₂多結晶ゲート電極５４が設けられた部分以外の結晶性シリコン膜５２に不純物が導入される。ｎ型のトランジスタを形成する場合には、導入される不純物は、リン（Ｐ）であり、ｐ型のトランジスタを形成する場合には、導入される不純物はホウ素（Ｂ）となる。
【０１２５】
次に、ＴＥＯＳガスとＯ₃ガスとを用いたプラズマＣＶＤ法によって、ガラス基板５１の全面にわたって、ＳｉＯ₂膜５５を形成した後、ＣＦ₄ガスとＣＨＦ₃ガスとを用いたＲＩＥ法によって、ソース・ドレイン領域とされる結晶性シリコン膜５２上にコンタクトホール５６を形成する。
【０１２６】
次に、スパッタリング法を用いて基板面の全面にＡｌを積層した後、ＢＣｌ₃ガスとＣｌ₂ガスとを用いたＲＩＥ法によって、ＳｉＯ₂膜５５に形成されたコンタクトホール５６を介して結晶性のシリコン膜５２に導通するＡｌ配線５７とする。
【０１２７】
次に、ＳｉＨ₄ガスとＮＨ₃ガスまたはＮ₂ガスとを用いたプラズマＣＶＤ法によって、基板面の全体にわたって、ＳｉＮ保護膜５８を形成し、最後にＳｉＮ保護膜５８の一部をＣＦ₄ガスとＣＨＦ₃ガスとを用いたエッチングによって、Ａｌ配線５７の一方側の部分に導通可能なようにスルーホール５９を形成して、半導体トランジスタ、抵抗、キャパシタ等の半導体装置が完成される。
（実施の形態６）
図１３は、本実施の形態６の半導体装置を用いたディスプレイ装置の製造方法を示す断面図である。
【０１２８】
本実施の形態６では、上記の実施の形態５と同様の方法で作製した半導体装置を用いて液晶ディスプレイ装置等のディスプレイ装置を製造する方法を説明する。
【０１２９】
以下、本実施の形態６について、図１３（ａ）及び（ｂ）を参照して説明する。
【０１３０】
まず、上記の実施の形態５の製造方法によりガラス基板等の絶縁基板５１上に半導体装置を製造する。なお、この絶縁基板５１上に形成される半導体装置の各構成については、実施の形態５と同一の符号を付し、詳しい説明は省略する。
【０１３１】
次に、ＳｉＮ保護膜５８が形成された基板面の全体にわたってＩＴＯ膜を形成し、続けてＨＣｌとＦｅＣｌ₃ガスとを用いてエッチングを行いパターニングして、ＳｉＮ保護膜５８に形成されたスルーホール５９を介して半導体装置のＡｌ配線５７に導通する画素電極６０を形成する。
【０１３２】
次に、ＳｉＨ₄ガスとＮＨ₃ガスまたはＮ₂ガスとを用いたプラズマＣＶＤ法によって、基板面の全面にわたってＳｉＮ膜６１を形成する。さらに、このＳｉＮ膜６１上に、配向膜となるポリイミド膜６２をオフセット印刷法を用いて形成し、ラビング処理を行う。
【０１３３】
一方、図１３（ｂ）に示すように、別のガラス基板７１上に、Ｒ（赤）、Ｇ（緑）、Ｂ（青）の各感光性樹脂膜を付したフィルムを熱圧着により転写を行った後、フォトリソグラフィ工程によるパターニングを行い、さらに、Ｒ、Ｇ、Ｂの各感光性樹脂が転写された部分間に、遮光性を有するブラックマトリクス部を形成して、カラーフィルター７２を作製する。
【０１３４】
このカラーフィルター７２上には、スパッタリング法によってＩＴＯ膜を基板の全面にわたって形成し、対向電極７３とする。さらに、この対向電極７３上に、配向膜であるポリイミド膜７４をオフセット印刷法によって形成して、ラビング処理を行う。
【０１３５】
以上のように形成された図１３（ｂ）に示すカラーフィルター７２等が形成されたガラス基板７１と、図１３（ａ）に示す薄膜トランジスタ等の半導体装置が形成されたガラス基板５１とを、ラビング処理を施した面が互いに対向するように配置して、シール樹脂によって貼り合せる。この際、２枚のガラス基板間のスペースが一定になるように、ガラス基板５１及び７１間に真球状のシリカを散布する。そして、両基板間に表示媒体となる液晶を注入した後、両ガラス基板５１及び７１の両外側にそれぞれ偏光板等を貼り付け、さらに、その周辺にドライバーＩＣ等を実装して液晶ディスプレイが完成される。
【０１３６】
次に、本発明の適用範囲について説明する。
【０１３７】
図９には、ガラス基板４０に形成される溝部４４の形状が示されていると共に、非晶質シリコン膜４１の連結領域４１ｂの長さ方向の寸法Ｌ及び幅方向の寸法Ｗが示されている。
【０１３８】
上記の実施の形態１〜４の半導体膜の形成方法において、非晶質シリコン膜４１の連結領域４１ｂの寸法は、連結領域４１ｂの上面の幅Ｗは、０．２μｍ〜１０μｍの範囲に形成すれば、結晶粒を選択する効果が確実になる。また、連結領域４１ｂの上面の長さＬは、０．５μｍ〜１００μｍの範囲に形成すれば、結晶粒を選択する効果が確実になる。
【０１３９】
連結領域４１の上面の幅方向の寸法Ｗが０．２μｍより小さい場合、または、連結領域４１の上面の長さＬが１００μｍより大きい場合には、触媒物質導入領域４３にて発生した結晶核が、連結領域４１ｂを通過して、連結領域４１ｂに対して結晶成長の前方側の第二主領域４１ｃまで結晶方位を引き継いで成長しなくなる。逆に、連結領域４１ｂの上面の幅方向の寸法が１０μｍより大きい場合、または、連結領域４１ｂの上面の長さが０．５μｍより小さい場合には、触媒物質導入領域４３にて発生した複数の結晶粒が、連結領域４１ｂにて単一の結晶粒に選択されず、複数の結晶粒が連結領域４１ｂを通過して、連結領域４１ｂに対して結晶成長の前方側にある第二主領域４１ｃに複数の結晶粒が成長し、結晶方位が揃った大きな結晶粒からなる結晶性半導体膜を形成することができなくなる。
【０１４０】
上記の実施の形態１〜４の半導体膜の形成方法では、３００℃の成膜温度として、プラズマＣＶＤ法により、非晶質シリコン膜４１を成膜し、膜中の水素濃度を１０〜２０ａｔ％としたが、この非晶質シリコン膜４１は、イオン注入法により形成してもよい。また、膜中の水素濃度が１０〜２０ａｔ％とするために、成膜温度は、２５０〜３５０℃の範囲に設定することが好適である。
【０１４１】
また、上記の実施の形態１〜４の結晶性半導体膜の形成方法では、製造される半導体膜の具体例として、シリコン膜を形成する方法を示しているが、本発明の結晶性半導体膜の形成方法は、シリコン膜に限られず、ＳｉＧｅ膜等を成膜する場合にも適用することができる。
【０１４２】
また、上記実施の形態１〜４では、半導体膜を形成する基板として、ガラス基板を用いているが、石英基板、ＳｉウエハにＳｉＯ₂膜、ＳｉＮ膜を形成したものを用いてもよい。
【０１４３】
また、上記実施の形態１〜４では、触媒物質導入領域４３に導入されるニッケルの表面濃度は、１×１０¹³〜５×１０¹³個／ｃｍ²としたが、この濃度は、１×１０¹¹〜１×１０¹⁶個／ｃｍ²の範囲であればよい。また、ニッケルは、スパッタリング法を用いた蒸着により触媒物質導入領域４３に導入されているが、真空蒸着法等の他の蒸着法によって導入してもよく、また、蒸着法以外に、ニッケルを含む溶液を塗布する方法、イオン注入法、ＣＶＤ法等の他の方法を用いてもよい。
【０１４４】
また、上記実施の形態１〜４では、結晶化を促進する触媒物質として、ニッケルを用いたが、Ｆｅ、Ｃｏ、Ｃｕ、Ｇｅ、Ｐｄ、Ａｕ等の金属、または、これらの金属を含む化合物、さらには、これらの金属及び金属を含む化合物を組み合わせたものを用いることができる。
【０１４５】
【発明の効果】
本発明の半導体膜の形成方法は、基板上に形成された半導体膜に、該半導体膜を溶融するエネルギーを与え、溶融後の結晶化により結晶成長させて結晶性半導体膜とする半導体膜の形成方法であって、該基板上に、膜中の水素濃度が１０〜２０ａｔ％である半導体膜を形成する工程と、半導体膜の結晶化を助長する触媒物質を導入する工程と、該触媒物質が導入された半導体膜にエネルギーを与える工程と、を包含することを特徴としている。
【０１４６】
このように、膜中の水素濃度が１０〜２０ａｔ％である半導体膜に触媒物質を導入した後、エネルギーを与えることにより結晶成長させると、（１１１）近傍に配向比率が高い結晶性半導体膜を得ることができる。
【図面の簡単な説明】
【図１】（ａ）及び（ｂ）は、それぞれ、実施の形態１の結晶性半導体膜の形成方法を工程毎に説明する斜視図である。
【図２】触媒物質導入領域の端部から連結領域までの間隔ａを説明する平面図である。
【図３】（ａ）及び（ｂ）は、それぞれ、実施の形態２の結晶性半導体膜の形成方法を説明する斜視図である。
【図４】連結領域から第二領域が滑らかに連続するようにパターニングされた非晶質シリコン膜を示す平面図である。
【図５】連結領域と第二主領域とが、滑らかに連続せず、エッジ形状を有するようにパターニングされた非晶質シリコン膜を示す平面図である。
【図６】（ａ）〜（ｃ）は、それぞれ、実施の形態３の結晶性半導体膜の形成方法を説明する斜視図である。
【図７】溝部が形成されたガラス基板の長手方向に直交する方向の断面図を示している。
【図８】（ａ）〜（ｃ）は、それぞれ、実施の形態４の結晶性半導体膜の形成方法を説明する斜視図である。
【図９】実施の形態４の結晶性半導体膜の形成方法において、基板に形成される溝部の他の例を示す斜視図である。
【図１０】試料として作製される非晶質シリコン膜を説明しており、（ａ）は、その断面図、（ｂ）は、その平面図、（ｃ）は、連結部を形成した場合の平面図をそれぞれ示している。
【図１１】表１に示される結晶方位分布を示すグラフである。
【図１２】実施の形態５の半導体装置の製造方法を示す断面図である。
【図１３】（ａ）及び（ｂ）は、それぞれ、実施の形態６の半導体装置を用いたディスプレイ装置の製造方法を示す断面図である。
【図１４】従来例１の半導体膜の形成方法を説明する平面図である。
【図１５】従来例２の半導体膜の形成方法を説明する斜視図である。
【図１６】従来例３の半導体膜の形成方法を説明する平面図である。
【図１７】従来例４の半導体膜の形成方法を説明する断面図である。
【図１８】（ａ）及び（ｂ）は、それぞれ、従来例５の半導体膜の形成方法を説明する断面図である。
【符号の説明】
４０ガラス基板
４１ 非晶質シリコン膜
４２ ＳｉＯ₂膜
４３ 触媒物質導入領域
４４ 溝部
５１ ガラス基板
５２ 結晶性シリコン膜
５３ ゲートＳｉＯ₂膜
５４ ＷＳｉ₂多結晶ゲート電極
５５ ＳｉＯ₂膜
５６ コンタクトホール
５７ Ａｌ配線
５８ ＳｉＮ保護膜
５９ スルーホール
６０ 画素電極
６１ ＳｉＮ膜
６２ ポリイミド膜
７１ ガラス基板
７２ カラーフィルター
７３ 対向電極
７４ ポリイミド膜
１０１ 結晶粒
１０２ 結晶粒
１０３ 結晶粒界[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for forming a semiconductor film and a semiconductor device and a display device manufactured by using the method, and particularly relates to an amorphous or multi-layer formed on a non-single crystal insulating film or a non-single crystal insulating substrate. A method of forming a semiconductor film capable of obtaining a crystalline semiconductor film having almost uniform crystal orientation by applying energy to a semiconductor film such as a crystal, and a semiconductor film formed using the method, and Relates to a semiconductor device such as a liquid crystal driver, a semiconductor memory, and a semiconductor logic circuit using the semiconductor film, and a display device using these semiconductor devices.
[0002]
[Prior art]
Conventionally, an amorphous or polycrystalline semiconductor film is formed on a non-single-crystal insulating film or a non-single-crystal insulating substrate formed on a substrate, and energy is applied to the semiconductor film to thereby form the semiconductor film. There is known a method for crystallizing. When a crystalline semiconductor film with a uniform crystal orientation is formed by this method, the generation of irregular crystal nuclei in an amorphous semiconductor film is suppressed, and the crystal nuclei with controlled crystal orientation are used as seeds. It is important to grow crystals as crystals.
[0003]
In Japanese Patent Laid-Open No. 58-85519 (hereinafter referred to as Conventional Example 1), as shown in FIG. 14, a Si film 2 is patterned into a predetermined shape on a rectangular insulating substrate 1 to obtain thermal energy. Is disclosed. In Conventional Example 1, the Si film 2 is provided over the entire surface of the insulating substrate 1 except for one side edge. The Si film 2 has a main region 2a provided at a portion other than the side edge portion of the insulating substrate 1, and a narrow region 2b provided at the center portion of the side edge portion of the insulating substrate 1, In the region 2a, the width dimension of the side edge continuous to the narrow region 2b becomes smaller as the narrow region 2b approaches. In the conventional method 1, the crystal nucleus formed in the narrow region 2b of the Si film 2 becomes a seed crystal, the crystal region extends from the seed crystal to the main region 2a, and the entire Si film 2 is monocrystallized. Is done. In this case, as a seed crystal formed in the narrow region 2b, a case where a crystal nucleus naturally generated in the narrow region 2b is used and a case where a single crystal piece of Si is arranged on the narrow region 2b are proposed.
[0004]
In U.S. Pat. No. 4,576,676 (hereinafter referred to as Conventional Example 2), a laser is applied to a thinned region of a polycrystalline silicon film 11 formed on a substrate 10 as shown in FIG. By forming a constricted portion 12 having a small length in a direction perpendicular to the scanning direction of the heating means, etc., and heating the thinned polycrystalline silicon film 11 in a certain direction to melt it. A method of crystallization has been proposed. In Conventional Example 2, a crystal orientation filter 13 for selecting a crystal orientation is installed in a region on the rear side with respect to the crystallization direction by melting, and in the middle of the scanning direction of melt crystallization, Only a single crystal grain is selected by passing through the constricted portion 12 formed with a small length in the orthogonal direction.
[0005]
Appl. Phys. Lett. Vol. 41, no. 8, pp 747-749 (hereinafter referred to as Conventional Example 3), as shown in FIG.₂The direction perpendicular to the direction 22 in which the melt solidification is performed by laser light irradiation or the like is narrowed in part with respect to the thin-film polycrystalline silicon film 21 formed on the Si substrate on which the film is deposited. A method has been proposed in which the narrow region 23 is formed by etching, and the thinned polycrystalline Si film 21 is melted by heating in a certain direction. In FIG. 16, reference numeral 24 denotes a region where the polycrystalline silicon film has been removed by etching. Also in the method of Conventional Example 3, the crystal orientation is selected in the narrow region 23 by passing through the narrow region 23 during the crystallization process after melting.
[0006]
Further, in Japanese Patent Laid-Open No. 7-231100, a nickel layer containing nickel is formed on the surface of an amorphous silicon film 32 formed on a glass substrate 31 as shown in FIG. There has been proposed a crystallization method in which crystallization is advanced using a crystallization promoting action (hereinafter referred to as Conventional Example 4). In the method of Conventional Example 4, a silicon oxide film 33 having a thickness of about 100 mm is formed on the surface of the amorphous silicon film 32 in order to improve wettability. A solution film 34 containing nickel which is a catalyst material for promoting the coating is applied and spin-dried to form a nickel layer containing nickel on the surface of the amorphous silicon film 32. Subsequently, the amorphous silicon film 32 is crystallized by annealing at 450 ° C. to 650 ° C., for example, 550 ° C. In this method, it is described that crystallization is further promoted by annealing at a temperature higher than the crystallization temperature, for example, 1000 ° C. By using this method, a crystal having a large grain size is described. Can be obtained.
[0007]
In the conventional example 4, nickel is introduced over the entire surface of the amorphous silicon film 32 to promote crystallization. However, the above Japanese Patent Laid-Open No. 7-231100 discloses FIG. 18 (a). Thus, using the silicon oxide film 35 formed on the amorphous silicon film 32 as a mask layer into which no catalyst material is introduced, a catalyst material introduction region 36 into which nickel as the catalyst material is selectively introduced is formed, A crystallization method has been proposed in which crystallization proceeds from the catalyst substance introduction region 36 (hereinafter referred to as Conventional Example 5). In the method of Conventional Example 5, a mask silicon oxide film 35 having a thickness of 1200 mm is formed on an amorphous silicon film 32 formed on a glass substrate 31, and then etched into a necessary pattern. In order to improve wettability, a silicon oxide film 33 having a thickness of about 100 mm is formed on the surface of the etched amorphous silicon film 32, and a catalytic substance that promotes crystallization is formed on the silicon oxide film 33. A solution film 34 containing nickel is applied and spin-dried using a spinner 37 placed below the glass substrate 31 to form a layer containing nickel in the catalytic material introduction region 36 of the amorphous silicon film 32. To do. Subsequently, the amorphous silicon film 32 is crystallized by annealing at 450 ° C. to 650 ° C., for example, 550 ° C. During this annealing, crystal growth in the amorphous silicon film 32 is caused by nickel from the region 32a of the amorphous silicon film 32 in the catalyst material introduction region 36 into which nickel is introduced, as shown in FIG. Proceed in the horizontal direction to the region 32b where no is introduced. When the crystal growth is completed, the silicon oxide film 35 is removed, and annealing at a temperature higher than the crystallization temperature, for example, 1000 ° C., is further promoted. A crystalline silicon film having a large grain size can also be obtained by the method of Conventional Example 5.
[0008]
[Problems to be solved by the invention]
However, in the crystallization method of Conventional Example 1 described above, when a crystal is grown using a crystal nucleus that is naturally generated in the narrow region 2b, it is based on crystal grains having one crystal orientation generated in the narrow region 2b. The crystal growth in the main region 2a proceeds, but the orientation of crystal nuclei generated in the narrow region 2b is irregular, and crystal nuclei with an orientation that facilitates crystal growth are not necessarily generated. Therefore, when crystal nuclei that are difficult to grow in the narrow region 2b are generated, crystal nuclei having other orientations may be generated in the main region 2a to become polycrystalline. Further, when a plurality of patterns of the Si film 2 having the shape shown in FIG. 14 are formed, the crystal orientations of crystal nuclei generated in each of the plurality of narrow regions 2b do not coincide with each other and are generated in the respective narrow regions 2b. The crystal orientation of the main region 2a where the crystal has grown does not match.
[0009]
On the other hand, when a single crystal piece of Si is arranged on the narrow region 2b and a crystal is grown based on this single crystal piece, it is pasted to paste a crystal piece as a seed crystal on the narrow region 2b. There is a problem that the bonding interface between the crystal piece and the Si film 2 in the narrow region 2b needs to be clean at the atomic level, and it is very difficult to form and maintain this clean interface. .
[0010]
In the conventional examples 2 and 3, the substrate temperature is excessively excessive when passing through the narrow regions 12 and 23 having small dimensions in the direction orthogonal to the scanning direction when the crystallization after melting is advanced. To rise. For this reason, an inexpensive substrate such as a glass substrate cannot be used.
[0011]
Furthermore, in the above-described conventional examples 1 to 3, when a corner portion that is not continuous is formed at the side portion of the edge portion of the patterned silicon film and the intersection portion at the bottom surface, the portion has an irregular crystal orientation. There is also a problem that crystal nuclei are easily generated.
[0012]
Further, in the above-described conventional example 4, the crystal nuclei for crystal growth occur irregularly over the entire surface of the amorphous silicon film 32, so that only crystal grains on the order of μm are obtained and the crystal orientation is aligned. It is difficult to obtain large crystal grains or single crystal regions.
[0013]
Further, in the method of Conventional Example 5, crystal nuclei are irregularly generated in the catalytic material introduction region 36 into which nickel has been introduced, and based on the crystal nuclei, crystals are transverse to the surface of the glass substrate 31. In order to advance the growth, longer crystal grains or single crystal regions can be obtained as compared with the method of Conventional Example 4. However, even in this case, crystal grains having dimensions in the width direction with respect to the crystal growth direction on the order of μm are obtained, and it is difficult to obtain larger crystal grains or single crystal regions.
[0014]
Furthermore, the semiconductor film crystallized by the methods of Conventional Examples 4 and 5 has a problem that many crystal defects are generated.
[0015]
When a semiconductor device (transistor) such as a liquid crystal driver, a semiconductor memory, or a semiconductor logic circuit is manufactured using a semiconductor film that does not have the same crystal orientation and has many crystal defects, the carrier mobility is low. Further, there is a problem that the threshold voltage is large, and further, there is a problem that variations in carrier mobility and threshold voltage of each semiconductor device (transistor) formed in a large number of liquid crystal tribars and the like become large.
[0016]
The present invention has been made to solve the above problems, and provides a method for forming a crystalline semiconductor film having large crystal grains with few crystal defects and substantially uniform crystal orientation, and a method for forming the same. An object of the present invention is to provide a semiconductor device and a display device manufactured using the same.
[0017]
[Means for Solving the Problems]
  In order to solve the above problems, a method for forming a crystalline silicon film of the present invention includes:A method for forming a crystalline silicon film by applying energy to an amorphous silicon film formed on a substrate to cause crystal growth to form a crystalline silicon film, wherein the amorphous silicon film is formed on the substrate by 250 to 350. Forming an amorphous silicon film having a hydrogen concentration in the film of 10 to 20 at%, and then forming the amorphous silicon film in a straight line along a predetermined direction. The first main region and the second main region that are spaced apart from each other, and the first main region and the second main region are provided so as to connect both, and the width direction And a catalyst for promoting crystallization of the amorphous silicon film in the first main region, and a step of patterning so as to have a connecting region that is smaller than the first and second main regions. Forming a catalytic material introduction region into which a material is selectively introduced A step of introducing nickel as the catalyst material into the catalyst material introduction region, and applying energy to the amorphous silicon film into which the nickel has been introduced, thereby causing the amorphous silicon film to be perpendicular to the substrate. And crystalline silicon having substantially the same crystal orientation (111) and the horizontal crystal orientation of the substrate being substantially uniform.
[0018]
  In the patterning step, the amorphous silicon film is preferably patterned so that the connection region and the second main region are smoothly continuous..
[0019]
  Before forming the amorphous silicon film on the substrate, a groove portion having a smoothly continuous side surface and bottom surface is formed on the substrate corresponding to the shape of the amorphous silicon film patterned in the patterning step. In the patterning step, it is preferable that the amorphous silicon film on the substrate other than the amorphous silicon film buried in the groove is removed..
[0020]
  The groove is preferably formed so that the connection region and the second main region of the amorphous silicon film patterned in the patterning step are smoothly continuous..
[0021]
  It is preferable that the dimension in the width direction of the connection region is formed in a range of 0.2 μm to 10 μm..
[0022]
  It is preferable that the length in the length direction of the connection region is formed in a range of 0.5 μm to 100 μm..
[0023]
  A semiconductor device according to the present invention includes the crystalline silicon film..
[0024]
  A display device according to the present invention includes the semiconductor device..
[0034]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described in detail.
[0035]
The present invention has been made paying attention to the fact that there is a correlation between the hydrogen concentration in the amorphous silicon film and the crystal orientation after crystallization.
[0036]
That is, the inventors of the present invention formed a plurality of types of amorphous silicon films having different hydrogen concentrations in the film as samples, applied energy to each sample, crystallized, and obtained crystalline silicon films The types of included crystal orientations and the occupied area ratio of each included crystal orientation were examined. Based on the experimental results, the inventors of the present application have realized a crystalline silicon film forming method for obtaining a crystalline silicon film in which the crystal orientations in the vertical direction of the substrate are substantially uniform.
[0037]
First, the experimental results of examining the correlation between the hydrogen concentration in the amorphous silicon film and the crystal orientation after crystallization will be described in detail.
[0038]
10A and 10B illustrate the amorphous silicon film 41 manufactured as each sample. FIG. 10A shows a cross-sectional view thereof, and FIG. 10B shows a plan view thereof.
[0039]
As Sample 1, an amorphous silicon film having a high concentration of hydrogen contained in the film was formed. In order to manufacture this sample 1, first, SiH on a glass substrate 40 at a film forming temperature of 250 ° C._FourAn amorphous silicon film 41 was formed to a thickness of 50 nm by plasma CVD (Chemical Vapor Deposition) using a gas. The hydrogen concentration in the amorphous silicon film 41 thus formed was 19% as a result of FTIR (Fourier Transform Infrared Spectrometer) measurement.
[0040]
Next, SiO 2 is formed on the amorphous silicon film 41 formed as described above.₂After the film 42 is formed to a thickness of 100 nm, the SiO 2 film is formed using the RIE (Reactive Ion Etching) method.₂A part of the film 42 is removed by etching to form a catalyst material introduction region 43. As shown in FIG. 10B, the catalyst material introduction region 43 was formed in a linear shape having a width direction dimension of 10 μm.
[0041]
Next, a nickel thin film is formed in the catalyst material introduction region 43 by sputtering. The nickel surface atomic concentration of this nickel thin film is 1 × 10¹³~ 5x10¹³Piece / cm²It was.
[0042]
Next, heat treatment at 550 ° C. was performed for 4 hours using an electric furnace. By this heat treatment, nickel introduced into the catalyst material introduction region 43 is combined with silicon in the amorphous silicon film 41 to form nickel silicide, and the nickel silicide serves as a crystal nucleus to form the amorphous silicon film 41. Crystallization is promoted. Nickel silicide moves in the lateral direction while crystallizing amorphous silicon, and a crystalline silicon film is formed on the rear side in the movement direction.
[0043]
Next, an amorphous silicon film in which the concentration of hydrogen contained in the film was lower than that of Sample 1 was formed as Sample 2.
[0044]
This sample 2 is formed on a glass substrate 40 at a film forming temperature of 350 ° C. with SiH._FourAn amorphous silicon film 41 was formed to a thickness of 50 nm by plasma CVD (Chemical Vapor Deposition) using a gas. Other steps were prepared in the same procedure as Sample 1 above.
[0045]
Next, an amorphous silicon film in which the concentration of hydrogen contained in the film was further reduced as compared with Sample 2 was formed as Sample 3.
[0046]
This sample 3 is formed on a glass substrate 40 at a film formation temperature of 450 ° C. and SiH._FourAn amorphous silicon film 41 was formed to a thickness of 50 nm by plasma CVD (Chemical Vapor Deposition) using a gas. Other steps were prepared in the same procedure as Sample 1 above.
[0047]
Next, the crystal orientations of the crystalline silicon films of Samples 1 to 3 manufactured as described above were measured using an EBSP (Electron Backscatter Diffraction Pattern) method. This EBSP method is a crystal orientation measurement method in which a sample is irradiated with an electron beam and the crystal orientation is determined by a chrysanthemum map that appears by the electron beam scattered by the sample.
[0048]
Table 1 below shows the crystal orientation plane distribution of Samples 1 to 3 measured using this EBSP method. In this table, the occupied area ratios in the vicinity of the (111) and (110) orientations in the vertical direction of the glass substrate 40 are respectively displayed. Further, in FIG. 11, the crystal orientation distribution shown in Table 1 is shown by a graph.
[0049]
[Table 1]

[0050]
Referring to Table 1 and the graph of FIG. 11 respectively, the preferentially oriented crystal orientation in Sample 1 is (111), and its occupation area is 68%.
[0051]
In sample 2 in which the hydrogen concentration in the film is reduced from that of sample 1, the preferentially oriented crystal orientation is (111) as in sample 1, but its occupied area is 54%, which is lower than the occupied area of sample 1. ing.
[0052]
In the sample 3 in which the hydrogen concentration in the film is lower than that in the sample 2, the preferentially oriented crystal orientation is not (111) but (110), and the occupied area is 47%.
[0053]
As is clear with reference to FIG. 11, the hydrogen concentration in the film is reduced, the crystal orientation of (111) is reduced, and the crystal orientation of (110) is increased. The cause is considered as follows.
[0054]
Nickel silicide formed by combining nickel introduced into the catalyst substance introduction region 43 with silicon in the amorphous silicon film 41 moves in the lateral direction while crystallizing the amorphous silicon film 41 and moves. A crystalline silicon film is formed on the rear side in the direction. The crystal orientation of the crystalline silicon film 41 formed in this way is (110) in the vertical direction of the substrate, according to J. Hayzelden et al. Appl. Phys. Vol. 73, no. 12, 1993.
[0055]
On the other hand, on the glass substrate 40, at a film forming temperature of 350 ° C., SiH_FourWhen an amorphous silicon film 41 formed to a thickness of 50 nm by performing a plasma CVD method using a gas is heated at a temperature of 570 ° C. for 20 hours, natural nuclei are formed in the amorphous silicon film 41. And the crystallization proceeds based on the natural nucleus. When the crystal orientation of the crystallized sample was measured by the X-ray analysis measurement method, only the diffraction peak based on the crystal orientation of (111) was observed. This result shows that the natural nucleus and the crystal grown based on the natural nucleus are preferentially oriented in the crystal orientation of the (111) plane.
[0056]
In the above samples 1 and 2, since the hydrogen concentration contained in the amorphous silicon film 41 is high, natural nuclei are likely to be generated due to the distortion of dangling bonds after the hydrogen escapes by heat treatment. It is considered that the crystal orientation of the formed crystalline silicon is preferentially oriented to (111) by this natural nucleus. In this case, the nickel silicide in the samples 1 and 2 is considered to have an effect of only increasing the crystallization speed.
[0057]
On the other hand, in sample 3, since the concentration of hydrogen contained in the amorphous silicon film 41 is low, the generation of natural nuclei is small, and crystallization with nickel silicide as crystal nuclei becomes dominant. It is thought that there is. As a result, it is considered that the crystal orientation of the formed crystalline silicon is preferentially oriented to (110) due to the influence of nickel silicide.
[0058]
As described above, in Sample 1, the crystalline silicon film to be formed has a high (111) plane occupation area, and the crystal orientation in the substrate vertical direction can be approximately aligned with (111).
[0059]
However, even when the concentration of hydrogen contained in the film is increased and the crystal orientation in the vertical direction of the substrate is substantially aligned with the (111) plane, the lateral direction of the substrate (X and Y directions in FIG. 10). The crystal orientation is not aligned.
[0060]
For this reason, when aligning the crystal orientation in the vertical direction of the substrate and aligning the crystal orientation in the lateral direction of the substrate, as shown in FIG. 10C, the dimension in the direction orthogonal to the crystal growth direction is used. The amorphous silicon film is patterned so as to have a constricted connecting portion so that the width is narrow. In this way, a single crystal grain is selected at the connecting portion among a plurality of crystal grains having respective crystal orientations for crystal growth, and selected at the front portion of the connecting portion with respect to the crystal growth direction. A single crystal region having no crystal grain boundary can be formed by growing the single crystal grain.
[0061]
In this case, since crystal growth is promoted by the catalyst material, it is not necessary to perform high-temperature heat treatment that causes an excessive temperature rise in the connecting portion, so even if a glass substrate that is not excellent in heat resistance is used, Crystallization can be performed.
[0062]
In this way, it is possible to form a crystalline silicon film in which the crystal orientation in the vertical direction of the substrate is substantially aligned with (111) and the crystal orientation in the lateral direction of the substrate is also approximately aligned.
[0063]
Hereinafter, specific modes of the method for forming a crystalline semiconductor film of the present invention will be described with reference to the drawings.
[0064]
(Embodiment 1)
FIGS. 1A and 1B are perspective views illustrating the method for forming a crystalline semiconductor film according to the first embodiment for each step.
[0065]
First, an amorphous silicon film 41 is uniformly formed to a thickness of 50 nm over the entire surface of the glass substrate 40 by plasma CVD. As a material gas used for film formation, SiH_FourThe substrate temperature is 300 ° C.
[0066]
Next, for the amorphous silicon film 41 formed on the glass substrate 40, CF_FourGas and O₂Etching is performed by a reactive ion etching (RIE) method using a gas, and the dimension in the width direction perpendicular to the longitudinal direction of the glass substrate 40 is constant as shown in FIG. Patterning is performed so as to have a connecting region 41b having a narrow dimension in the width direction between the first main region 41a and the second main region 41c. The connecting region 41b has a width dimension of 5 μm and a longitudinal dimension along the longitudinal direction of 20 μm.
[0067]
Next, SiH_FourGas and O₂SiO 2 over the entire surface of the glass substrate 40 on which the amorphous silicon film 41 is formed by atmospheric pressure CVD using a gas.₂The film 42 is formed to a thickness of 100 nm. Subsequently, SiO is performed by RIE.₂In the film 42, the corresponding position on the first main region 41a of the amorphous silicon film 41 is removed by etching into a rectangular shape as shown in FIG. Let it be an introduction area 43.
[0068]
Next, nickel (Ni) is deposited over the entire surface by sputtering. In the first embodiment, the surface atomic concentration of nickel is 1 × 10¹³~ 5x10¹³Piece / cm²It was.
[0069]
Next, heat treatment is performed using an electric furnace. The conditions for this heat treatment are, for example, 550 ° C. and 4 hours. By this heat treatment, crystal nuclei are first generated in the catalyst substance introduction region 43, and crystal growth proceeds using the crystal nuclei as seeds.
[0070]
In the first embodiment, the amorphous silicon film 41 formed on the glass substrate 40 is formed under a temperature condition of 300 ° C., and the concentration of hydrogen contained in the film is high. The crystal orientations of the directions are approximately (111).
[0071]
A large number of crystal nuclei generated in the catalyst substance introduction region 43 are selected as a single crystal grain in the connection region 41b when crystal growth proceeds in the lateral direction.
[0072]
Therefore, when the crystal nuclei generated in the catalyst material introduction region 43 of the first main region 41a progress through the connection region 41b to the second main region 41c, in the second main region 41c, the glass nuclei 40 It is crystallized into a crystalline silicon film in which the crystal orientation in the vertical direction is substantially aligned (111) and the crystal orientation in the lateral direction of the glass substrate 40 is also approximately aligned.
[0073]
Next, SiO formed over almost the entire surface₂After the film 42 is removed by etching, crystallization by laser irradiation is performed, and the silicon film 41 crystallized by heating is further completely crystallized. The energy of the laser used for this laser irradiation is 350 to 400 mJ / cm.²Is set in the range.
[0074]
When the crystal orientation of the crystalline silicon film 41 formed in this way was measured by the EBSP method, the crystal orientation in the substrate vertical direction of the crystalline silicon film in the second main region 41c was substantially aligned with (111).
[0075]
In order to improve the selectivity of the crystal orientation in the lateral direction of the glass substrate 40 by installing the connection region 41b, a predetermined distance from the end of the catalyst material introduction region 43 to the connection region 41b in the first main region 41a. Is formed. FIG. 2 is a plan view for explaining the distance a. The interval a is set to 0.5 to 50 μm. When the distance a is smaller than 0.5 μm, the crystal orientation selectivity by the connection region 41b is lowered.
[0076]
(Embodiment 2)
FIGS. 3A and 3B are perspective views illustrating a method for forming a crystalline semiconductor film according to the second embodiment.
[0077]
The second embodiment is performed in substantially the same process as the method for forming the crystalline semiconductor film of the first embodiment, but an edge shape is not generated from the connection region 41b to the second main region 41c. The point that the amorphous silicon film 41 is patterned so as to be smoothly continuous is different from the first embodiment.
[0078]
This will be specifically described below.
[0079]
First, in the same manner as in the first embodiment, an amorphous silicon film 41 is uniformly formed to a thickness of 50 nm on the glass substrate 40.
[0080]
Next, for the amorphous silicon film 41 formed on the glass substrate 40, CF_FourGas and O₂Etching is performed by RIE using gas, and as shown in FIG. 3A, the first main region 41a and the first main region 41a having a constant dimension in the width direction perpendicular to the longitudinal direction of the glass substrate 40 Patterning is performed so as to have a connecting region 41b having a narrow dimension in the width direction between the two main regions 41c. The connecting region 41b has a width dimension of 5 μm and a longitudinal dimension along the longitudinal direction of 20 μm. In the second embodiment, the width dimension of the connection region 41b gradually increases from the connection region 41b to the second main region 41c while forming a smooth curved shape. The amorphous silicon film 41 is patterned so that an edge shape does not occur between the first main region 41c and the second main region 41c.
[0081]
FIG. 4 shows a plan view of the amorphous silicon film 41 thus patterned. Such a smooth curved shape formed between the connection region 41b and the second main region 41c is formed, for example, by continuously joining two ¼ curved portions of a substantially circumference. .
[0082]
Next, SiH_FourGas and O₂SiO 2 over the entire surface of the glass substrate on which the amorphous silicon film 41 is formed by atmospheric pressure CVD using a gas.₂The film 42 is formed to a thickness of 100 nm. Subsequently, the SiO layer at the corresponding position on the first main region 41a of the amorphous silicon film 41 is formed by RIE.₂As shown in FIG. 3B, the film 42 is etched into a rectangular shape to form a catalyst material introduction region 43 into which the catalyst material is introduced.
[0083]
Next, nickel (Ni) is deposited over the entire surface by sputtering. In the second embodiment, the surface atomic concentration of nickel is 1 × 10¹³~ 5x10¹³Piece / cm²It was.
[0084]
Next, heat treatment is performed using an electric furnace. The conditions for this heat treatment are 550 ° C. and 4 hours. By this heat treatment, crystal nuclei are first generated in the catalyst substance introduction region 43, and crystal growth proceeds using the crystal nuclei as seeds.
[0085]
In the second embodiment, the amorphous silicon film 41 formed on the glass substrate 40 is formed under a temperature condition of 300 ° C., and the concentration of hydrogen contained in the film is high. The crystal orientations of the directions are approximately (111).
[0086]
A large number of crystal nuclei generated in the catalyst substance introduction region 43 are selected as a single crystal grain in the connection region 41b when crystal growth proceeds in the lateral direction.
[0087]
Accordingly, when crystal growth of the crystal nucleus generated in the catalytic material introduction region 43 of the first main region 41a progresses to the second main region 41c via the connection region 41b, in the second main region 41c, the vertical direction of the substrate Is crystallized into a crystalline silicon film having substantially the same crystal orientation (111) and also having a crystal orientation in the lateral direction of the substrate.
[0088]
Furthermore, in the second embodiment, the width dimension of the connection region 41b gradually increases from the connection region 41b to the second main region 41c while forming a smooth curved shape. And the second main region 41c are smoothly continuous so as not to generate an edge shape, so that it is possible to suppress the generation of irregular crystal nuclei in the portion where the edge shape is formed.
[0089]
FIG. 5 shows a case where the amorphous silicon film 41 is patterned so that the connection region 41b and the second main region 41c are not smoothly continuous and have an edge shape, unlike the second embodiment. FIG. Thus, when an edge shape is generated between the connection region 41b and the second main region 41c, even if the crystal grain 101 having a single crystal orientation is selected in the connection region 41b, Irregular nuclei generated at the edge, specifically, non- (111) plane orientations such as (112) plane, (114) plane, (123) plane, (334) plane, (345) plane, etc. Crystal nuclei are generated, and in the second main region 41c, crystal grains 102 having a non- (111) plane orientation and crystal grains 101 having a (111) plane orientation selected in the coupling region 41b grow. Thus, a crystal grain boundary 103 is generated between the crystal grains. For this reason, as shown in FIG. 5, when the amorphous silicon film 41 is patterned, it becomes impossible to obtain a crystalline silicon film having substantially uniform crystal orientation.
[0090]
Next, SiO formed over almost the entire surface₂After the film 42 is removed by etching, crystallization is performed by laser irradiation, and the silicon film crystallized by heating is further completely crystallized.
(Embodiment 3)
6A to 6C are perspective views illustrating a method for forming a crystalline semiconductor film according to the third embodiment.
[0091]
The third embodiment is performed by substantially the same process as the method for forming the crystalline semiconductor film of the first embodiment described above, but the amorphous silicon film to be crystallized is formed in the groove formed on the substrate. The embodiment is that the first and second main regions and the connection region of the amorphous silicon film are formed in an embedded state, and have side surfaces and bottom surfaces that are smoothly continuous. 1 and different.
[0092]
This will be specifically described below.
[0093]
First, CF_FourThe groove portion 44 is formed on the surface of the glass substrate 40 by performing a combination of RIE using gas and wet etching using buffered hydrofluoric acid. As shown in FIG. 6A, the groove 44 is formed between the first main region 44a and the second main region 44c in which the dimension in the width direction orthogonal to the longitudinal direction of the glass substrate 40 is constant. , And patterned so as to have a connecting region 44b having a narrow dimension in the width direction.
[0094]
FIG. 7 shows a cross-sectional view in a direction perpendicular to the longitudinal direction of the glass substrate 40 in which the groove 44 is formed. The groove portion 44 thus formed is formed in a curved shape in which the side surface portion and the bottom surface portion are smoothly continuous. The curved shape of the groove 44 is formed, for example, so that the side surface of the groove 44 is approximately ¼ of the circumference.
[0095]
Next, in the same manner as in the first embodiment, an amorphous silicon film 41 is uniformly formed to a thickness of 50 nm.
[0096]
Next, for the amorphous silicon film 41 formed on the glass substrate 40, CF_FourGas and O₂Etching is performed by RIE using a gas, and the amorphous silicon film other than the amorphous silicon film 41 embedded in the groove 44 is removed as shown in FIG. 6B. .
[0097]
Next, SiH_FourGas and O₂The amorphous silicon film 41 is formed over the entire surface of the glass substrate 40 embedded in the groove 44 formed on the surface of the glass substrate 40 by an atmospheric pressure CVD method using gas.₂The film 42 is formed to a thickness of 100 nm. Subsequently, the SiO layer at a position corresponding to the first main region 41a of the amorphous silicon film 41 is formed by RIE.₂As shown in FIG. 6C, the film 42 is removed by etching into a rectangular shape to form a catalyst material introduction region 43 into which the catalyst material is introduced.
[0098]
Next, nickel (Ni) is deposited over the entire surface by sputtering. In Embodiment 3, the surface atomic concentration of nickel is 1 × 10¹³~ 5x10¹³Piece / cm²It was.
[0099]
Next, heat treatment is performed using an electric furnace. The conditions for this heat treatment are, for example, 550 ° C. and 4 hours. By this heat treatment, crystal nuclei are first generated in the catalyst substance introduction region 43, and crystal growth proceeds using the crystal nuclei as seeds.
[0100]
In Embodiment 3, since the amorphous silicon film 41 embedded in the groove 44 on the glass substrate 40 is formed at a temperature condition of 300 ° C., the hydrogen concentration contained in the film is high. The vertical crystal orientation of the substrate is approximately (111).
[0101]
A large number of crystal nuclei generated in the catalyst substance introduction region 43 are selected as a single crystal grain in the connection region 41b when crystal growth proceeds in the lateral direction.
[0102]
Therefore, when the crystal nuclei generated in the catalyst material introduction region 43 of the first main region 41a progress through the connection region 41b to the second main region 41c, in the second main region 41c, the glass nuclei 40 It is crystallized into a crystalline silicon film in which the crystal orientation in the vertical direction is substantially aligned (111) and the crystal orientation in the lateral direction of the glass substrate 40 is also approximately aligned.
[0103]
Further, in the third embodiment, the amorphous silicon film 41 is formed so as to be embedded in the groove 44 formed on the glass substrate 40, and the first main region 41a, the connecting region 41b, and the second main region are formed. Since the side surface portion and the bottom surface portion are formed in a curved shape that smoothly continues across each region of the region 41c, the edge shape is not formed at the continuous portion between the side surface and the bottom surface of the amorphous silicon film 41. Therefore, irregular crystal nuclei in the portion where the edge shape is formed, specifically, various surface orientations such as (112) plane, (114) plane, (123) plane, (334) plane, (345) plane, etc. It is possible to suppress the generation of possessed crystal nuclei.
[0104]
Next, SiO formed over almost the entire surface₂After the film 42 is removed by etching, crystallization is performed by laser irradiation, and the silicon film crystallized by heating is further completely crystallized.
(Embodiment 4)
FIGS. 8A to 8C are perspective views illustrating a method for forming a crystalline semiconductor film according to the fourth embodiment.
[0105]
The fourth embodiment is performed by substantially the same process as the method for forming the crystalline semiconductor film of the first embodiment, but the amorphous silicon film to be crystallized is formed in the groove formed on the substrate. Each of the first and second main regions and the connection region of the amorphous silicon film is formed in an embedded state and has a shape in which the side surface and the bottom surface of the amorphous silicon film are smoothly continuous. Moreover, the groove part is formed so that it may continue smoothly from a connection area | region to a 2nd main area | region so that edge shape may not arise. That is, the fourth embodiment has a shape of an amorphous silicon film in which the second embodiment and the third embodiment are combined.
[0106]
This will be specifically described below.
[0107]
First, CF_FourThe groove portion 44 is formed on the surface of the glass substrate 40 by performing a combination of RIE using gas and wet etching using buffered hydrofluoric acid. As shown in FIG. 8A, the groove 44 is formed between the first main region 44a and the second main region 44c in which the dimension in the width direction orthogonal to the longitudinal direction of the glass substrate 40 is constant. , The pattern is formed so as to have a connection region 44b having a narrow dimension in the width direction. The connecting region 44b has a width dimension of 5 μm and a longitudinal dimension along the longitudinal direction of 20 μm. The groove portion 44 formed in this way is formed in a curved shape in which the side surface portion and the bottom surface portion are smoothly continuous, and has a shape in which an edge shape does not occur at the boundary portion between the side surface portion and the bottom surface portion. In the fourth embodiment, the width dimension of the connection area 44b gradually increases from the connection area 44b to the second main area 44c while forming a smooth curved shape. And the second main region 44c are patterned so as to be smoothly continuous so as not to cause an edge shape.
[0108]
Next, in the same manner as in the first embodiment, an amorphous silicon film 41 is uniformly formed to a thickness of 50 nm.
[0109]
Next, for the amorphous silicon film 41 formed on the glass substrate 40, CF_FourGas and O₂Etching is performed by RIE using a gas, and the amorphous silicon film other than the amorphous silicon film 41 embedded in the groove 44 is removed as shown in FIG. .
[0110]
Next, SiH_FourGas and O₂The amorphous silicon film 41 is formed over the entire surface of the glass substrate 40 embedded in the groove 44 formed on the surface of the glass substrate 40 by an atmospheric pressure CVD method using gas.₂The film 42 is formed to a thickness of 100 nm. Subsequently, the SiO layer at a position corresponding to the first main region 41a of the amorphous silicon film 41 is formed by RIE.₂As shown in FIG. 8C, the film 42 is removed by etching into a rectangular shape to form a catalyst material introduction region 43 into which the catalyst material is introduced.
[0111]
Next, nickel (Ni) is deposited over the entire surface by sputtering. In the fourth embodiment, the surface atomic concentration of nickel is 1 × 10¹³~ 5x10¹³Piece / cm²It was.
[0112]
Next, heat treatment is performed using an electric furnace. The conditions for this heat treatment are, for example, 550 ° C. and 4 hours. By this heat treatment, crystal nuclei are first generated in the catalyst substance introduction region 43, and crystal growth proceeds using the crystal nuclei as seeds.
[0113]
In the fourth embodiment, the amorphous silicon film 41 embedded in the groove 44 on the glass substrate 40 is formed under a temperature condition of 300 ° C., and the hydrogen concentration contained in the film is high. The crystal orientation in the vertical direction of the glass substrate 40 is substantially aligned with (111).
[0114]
A large number of crystal nuclei generated in the catalyst substance introduction region 43 are selected as a single crystal grain in the connection region 41b when crystal growth proceeds in the lateral direction.
[0115]
Therefore, when the crystal nuclei generated in the catalyst material introduction region 43 of the first main region 41a progress through the connection region 41b to the second main region 41c, in the second main region 41c, the glass nuclei 40 It is crystallized into a crystalline silicon film in which the crystal orientation in the vertical direction is substantially aligned (111) and the crystal orientation in the lateral direction of the glass substrate 40 is also approximately aligned.
[0116]
Furthermore, in the fourth embodiment, the amorphous silicon film 41 is formed so as to be embedded in the groove 44 formed on the glass substrate 40, and the first main region 41a, the connection region 41b, and the second main region are formed. Since the side surface portion and the bottom surface portion are formed in a curved shape that is smoothly continuous over each region of the region 41c, the edge shape is not formed at the continuous portion between the side surface and the bottom surface of the amorphous silicon film 41. In addition, the width dimension of the connection region 41b gradually increases from the connection region 41b to the second main region 41c while forming a smooth curved shape, and the connection region 41b and the second main region 41c It is smoothly continuous so that no edge shape occurs between the two.
[0117]
Therefore, in the fourth embodiment, irregular crystal nuclei, specifically, (112) plane, (114) plane, (123) plane, (334) plane, (345) are formed in the portion where the edge shape is formed. ) Generation of crystal nuclei having various plane orientations such as planes can be suppressed.
[0118]
Next, SiO formed over almost the entire surface₂After the film 42 is removed by etching, crystallization is performed by laser irradiation, and the silicon film crystallized by heating is further completely crystallized.
[0119]
In the fourth embodiment, the groove portion 44 formed on the surface of the glass substrate 40 extends from the connection region 44b to the second main region 44c while the width dimension of the connection region 44b forms a smooth curved shape. The dimension in the width direction gradually increases, and is formed so as to be smoothly continuous so as not to cause an edge shape between the connection region 44b and the second main region 44c. As shown in FIG. 9, it may be formed in a portion extending from the first main flow area 44a to the connection area 44b. In this way, the edge shape is further reduced, and the generation of irregular crystal nuclei can be suppressed.
(Embodiment 5)
FIG. 12 is a cross-sectional view showing the method for manufacturing the semiconductor device of the fifth embodiment.
[0120]
In the fifth embodiment, a method for manufacturing a semiconductor device such as a thin film transistor using the crystalline semiconductor film described in any of the first to fourth embodiments will be described. The semiconductor device manufactured by the manufacturing method of the fifth embodiment can be used for a liquid crystal driver, a semiconductor memory, a semiconductor logic circuit, and the like.
[0121]
Hereinafter, a specific description will be given with reference to FIG.
[0122]
First, a crystalline silicon film is formed to a thickness of 50 nm on the glass substrate 51 by the method for forming a crystalline semiconductor film according to any of the first to fourth embodiments described above. CF film with CF_FourGas and O₂An island-like crystalline silicon film 52 is formed by patterning into a predetermined shape by an RIE method using gas. Thereafter, TEOS (tetraethoxysilane) gas and O 2 are formed over the entire substrate surface on which the crystalline silicon film 52 is formed._ThreeThe gate SiO is formed by plasma CVD using a gas.₂A film 53 is formed.
[0123]
Next, a gate SiO is formed by sputtering.₂Over the entire surface of the glass substrate 51 on which the film 53 is formed, WSi₂After depositing the layer, CF_FourGas and O₂By the RIE method using a gas, only WSi on the crystalline silicon film 52 is WSi.₂Etching that results in patterning that leaves a layer, WSi₂A polycrystalline gate electrode 54 is formed.
[0124]
Next, impurities are introduced onto the crystalline silicon film 52 in order to form source / drain regions of the thin film transistor. In the case of the fifth embodiment, the above WSi₂The polycrystalline gate electrode 54 serves as a mask when introducing impurities, and WSi₂Impurities are introduced into the crystalline silicon film 52 other than the portion where the polycrystalline gate electrode 54 is provided. In the case of forming an n-type transistor, the introduced impurity is phosphorus (P), and in the case of forming a p-type transistor, the introduced impurity is boron (B).
[0125]
Next, TEOS gas and O_ThreeSiO 2 over the entire surface of the glass substrate 51 by a plasma CVD method using a gas.₂After forming the film 55, CF_FourGas and CHF_ThreeA contact hole 56 is formed on the crystalline silicon film 52 serving as a source / drain region by an RIE method using a gas.
[0126]
Next, after depositing Al on the entire surface of the substrate by sputtering, BCl_ThreeGas and Cl₂SiO2 by RIE method using gas₂An Al wiring 57 is formed which is electrically connected to the crystalline silicon film 52 through a contact hole 56 formed in the film 55.
[0127]
Next, SiH_FourGas and NH_ThreeGas or N₂A SiN protective film 58 is formed over the entire surface of the substrate by plasma CVD using a gas, and finally a part of the SiN protective film 58 is CF_FourGas and CHF_ThreeThrough holes 59 are formed so as to be conductive to one side portion of the Al wiring 57 by etching using a gas, and a semiconductor device such as a semiconductor transistor, a resistor, or a capacitor is completed.
(Embodiment 6)
FIG. 13 is a cross-sectional view showing a method of manufacturing a display device using the semiconductor device of the sixth embodiment.
[0128]
In the sixth embodiment, a method for manufacturing a display device such as a liquid crystal display device using a semiconductor device manufactured by the same method as in the fifth embodiment will be described.
[0129]
Hereinafter, the sixth embodiment will be described with reference to FIGS. 13 (a) and 13 (b).
[0130]
First, a semiconductor device is manufactured on an insulating substrate 51 such as a glass substrate by the manufacturing method of the fifth embodiment. The components of the semiconductor device formed on the insulating substrate 51 are denoted by the same reference numerals as those in the fifth embodiment, and detailed description thereof is omitted.
[0131]
Next, an ITO film is formed over the entire surface of the substrate on which the SiN protective film 58 is formed, followed by HCl and FeCl._ThreeEtching is performed using gas and patterning is performed to form a pixel electrode 60 that is electrically connected to the Al wiring 57 of the semiconductor device through the through hole 59 formed in the SiN protective film 58.
[0132]
Next, SiH_FourGas and NH_ThreeGas or N₂A SiN film 61 is formed over the entire surface of the substrate by plasma CVD using a gas. Further, a polyimide film 62 serving as an alignment film is formed on the SiN film 61 by using an offset printing method, and a rubbing process is performed.
[0133]
On the other hand, as shown in FIG. 13B, a film with R (red), G (green), and B (blue) photosensitive resin films on another glass substrate 71 is transferred by thermocompression bonding. Then, patterning is performed by a photolithography process. Further, a black matrix portion having a light shielding property is formed between portions where the photosensitive resins of R, G, and B are transferred, and the color filter 72 is manufactured. .
[0134]
On the color filter 72, an ITO film is formed over the entire surface of the substrate by a sputtering method to form a counter electrode 73. Further, a polyimide film 74 as an alignment film is formed on the counter electrode 73 by an offset printing method, and a rubbing process is performed.
[0135]
The glass substrate 71 on which the color filter 72 and the like shown in FIG. 13B formed as described above and the glass substrate 51 on which a semiconductor device such as a thin film transistor shown in FIG. 13A is formed are rubbed. It arrange | positions so that the surface which performed the process may mutually oppose, and it bonds together by sealing resin. At this time, spherical silica is dispersed between the glass substrates 51 and 71 so that the space between the two glass substrates is constant. Then, after injecting liquid crystal as a display medium between both substrates, a polarizing plate or the like is attached to both outer sides of both glass substrates 51 and 71, and a driver IC or the like is mounted on the periphery to complete a liquid crystal display. Is done.
[0136]
Next, the scope of application of the present invention will be described.
[0137]
FIG. 9 shows the shape of the groove 44 formed in the glass substrate 40, and shows the dimension L in the length direction and the dimension W in the width direction of the connection region 41 b of the amorphous silicon film 41. Yes.
[0138]
In the method of forming a semiconductor film according to the first to fourth embodiments, the dimension of the connection region 41b of the amorphous silicon film 41 is such that the width W of the upper surface of the connection region 41b is in the range of 0.2 μm to 10 μm. Thus, the effect of selecting crystal grains is ensured. Moreover, if the length L of the upper surface of the connection region 41b is formed in the range of 0.5 μm to 100 μm, the effect of selecting crystal grains is ensured.
[0139]
When the dimension W in the width direction of the upper surface of the connection region 41 is smaller than 0.2 μm, or when the length L of the upper surface of the connection region 41 is larger than 100 μm, the crystal nuclei generated in the catalyst material introduction region 43 are The crystal orientation does not pass through the connection region 41b to the second main region 41c on the front side of the crystal growth with respect to the connection region 41b. On the contrary, when the dimension in the width direction of the upper surface of the connection region 41b is larger than 10 μm, or when the length of the upper surface of the connection region 41b is smaller than 0.5 μm, a plurality of occurrences in the catalyst material introduction region 43 are caused. The crystal grains are not selected as a single crystal grain in the connection region 41b, and a plurality of crystal grains pass through the connection region 41b, and the second main region 41c on the front side of the crystal growth with respect to the connection region 41b. Thus, a plurality of crystal grains grow, and a crystalline semiconductor film composed of large crystal grains with uniform crystal orientation cannot be formed.
[0140]
In the semiconductor film forming methods of the first to fourth embodiments, the amorphous silicon film 41 is formed by plasma CVD at a film formation temperature of 300 ° C., and the hydrogen concentration in the film is 10 to 20 at%. However, the amorphous silicon film 41 may be formed by an ion implantation method. Further, in order to set the hydrogen concentration in the film to 10 to 20 at%, it is preferable to set the film forming temperature in the range of 250 to 350 ° C.
[0141]
Further, in the method for forming a crystalline semiconductor film of the first to fourth embodiments, a method for forming a silicon film is shown as a specific example of a semiconductor film to be manufactured. The formation method is not limited to the silicon film, and can also be applied when a SiGe film or the like is formed.
[0142]
In the first to fourth embodiments, a glass substrate is used as a substrate on which a semiconductor film is formed.₂A film or a SiN film may be used.
[0143]
Moreover, in the said Embodiment 1-4, the surface concentration of nickel introduce | transduced into the catalyst substance introduction area | region 43 is 1 * 10.¹³~ 5x10¹³Piece / cm²The concentration was 1 × 10¹¹~ 1x10¹⁶Piece / cm²It may be in the range. Nickel is introduced into the catalyst material introduction region 43 by vapor deposition using a sputtering method, but may be introduced by other vapor deposition methods such as vacuum vapor deposition, and includes nickel in addition to the vapor deposition method. Other methods such as a method of applying a solution, an ion implantation method, and a CVD method may be used.
[0144]
In the first to fourth embodiments, nickel is used as a catalyst material for promoting crystallization. However, a metal such as Fe, Co, Cu, Ge, Pd, or Au, or a compound containing these metals, Furthermore, what combined these metals and the compound containing a metal can be used.
[0145]
【The invention's effect】
According to the method for forming a semiconductor film of the present invention, a semiconductor film formed on a substrate is given energy for melting the semiconductor film, and crystal growth is performed by crystallization after melting to form a semiconductor film to be a crystalline semiconductor film. A method of forming a semiconductor film having a hydrogen concentration in the film of 10 to 20 at% on the substrate; a step of introducing a catalytic material that promotes crystallization of the semiconductor film; and And a step of applying energy to the introduced semiconductor film.
[0146]
Thus, after introducing a catalytic substance into a semiconductor film having a hydrogen concentration of 10 to 20 at% in the film and then growing the crystal by applying energy, a crystalline semiconductor film having a high orientation ratio is formed in the vicinity of (111). Obtainable.
[Brief description of the drawings]
FIGS. 1A and 1B are perspective views illustrating a method for forming a crystalline semiconductor film according to a first embodiment for each step. FIGS.
FIG. 2 is a plan view for explaining a distance a from an end portion of a catalyst substance introduction region to a connection region.
FIGS. 3A and 3B are perspective views illustrating a method for forming a crystalline semiconductor film according to a second embodiment, respectively.
FIG. 4 is a plan view showing an amorphous silicon film patterned so that a second region smoothly continues from a connection region.
FIG. 5 is a plan view showing an amorphous silicon film patterned so that a connection region and a second main region are not smoothly continuous but have an edge shape.
6A to 6C are perspective views illustrating a method for forming a crystalline semiconductor film according to a third embodiment, respectively.
FIG. 7 shows a cross-sectional view in a direction perpendicular to the longitudinal direction of a glass substrate on which a groove is formed.
8A to 8C are perspective views illustrating a method for forming a crystalline semiconductor film according to a fourth embodiment, respectively.
9 is a perspective view showing another example of a groove formed in a substrate in the method for forming a crystalline semiconductor film of Embodiment 4. FIG.
10A and 10B illustrate an amorphous silicon film manufactured as a sample, where FIG. 10A is a cross-sectional view thereof, FIG. 10B is a plan view thereof, and FIG. 10C is a case where a connecting portion is formed. Plan views are respectively shown.
11 is a graph showing the crystal orientation distribution shown in Table 1. FIG.
12 is a cross-sectional view showing a method for manufacturing the semiconductor device of Embodiment 5. FIG.
13A and 13B are cross-sectional views showing a method for manufacturing a display device using the semiconductor device of the sixth embodiment, respectively.
14 is a plan view illustrating a method for forming a semiconductor film according to Conventional Example 1. FIG.
FIG. 15 is a perspective view illustrating a method for forming a semiconductor film according to Conventional Example 2;
FIG. 16 is a plan view illustrating a method for forming a semiconductor film according to Conventional Example 3;
17 is a cross-sectional view illustrating a method for forming a semiconductor film of Conventional Example 4. FIG.
18A and 18B are cross-sectional views illustrating a method for forming a semiconductor film of Conventional Example 5, respectively.
[Explanation of symbols]
40 glass substrate
41 Amorphous silicon film
42 SiO₂film
43 Catalyst Material Introduction Area
44 Groove
51 glass substrate
52 Crystalline silicon film
53 Gate SiO₂film
54 WSi₂Polycrystalline gate electrode
55 SiO₂film
56 contact hole
57 Al wiring
58 SiN protective film
59 Through hole
60 pixel electrodes
61 SiN film
62 Polyimide film
71 glass substrate
72 Color filter
73 Counter electrode
74 Polyimide film
101 crystal grains
102 crystal grains
103 Grain boundary

Claims (8)

A method for forming a crystalline silicon film by applying energy to an amorphous silicon film formed on a substrate and growing the crystal to form a crystalline silicon film,
Forming an amorphous silicon film on the substrate in a temperature range of 250 to 350 ° C. to form an amorphous silicon film having a hydrogen concentration of 10 to 20 at% in the film;
Next, the amorphous silicon film is formed in a linear shape along a predetermined direction, the first main region and the second main region provided at a distance from each other, and the first main region and the second main region. A step of patterning so as to have a connecting region that is provided so as to connect both of the regions and whose width dimension is smaller than that of the first and second main regions;
Forming a catalytic material introduction region into which the catalytic material for promoting crystallization of the amorphous silicon film is selectively introduced in the first main region;
Introducing nickel as the catalyst material into the catalyst material introduction region;
By applying energy to the amorphous silicon film into which the nickel has been introduced, the crystal orientation of the amorphous silicon film in the vertical direction of the substrate is substantially aligned (111) , and the horizontal direction of the substrate is A step of forming crystalline silicon having substantially uniform crystal orientation in the direction ;
A method for forming a crystalline silicon film, comprising:   2. The method of forming a crystalline silicon film according to claim 1, wherein in the patterning step, the amorphous silicon film is patterned so that the connection region and the second main region are smoothly continuous. Before forming the amorphous silicon film on the substrate, a groove portion having a smoothly continuous side surface and bottom surface is formed on the substrate corresponding to the shape of the amorphous silicon film patterned in the patterning step. Further comprising the step of forming
The method for forming a crystalline silicon film according to claim 1, wherein in the patterning step, the amorphous silicon film on the substrate other than the amorphous silicon film buried in the groove is removed.   4. The crystallinity according to claim 3, wherein the groove is formed such that the connection region and the second main region of the amorphous silicon film patterned in the patterning step are smoothly continuous. 5. A method for forming a silicon film.   2. The method for forming a crystalline silicon film according to claim 1, wherein a dimension in a width direction of the connection region is formed to be in a range of 0.2 μm to 10 μm.   2. The method for forming a crystalline silicon film according to claim 1, wherein a dimension in a length direction of the connection region is formed to be in a range of 0.5 μm to 100 μm.   A semiconductor device comprising the crystalline silicon film according to claim 1.   A display device comprising the semiconductor device according to claim 7.

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