JP4621137B2 - Communication equipment - Google Patents

Description

  The present invention relates to a communication device that switches a plurality of communication partner devices to communicate with them, and a communication device system including the communication device.

  In a general mobile phone system, a service area is divided into cells, and a base station is arranged in each cell. When a mobile phone located in a certain cell moves to another cell, a handover is performed to switch the communication base station of the mobile phone to the nearest base station.

In addition, the technique regarding mobile communication is disclosed by patent documents 1-7.
JP-A-8-251654 JP-A-6-334593 JP 2003-309870 A JP 2003-332939 A JP-A-5-75531 Japanese Patent Laid-Open No. 9-162841 US Pat. No. 6,236,843

  Now, in a general mobile phone system, a plurality of base stations are different from each other because a relative speed, a radio wave reflection and a scattering state between the mobile phone and the base station are different between a plurality of base stations. It is operating at the operation timing.

  The voice system in the mobile phone is provided with an A / D converter and a D / A converter for processing voice data, which operate in synchronization with the operation timing of the base station in communication. ing. Therefore, when a mobile phone communicates with another base station after handover is performed, the operation timing of the A / D converter or the D / A converter that processes voice data may change abruptly.

  As a result, the A / D converter or the D / A converter may malfunction, and abnormal noise may occur to the user. Alternatively, it is necessary to execute the mute function for a long time with the audio output level of the mobile phone set to zero in order to prevent the occurrence of the abnormal noise.

  In recent years, handover between different communication systems such as a GSM (Global System for Mobile communication) system and a W-CDMA (Wideband-Code Division Multiple Access) system has also been realized. It is becoming increasingly difficult to adjust the operation timing between them, and the above problem is inevitable.

  Accordingly, an object of the present invention is made in view of the above-described problems, and is an A / D (Analog / Digital) converter or a D / A (Digital / Analog) converter that processes audio data in a communication device. It is an object of the present invention to provide a technique capable of suppressing the malfunction of the system.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  The communication device of the present invention is a communication device that switches between a plurality of communication partner devices and communicates with them, and operates in synchronization with a free-running clock signal, and converts analog audio data into digital audio data And at least one D / A converter that operates in synchronization with the free-running clock signal and converts digital audio data into analog audio data, and generates the free-running clock signal. And a PLL unit that synchronizes with a synchronous clock signal that is synchronized with the operation timing of the communicating counterpart device.

  The communication device system of the present invention includes a plurality of communication partner devices and a communication device that switches the plurality of communication partner devices to communicate with them, and the communication device operates in synchronization with a free-running clock signal. At least one of an A / D converter that converts analog audio data into digital audio data, and a D / A converter that operates in synchronization with the free-running clock signal and converts digital audio data into analog audio data; A PLL unit that generates the free-running clock signal and synchronizes the free-running clock signal with a synchronous clock signal that is synchronized with an operation timing of the communicating counterpart device.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  A PLL unit that synchronizes the A / D converter that processes audio data or the free-running clock signal that operates in synchronization with the D / A converter with the synchronous clock signal that synchronizes with the operation timing of the communicating counterpart device is provided. It has been. Therefore, by appropriately adjusting the characteristics of the PLL unit, a free-running clock signal with little phase change can be realized even when the phase of the synchronous clock signal changes greatly when the communication counterpart device is switched. Therefore, it is possible to prevent the A / D converter or the D / A converter from malfunctioning when the communication counterpart device is switched, and it is possible to appropriately process the audio data.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  FIG. 1 is a diagram showing a configuration of a communication device system 100 according to an embodiment of the present invention. A communication device system 100 according to the present embodiment is a cellular mobile phone system that is communicated by, for example, a TDMA (Time Division Multiple Access) method, and includes two types of a GSM system and a W-CDMA system. ing.

  As shown in FIG. 1, the communication device system 100 includes a plurality of GSM cells 50 and a plurality of W-CDMA cells 60. A plurality of GSM base stations 5 are arranged in each of the plurality of GSM cells 50, and a plurality of W-CDMA base stations 6 are arranged in each of the plurality of W-CDMA cells 60.

  The mobile phone 1 in this communication device system 100 can switch between a plurality of GSM base stations 5 and communicate with them, and can further switch between a plurality of W-CDMA base stations 6 and communicate with them. is there. The mobile phone 1 can also switch between the GSM base station 5 and the W-CDMA base station 6 to communicate with them.

  When the mobile phone 1 moves from one GSM cell 50 to another GSM cell 50 adjacent thereto as indicated by an arrow 70, the mobile phone 1 performs a handover and switches communication counterpart devices.

  Further, as indicated by an arrow 80, the mobile phone 1 also performs a handover when switching from the GSM cell 50 to the W-CDMA cell 60 to switch the communication partner device. Furthermore, the mobile phone 1 also performs a handover when moving from one W-CDMA cell 60 to another W-CDMA cell 60.

  FIG. 2 is a block diagram showing a configuration of the mobile phone 1 according to the present embodiment.

  As shown in FIG. 2, the mobile phone 1 as a communication device includes a transmission antenna 11, a transmission RF unit 12, a TDMA transmission unit 13, a voice compression unit 14, a transmission mute function execution unit 15, An A / D converter 16 and a microphone 17 are provided.

  Further, the cellular phone 1 includes a receiving antenna 21, a receiving RF unit 22, a TDMA receiving unit 23, an audio decompressing unit 24, a receiving mute function executing unit 25, a D / A converter 26, and a speaker 27. It has. The mobile phone 1 includes a network synchronization clock PLL unit 31, a mute controller 32, a PCM clock generation unit 33, and a free-running clock PLL unit 34.

  TDMA transmission unit 13, audio compression unit 14, transmission mute function execution unit 15, TDMA reception unit 23, audio expansion unit 24, reception mute function execution unit 25, mute controller 32, PCM clock generation unit 33, and free-running clock PLL unit 34 Constitutes a semiconductor integrated circuit and is accommodated in one package 40. Not only these components but also the transmission RF unit 12, the A / D converter 16, the reception RF unit 22, the D / A converter 26, and the network synchronization clock PLL unit 31 are integrated on a single semiconductor substrate. May be stored in the package 40.

  The microphone 17 converts the input sound into analog sound data SAMD and outputs it to the A / D converter 16. A / D converter 16 operates in synchronization with free-running clock signal SC8K output from free-running clock PLL section 34.

  The free-running clock signal SC8K is, for example, a clock signal having a frequency of 8 kHz or a frequency close thereto. The A / D converter 16 includes an A / D built-in PLL unit 16a, and the A / D built-in PLL unit 16a has a frequency obtained by multiplying the frequency of the free-running clock signal SC8K. A sampling clock signal synchronized with the signal is generated.

  Then, the A / D converter 16 samples the analog audio data SAMD using the generated sampling clock signal, and then performs quantization and encoding to convert the analog audio data SAMD into PCM (Pulse Code Modulation). Digital audio data SDMD is generated. The digital audio data SDMD is composed of, for example, 13 bits or 14 bits.

  A PCM clock signal PCLK output from the PCM clock generator 33 is also input to the A / D converter 16. The frequency of the PCM clock signal PCLK is sufficiently higher than the free-running clock signal SC8K and is, for example, 13 MHz.

  Each time the 8 kHz free-running clock signal SC8K rises, the A / D converter 16 serially outputs 13-bit or 14-bit digital audio data SDMD bit by bit in synchronization with the rise of the PCM clock signal PCLK.

  The transmission mute function execution unit 15 executes the mute function by operation control by the mute controller 32. The transmission mute function execution unit 15 outputs the digital audio data SDMD output from the A / D converter 16 with a signal level of zero or minute at the time of handover, and in other cases, the input digital data The audio data SDMD is output as it is.

  The audio compressor 14 receives the free-running clock signal SC8K and the PCM clock signal PCLK. The audio compression unit 14 takes in the digital audio data SDMD output from the transmission mute function execution unit 15 each time the free-running clock signal SC8K rises.

  At this time, the audio compression unit 14 takes in the digital audio data SDMD bit by bit in synchronization with the rising edge of the PCM clock signal PCLK. Then, the audio compression unit 14 executes audio compression processing on the captured digital audio data SDMD, and outputs the compressed digital audio data SDMD. For example, the audio compression unit 14 compresses digital audio data SDMD composed of 13 bits or 14 bits into 4-bit or 8-bit data.

  The audio compression unit 14 also receives the network synchronization clock signal NC8K output from the TDMA receiving unit 23. The network synchronization clock signal NC8K is a clock signal synchronized with the operation timing of the base station with which the cellular phone 1 is communicating, and its frequency is, for example, 8 kHz. Each time the network synchronization clock signal NC8K rises, the voice compression unit 14 serially outputs the compressed digital voice data SDMD having a 4-bit or 8-bit configuration bit by bit in synchronization with the rise of the PCM clock signal PCLK.

  The network synchronization clock signal NC8K and the PCM clock signal PCLK are input to the TDMA transmission unit 13. The TDMA transmission unit 13 takes in the compressed digital audio data SDMD output from the audio compression unit 14 every time the network synchronization clock signal NC8K rises.

  At this time, the TDMA transmission unit 13 takes in the digital audio data SDMD bit by bit in synchronization with the rising edge of the PCM clock signal PCLK. Then, the TDMA transmission unit 13 incorporates the captured digital audio data SDMD into the communication frame 200 together with other data. Thereafter, the TDMA transmission unit 13 performs digital modulation processing on the carrier wave, superimposes the communication frame 200 on the carrier wave, and outputs it to the transmission RF unit 12.

  FIG. 3 is a diagram illustrating an example of the configuration of the communication frame 200.

  As shown in FIG. 3, the communication frame 200 includes, for example, a header part 200a, a control part 200b, a data part 200c, and an FCS part 200d. The header part 200a stores a code indicating the head of the frame, and the control part 200b stores a control signal for communication.

  Various data such as audio data is stored in the data part 200c, and a code for detecting a frame error is stored in the FCS part 200d. The TDMA transmission unit 13 incorporates the compressed digital audio data SDMD into the data unit 200c.

  The transmission RF unit 12 performs amplification processing on the modulated carrier wave received from the TDMA transmission unit 13 and outputs the processed carrier wave via the transmission antenna 11. The radio wave output from the transmitting antenna 11 is received by the GSM base station 5 or the W-CDMA base station 6.

  When a reception signal from the GSM base station 5 or the W-CDMA base station 6 is input via the reception antenna 21, the reception RF unit 22 performs amplification processing or the like on the reception signal, The processed reception signal is output to the TDMA receiving unit 23. The TDMA receiving unit 23 performs demodulation processing on the input received signal and extracts the communication frame 200 from the received signal.

  The TDMA receiver 23 extracts the digital audio data RDMD from the extracted communication frame 200. The digital audio data RDMD extracted here is compressed audio data, and is composed of, for example, 4-bit or 8-bit data.

  Further, the network synchronization clock signal NC13M output from the network synchronization clock PLL unit 31 is input to the TDMA reception unit 23. The network synchronization clock signal NC13M is a clock signal synchronized with the carrier wave in the reception signal input to the reception RF unit 22, and has a frequency of, for example, 13 MHz.

  The TDMA receiver 23 generates and outputs a network synchronization clock signal NC8K that is synchronized with the frame period of the GSM base station 5 or W-CDMA base station 6 that is communicating based on predetermined data included in the received signal. . The TDMA receiver 23 divides the network synchronization clock signal NC13M by 1625 at a predetermined timing to generate an 8 kHz network synchronization clock signal NC8K.

  Further, the PCM clock signal PCLK is also input to the TDMA receiver 23. Each time the network synchronization clock signal NC8K rises, the TDMA receiving unit 23 serially outputs the extracted 4-bit or 8-bit digital audio data RDMD bit by bit in synchronization with the rise of the PCM clock signal PCLK.

  The network expansion clock signal NC8K and the PCM clock signal PCLK are input to the voice decompression unit 24. The audio decompression unit 24 takes in the digital audio data RDMD output from the TDMA reception unit 23 every time the network synchronization clock signal NC8K rises.

  At this time, the audio decompression unit 24 captures the digital audio data RDMD bit by bit in synchronization with the rising edge of the PCM clock signal PCLK. Then, the audio decompression unit 24 performs audio decompression processing on the captured digital audio data RDMD, and outputs the decompressed digital audio data RDMD. For example, the audio decompression unit 24 decompresses digital audio data RDMD composed of 4 bits or 8 bits into 13 bits or 14 bits.

  In addition, a free-running clock signal SC8K is also input to the voice decompression unit 24. Each time the free-running clock signal SC8K rises, the audio decompression unit 24 serially outputs the 13-bit or 14-bit decompressed digital audio data RDMD one bit at a time in synchronization with the rise of the PCM clock signal PCLK.

  The reception mute function execution unit 25 executes the mute function by operation control by the mute controller 32. The reception mute function execution unit 25 outputs the digital audio data RDMD output from the audio expansion unit 24 at the time of handover with the signal level set to zero or very small. In other cases, the input digital audio data RDMD is output as it is.

  The D / A converter 26 operates in synchronization with the free-running clock signal SC8K. The free-running clock signal SC8K and the PCM clock signal PCLK are input to the D / A converter 26. The D / A converter 26 takes in the digital audio data RDMD output from the reception mute function execution unit 25 each time the free-running clock signal SC8K rises. At this time, the D / A converter 26 takes in the digital audio data RDMD bit by bit in synchronization with the rising edge of the PCM clock signal PCLK.

  The D / A converter 26 includes a D / A built-in PLL unit 26a, and the D / A built-in PLL unit 26a has a frequency obtained by multiplying the frequency of the free-running clock signal SC8K. A conversion clock signal synchronized with the signal is generated.

  The D / A converter 26 decodes the captured digital audio data RDMD and converts the digital audio data RDMD into the analog audio data RAMD every time the generated conversion clock signal rises. Output. The speaker 27 converts the analog audio data RAMD output from the D / A converter 26 into audio and outputs it to the outside.

  The network synchronization clock PLL unit 31 includes a TCXO (temperature compensated crystal oscillator), and synchronizes the clock signal output from the TCXO with the carrier wave of the reception signal in the reception RF unit 22 to generate the network synchronization clock. Output as signal NC13M. The PCM clock generator 33 divides the 13 MHz network synchronization clock signal NC13M or outputs it as it is as the PCM clock signal PCLK.

  The free-running clock PLL unit 34 synchronizes the free-running clock signal SC8K output to the A / D converter 16 and the like with the frame period of the GSM base station 5 or W-CDMA base station 6 in communication. Synchronize with NC8K.

  FIG. 4 is a block diagram showing the configuration of the free-running clock PLL unit 34. As shown in FIG. 4, the free-running clock PLL unit 34 includes a variable frequency divider 34a having a variable frequency dividing ratio, a phase comparator 34b, and a frequency dividing ratio setting unit 34c.

  The variable frequency divider 34a divides the 13 MHz network synchronization clock signal NC13M output from the network synchronization clock PLL unit 31 by the frequency division ratio notified from the frequency division ratio setting unit 34c to obtain a free-running clock signal SC8K. Output. The phase comparator 34b performs phase comparison between the network synchronous clock signal NC8K and the free-running clock signal SC8K output from the variable frequency divider 34a, and outputs the phase comparison result to the frequency division ratio setting unit 34c. The frequency division ratio setting unit 34c determines the frequency division ratio in the variable frequency divider 34a based on the phase comparison result received from the phase comparator 34b, and notifies the variable frequency divider 34a of the frequency division ratio.

  When the phase of the free-running clock signal SC8K is more advanced than the network synchronization clock signal NC8K in the phase comparison result of the phase comparator 34b, the frequency division ratio setting unit 34c sets “1 / (1625 + 1) as the value of the frequency division ratio. ) ”To the variable frequency divider 34a, and if the phase of the free-running clock signal SC8K is delayed from the network synchronization clock signal NC8K,“ 1 / (1625-1) ”is notified as the value of the frequency division ratio. When the phase of the free-running clock signal SC8K coincides with the network synchronization clock signal NC8K, “1/1625” is notified as the value of the frequency division ratio.

  Since the free-running clock PLL unit 34 according to the present embodiment is configured as described above, when the phase of the free-running clock signal SC8K advances from the variable frequency divider 34a with respect to the network synchronization clock signal NC8K, the network When a clock signal of 7.9951 kHz lower than the frequency of the synchronous clock signal NC8K is output as the free-running clock signal SC8K, and the phase of the free-running clock signal SC8K is delayed from the network synchronous clock signal NC8K, the frequency of the network synchronous clock signal NC8K When the phase of the free-running clock signal SC8K coincides with the network synchronization clock signal NC8K, an 8 kHz clock signal having the same frequency as the network synchronization clock signal NC8K is generated. Output as free-running clock signal SC8K.

  Next, the operation of the mobile phone 1 according to the present embodiment when a handover occurs will be described with reference to FIG.

  FIG. 5 is a diagram illustrating waveforms of various signals when a handover is executed. In the following example, it is assumed that the mobile phone 1 switches the communication partner from the base station A to the base station B by executing the handover.

  When the mobile phone 1 moves from the cell where the base station A is located to the cell where the base station B is located, and the signal strength of the received signal from the base station A decreases, the TDMA receiving unit 23 starts communication with the base station A. Switching to communication with the base station B, the communication frame 200 included in the received signal from the base station B is acquired.

  Then, the TDMA receiver 23 generates and outputs a network synchronization clock signal NC8K synchronized with the frame period at the base station B, and notifies the mute controller 32 that the handover has been executed. The mute controller 32 controls the transmission mute function execution unit 15 and the reception mute function execution unit 25 to cause each to execute the mute function.

  Here, as described above, the relative speed between the mobile phone 1 and the base station and the reflection and scattering conditions of the radio waves differ between the plurality of base stations, so that the plurality of base stations have different operation timings. Is working with. Therefore, as shown in FIG. 5, the frame timing signal indicating the frame period of the base station A and the frame timing signal indicating the frame period of the base station B are generally not synchronized.

  Therefore, when a handover occurs in the mobile phone 1 at the timing of the arrow 250 in the figure and the communication partner of the mobile phone 1 is switched from the base station A to the base station B, as shown in a portion 260 in the figure, The period of the rising timing of the network synchronization clock signal NC8K is disturbed, the phase of the network synchronization clock signal NC8K changes greatly, and its frequency temporarily deviates greatly from 8 kHz.

  On the other hand, with respect to the free-running clock signal SC8K, as shown in FIG. 5, in the state where the free-running clock signal SC8K is synchronized with the network synchronization clock signal NC8K, the phase of the network synchronization clock signal NC8K occurs. Changes, the phase of the free-running clock signal SC8K is delayed or advanced from the network synchronization clock signal NC8K.

  As a result, the free-running clock signal SC8K becomes asynchronous with respect to the network synchronization clock signal NC8K, and the frequency of the free-running clock signal SC8K changes from 8 kHz to about 8 kHz (8.00049 kHz or 7.9951 kHz).

  Thereafter, the phase of the asynchronous free-running clock signal SC8K gradually approaches the phase of the network synchronization clock signal NC8K, and the free-running clock signal SC8K is synchronized with the network synchronization clock signal NC8K as shown in FIG. The frequency of the free-running clock signal SC8K is 8 kHz.

  The variable frequency divider 34a of the free-running clock PLL unit 34 changes the division ratio when a certain rising timing is delayed from the network synchronization clock signal NC8K in the free-running clock signal SC8K, and a rising timing later than that. The frequency of the free-running clock signal SC8K is continuously changed from 8 kHz to 8.0049 kHz.

  That is, due to the action of the variable frequency divider 34a, the rising timing of the free-running clock signal SC8K, which has been generated at an interval of 125 μs until then, does not become a value far from 125 μs, but occurs at an interval of about 124.9 μs. Become.

  Further, the variable frequency divider 34a changes the frequency division ratio when a certain rising timing advances from the network synchronous clock signal NC8K in the free-running clock signal SC8K, and makes the subsequent rising timing later than before. By doing so, the frequency of the free-running clock signal SC8K is continuously changed from 8 kHz to 7.9951 kHz.

  In this way, since the free-running clock signal SC8K continuously changes from 8 kHz to about 8 kHz, handover occurs, the phase of the network synchronization clock signal NC8K changes greatly, and the frequency of the network synchronization clock signal NC8K is temporarily changed. Even when the frequency greatly deviates from 8 kHz, the phase of the free-running clock signal SC8K does not change significantly. Even when the free-running clock signal SC8K changes from about 8 kHz to 8 kHz in synchronization with the network synchronization clock signal NC8K, the phase of the free-running clock signal SC8K does not change significantly.

  In the present embodiment, when the free-running clock signal SC8K changes from 8 kHz to 8.0049 kHz or 7.9951 kHz, the phase changes by about 77 ns (= 1/13000000), but the variable frequency divider 34a A clock signal having a higher frequency is input instead of the network synchronization clock signal NC13M, and the phase change amount of the free-running clock signal SC8K is further reduced by changing the division ratio set in the variable frequency divider 34a. can do.

  For example, when a 16 MHz clock signal is input to the variable frequency divider 34a and an 8 kHz free-running clock signal SC8K is output, the frequency division ratio is set to “1/2000” and the free-running frequency is lower than 8 kHz. The frequency division ratio is set to “1/2001” when the clock signal SC8K is output, and the frequency division ratio is set to “1/1999” when the free-running clock signal SC8K having a frequency higher than 8 kHz is output. Then, the characteristics of the free-running clock PLL unit 34 are changed. As a result, the amount of phase change when the frequency of the free-running clock signal SC8K changes can be reduced to 62.5 ns (= 1/16000000).

  FIG. 6 is a state transition diagram of the free-running clock signal SC8K.

  As shown in FIG. 6, the free-running clock signal SC8K in the initial state is in the asynchronous state 300, and its frequency is 7.9951 kHz. The free-running clock signal SC8K in the asynchronous state 300 transitions to the GSM synchronization state 301 in synchronization with the network synchronization clock signal NC8K synchronized with the frame period in the GSM base station 5, or the frame period in the W-CDMA base station 6 When the state transits to the W-CDMA synchronization state 303 in synchronization with the network synchronization clock signal NC8K synchronized with the frequency, the frequency becomes 8 kHz.

  When the phase of the free-running clock signal SC8K in the GSM synchronization state 301 is delayed from the network synchronization clock signal NC8K and the free-running clock signal SC8K transitions to the asynchronous state 300, the frequency becomes 7.9951 kHz. When the phase of the free-running clock signal SC8K advances from that of the network synchronous clock signal NC8K and the free-running clock signal SC8K changes to the asynchronous state 302, the frequency becomes 8.0049 kHz.

  The free-running clock signal SC8K in the asynchronous state 302 transitions to the GSM synchronous state 301 in synchronization with the network synchronization clock signal NC8K synchronized with the frame period in the GSM base station 5, or the frame period in the W-CMDA base station 6 When the state transits to the W-CMDA synchronization state 303 in synchronization with the network synchronization clock signal NC8K synchronized with the frequency, the frequency becomes 8 kHz.

  When the phase of the free-running clock signal SC8K in the W-CDMA synchronization state 303 is delayed from the network synchronization clock signal NC8K and the free-running clock signal SC8K transitions to the asynchronous state 300, the frequency becomes 7.9951 kHz, and W-CDMA When the phase of the free-running clock signal SC8K in the synchronization state 303 advances from that of the network synchronization clock signal NC8K and the free-running clock signal SC8K changes to the asynchronous state 302, the frequency becomes 8.0049 kHz.

  As described above, in mobile phone 1 according to the present embodiment, free-running clock signal SC8K in which A / D converter 16 or D / A converter 26 operates in synchronization is synchronized with network synchronization clock signal NC8K. A free-running clock PLL unit 34 is provided.

  As described above, when a handover occurs, the phase of the network synchronization clock signal NC8K synchronized with the operation timing of the base station in communication may change greatly. Therefore, the A / D converter 16 and the D / A converter 26 However, unlike the present embodiment, when operating in synchronization with the network synchronization clock signal NC8K, they may malfunction. As a result, the cellular phone 1 cannot properly process the audio data, and abnormal noise may occur to the user. Alternatively, when the cellular phone 1 has a mute function as in the present embodiment, the transmission mute function execution unit 15 and the reception mute function execution unit 25 are long in order to suppress the occurrence of abnormal noise. The time mute function needs to be executed, and as a result, the long-time call may be interrupted.

  In this embodiment, since the A / D converter 16 or the D / A converter 26 operates in synchronization with the free-running clock signal SC8K, a handover occurs and the base station of the communication partner is switched. Even when the phase of the synchronous clock signal NC8K changes significantly, the phase change of the free-running clock signal SC8K can be suppressed by appropriately adjusting the characteristics of the free-running clock PLL unit 34. Therefore, malfunction of the A / D converter 16 or the D / A converter 26 can be prevented, and sound data can be processed appropriately. Therefore, generation | occurrence | production of abnormal noise and interruption | blocking of long-time telephone call can be suppressed.

  In the variable frequency divider 34a functioning as a clock output unit capable of outputting a plurality of clock signals having different frequencies, the phase of the free-running clock signal SC8K is network-synchronized in the phase comparison result of the phase comparator 34b. When the clock signal NC8K is advanced, a clock signal having a frequency lower than the frequency of the network synchronization clock signal NC8K is output as the free-running clock signal SC8K, and the phase of the free-running clock signal SC8K is delayed from the network synchronization clock signal NC8K. If so, a clock signal having a frequency higher than that of the network synchronization clock signal NC8K is output as a free-running clock signal SC8K. Therefore, as described above, by changing the frequency of the reference clock signal input to the variable frequency divider 34a and the set division ratio, the frequency of these clock signals output as the free-running clock signal SC8K is changed. The characteristics of the free-running clock PLL unit 34 can be easily adjusted. Therefore, the characteristics of the free-running clock PLL unit 34 that is optimal for the communication device system 100 can be easily realized.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention is suitable for voice data processing technology in communication equipment such as a mobile phone system.

It is a figure which shows the structure of the communication equipment system which concerns on one embodiment of this invention. It is a block diagram which shows the structure of the mobile telephone which concerns on one embodiment of this invention. It is a figure which shows the structure of the communication frame which concerns on one embodiment of this invention. It is a block diagram which shows the structure of the free-running clock PLL part which concerns on one embodiment of this invention. It is a figure which shows the waveform of various signals in the mobile telephone which concerns on one embodiment of this invention. It is a state transition diagram of a free-running clock signal according to an embodiment of the present invention.

Explanation of symbols

1 Cellular phone 5 GSM base station 6 W-CDMA base station 16 A / D converter 26 D / A converter 34 Free-running clock PLL unit 34a Variable frequency divider 34b Phase comparator 100 Communication equipment system NC13M, NC8K Network synchronization clock Signal SC8K Free-running clock signal SAMD, RAMD Analog audio data SDMD, RDMD Digital audio data

Claims (7)

A communication device that switches a plurality of communication partner devices and communicates with them ,
At least one D / A converter for converting the A / D converter, and the digital audio data into analog audio data and converts the analog voice data into digital audio data,
A PLL unit for synchronizing to generate self-run clock signal, said free-running clock signal, the network synchronization clock signal synchronized with the operation timing of the communication partner apparatus during communication,
A mute function execution unit for realizing a mute function,
The communication apparatus performs handover for switching between a first communication partner that outputs a first frame timing signal indicating a first frame period and a second communication partner that outputs a second frame timing signal indicating a second frame period. Run
The PLL unit has a variable frequency divider,
When the handover is executed, the input to the PLL unit is from the input of the network synchronization clock signal synchronized with the first frame timing signal to the input of the network synchronization clock signal synchronized with the second frame timing signal. Changed,
The variable frequency divider is
By controlling the division ratio of the free-running clock signal according to the phase comparison result of the free-running clock signal and the free-running clock signal, control to synchronize with the free-running clock signal,
When the phase of the free-running clock signal is ahead of the network synchronization clock signal, the first division ratio is set,
When the phase of the free-running clock signal is delayed from the network synchronization clock signal, a second division ratio different from the first division ratio is set,
When the phase of the free-running clock signal matches the network synchronization clock signal, a third division ratio is set,
When executing the handover, the variable frequency divider outputs the free-running clock signal whose frequency is continuously changed, and the mute function executing unit outputs the digital audio output from the A / D converter. Execute the mute function for the data signal level,
The A / D converter and the D / A converter are operable in synchronization with the free-running clock signal synchronized with the communication counterpart device generated by the PLL unit before and after execution of the handover. communication equipment characterized by. The communication device according to claim 1, wherein
The communication device includes a receiving unit that generates the network synchronization clock signal. The communication device according to claim 2, wherein
The communication device according to claim 1, wherein the variable frequency divider controls the phase of the free-running clock signal so as not to change significantly when a handover occurs. The communication device according to claim 3, wherein
The first division ratio is 1 / (1625 + 1),
The second division ratio is 1 / (1625-1)
The communication device according to claim 3, wherein the third frequency division ratio is 1/1625. In the communication apparatus of any one of Claims 1-3,
The variable frequency divider, when the first or second frequency division ratio is set, and when a comparison result in which the free-running clock signal is synchronized with the network synchronization clock signal is generated, A communication device characterized by being set. The communication device according to any one of claims 1 to 5,
The PLL unit further includes a frequency division ratio setting device and a phase comparator,
The phase comparator performs a phase comparison between the network synchronization clock signal and the free-running clock signal, and outputs a phase comparison result to the division ratio setting device.
The frequency division ratio setting device sets any one of the first to third frequency division ratios to the variable frequency divider according to the phase comparison result. In the communication apparatus of any one of Claims 1-6,
The mute function by the mute function execution unit is a communication device characterized in that the digital audio data is output with a signal level of zero or minute.

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