JP4622174B2 - Receiver - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a receiving apparatus that receives a digital signal transmitted by a ground wave or a satellite wave.
[0002]
[Prior art]
When transmitting digital data, the transmission side performs error correction coding on the transmission data and then digitally modulates and transmits the signal, and the reception side performs digital demodulation and then decodes the error correction code and transmits the transmission data. Playing. In a digital data transmission system, data transmission with high reliability is performed by adding such an error correction code to transmission data.
[0003]
In general, an error correction code is a concatenation of a convolutional code that can be expected to have an error correction effect even in a low C / N environment and a block code that can completely eliminate an error when an error rate of a certain level is guaranteed. Often used. In particular, a Reed-Solomon (RS) code, which is one of block codes, is widely used because of its good affinity with Viterbi decoding, which is a decoding process for convolutional codes.
[0004]
In addition, when receiving digital satellite broadcasting, an antenna must be installed, but the direction of the antenna needs to be adjusted to the direction in which radio waves are transmitted. In other words, the antenna must be installed in the direction of the satellite. Since digital satellite broadcasting antennas are generally installed outdoors, it is necessary to make adjustments at the time of installation of the antennas. The direction of the antenna is normally adjusted while monitoring whether transmission data can be received or not.
[0005]
[Problems to be solved by the invention]
By the way, in an environment with a high C / N, such as in fine weather, there are few errors in transmission. Therefore, even if the direction of the antenna is slightly deviated from the direction of the satellite, the error component due to the direction deviation is completely corrected by the RS decoder. Therefore, when the antenna is installed on a clear day and the direction of the antenna is adjusted by judging whether transmission data can be received or not, the direction of the antenna cannot be accurately adjusted to the direction of the satellite. .
[0006]
However, if the direction of the antenna is not adjusted accurately, even if reception is possible in fine weather, an error in transmission data will occur if the received electric field is low, such as rainfall or snowfall, and the C / N decreases. The number increases, resulting in a reception state where error correction is impossible.
[0007]
Therefore, when adjusting the direction of the antenna, rather than simply judging whether or not the transmission data has been received, the antenna must be installed with a margin so that an optimal reception state can be obtained from the beginning of the adjustment. Don't be.
[0008]
In addition, when transmitting / receiving transmission data transmitted via a mobile medium such as a digital terrestrial broadcast or a cellular phone, generally, a service area covered by one base station is defined, and within the service area If it is, transmission / reception is performed with the base station. Since the mobile receiver performs error correction by the RS code as described above even if it is received inside this service area, even if it is at the periphery of the service area, a transmission error is detected by the RS decoder. Completely corrected, transmission data can be transmitted and received. However, once out of the service area, the number of error bytes exceeding the error correction capability is generated, and the reception state becomes poor. If the user is likely to be out of the service area, the user can take measures such as adjusting the antenna or matching the reception channel in the next service area in advance. Therefore, it is desirable to notify the user of how much room is left before the current reception state becomes a state where reception is not possible.
[0009]
The present invention has been made in view of such circumstances, and is a receiving device that receives transmission data that has been subjected to convolutional coding after a Reed-Solomon code has been added, and accurately receives a received signal with a simple configuration. It is an object of the present invention to provide a receiving apparatus that detects the reception state of the receiver.
[0010]
[Means for Solving the Problems]
In order to solve the above problems, the present invention Pertaining to The receiving device is digitally modulated data with respect to a predetermined carrier signal, and is transmission data that has been subjected to convolutional coding after a Reed-Solomon code is added. Including signal In the receiving device for receiving Recieved Demodulating means for demodulating transmission data from a received signal, transmission path decoding means for decoding transmission data demodulated by the demodulation means according to a transmission system, and Viterbi decoding for Viterbi decoding transmission data output from the transmission path decoding means Means and transmission data output from the Viterbi decoding means By detecting an error position polynomial using the calculated syndrome, an error flag for identifying the position where an error occurs in each block obtained by dividing the transmission data into a plurality of blocks is detected for each block, Of the transmission data Correct detected errors Perform error correction At the same time, if there are less than 9 error bytes in each block, an error flag for each detected block and a synchronization signal indicating the head byte position of each block when active are displayed. When an error byte of 9 bytes or more exists in each block, an error correction impossible flag indicating that the block cannot be corrected, and the head of each block when active Output sync signal indicating byte position Reed-Solomon decoding means, For blocks that can be error-corrected, the error flag for each block output by the Reed-Solomon decoding means is counted in synchronization with the synchronization signal, and the total error byte count for each block obtained by counting is error-corrected. For a block that cannot be corrected, when the synchronization signal output by the Reed-Solomon decoding unit is active, the error correction output from the Reed-Solomon decoding unit indicates that the block cannot be corrected. Output disabled flag respectively Reception state detection means And the total number of error bytes generated in each block output from the reception state detection means is compared with a predetermined threshold, and if the result of the comparison is that the total number of error bytes is greater than the threshold, Calculates a logical sum of a plurality of comparators that respectively output H and L when the total number of error bytes is smaller than the threshold, the outputs output from the respective comparators, and the error correction impossible flag. And display means comprising the same number of OR circuits as the comparators. It is characterized by that.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a digital satellite broadcast (BS digital broadcast) receiving apparatus to which the present invention is applied will be described as an embodiment of the present invention.
[0013]
As shown in FIG. 1, the BS digital broadcast receiving apparatus 1 includes a tuner 11, a demodulator 12, a Viterbi decoder 13, a transmission path decoder 14, an RS decoder 15, and a reception state detector 16. The reception state display unit 17 and the antenna control unit 18 are provided.
[0014]
The antenna 2 is an antenna capable of controlling the reception direction, which is called a so-called adaptive antenna.
[0015]
An RF signal received by the antenna 2 is input to the tuner 11. The tuner 11 performs amplification, frequency conversion, filtering, etc., and outputs an IF signal. The output IF signal is supplied to the demodulator 12.
[0016]
The demodulator 12 performs digital quadrature demodulation on the IF signal and outputs I and Q signals that are quadrature modulation signals. The output I and Q signals are supplied to the Viterbi decoding unit 13.
[0017]
The Viterbi decoding unit 13 performs Viterbi decoding on transmission data subjected to convolutional encoding. The transmission data subjected to Viterbi decoding is supplied to the transmission path decoding unit 14.
[0018]
The transmission path decoding unit 14 performs transmission path decoding processing according to a transmission path scheme such as deinterleaving, inverse energy spreading, and TMCC (Transmission and Multiplexing Configuration Control) decoding processing. The transmission data subjected to the transmission path decoding process is supplied to the RS decoding unit 15.
[0019]
The RS decoding unit 15 performs RS decoding of RS (204, 188) in units of RS blocks each having 204 bytes, corrects an error byte existing in the RS block, and outputs a transport packet (TSP). The output transport packet is supplied to an MPEG decoder or the like provided in the subsequent stage of the receiving apparatus 1.
[0020]
In the case of digital satellite broadcasting, Reed-Solomon encoding processing is performed by adding 16-byte parity to one 188-byte transport packet. This RS encoding process of RS (204, 188) is a degenerate code of RS (244, 239). The Reed-Solomon code of RS (204, 188) can correct errors of up to 8 bytes existing in one block (204 bytes). That is, the error correction capability of the RS (204, 188) is 8 bytes, and when an error of 9 bytes or more exists in one RS block (204 bytes), the block cannot be corrected.
[0021]
Here, the decoding of the RS code is performed by the following algorithm.
Step 1 The syndrome is calculated from the received codeword with the error added.
Step 2 Find error locator polynomial coefficients.
Step 3 Solve the error locator polynomial.
Step 4 Find the error pattern.
Step 5 Subtract the error pattern from the received codeword.
[0022]
In the RS decoding algorithm, when the error position polynomial is solved (step S3), it is specified which byte in the 1RS block (204 bytes) has an error. In the RS decoding unit 15, error position information obtained by solving this error position polynomial, that is, information specifying which byte position in one RS block has an error (hereinafter referred to as an error flag) is described. , Each block is detected and supplied to the reception state detection unit 16.
[0023]
Also, in the RS decoding algorithm, if there are 9 or more error bytes in one RS block (204 bytes), the RS block cannot be corrected, but the error of the block cannot be corrected, that is, The presence of error bytes of 9 bytes or more can be detected. When there are 9 or more error bytes in one block and an error exceeding the error correction capability exists in the block, the RS decoding unit 15 sends an error correction impossible flag to the reception state detection unit 16. Supply.
[0024]
Furthermore, the RS decoding unit 15 also supplies a synchronization signal (Sync) indicating the head byte position of the RS block to the reception state detection unit 16.
[0025]
The reception state detection unit 16 receives the error flag (Error Flag), the error correction impossible flag, and the synchronization signal (Sync), and detects the reception state of the reception signal received by the antenna 2 based on these pieces of information.
[0026]
The display unit 17 displays the reception state of the reception signal to the user based on the detection result by the reception state detection unit 16.
[0027]
The antenna control unit 18 controls the reception direction of the antenna 2 that functions as an adaptive antenna based on the detection result by the reception state detection unit 16. The antenna control unit 18 controls the direction of the antenna 2 to an optimal position so that the detection result by the reception state detection unit 16 is the best.
[0028]
Next, the reception state detection unit 16 and the display unit 17 will be further described. FIG. 2 shows a configuration diagram of the reception state detection unit 16 and the display unit 17. FIG. 3 shows a time chart of each signal in the reception state detection unit 16.
[0029]
The reception state detection unit 16 includes a synchronization signal (Sync) indicating the position of the first byte of the RS block as shown in FIG. 3A, and an error byte in which byte in the RS block as shown in FIG. The RS decoding unit 15 includes an error flag (Error Flag) that specifies whether or not there is an error and an error correction impossible flag that indicates that an error exceeding the error correction capability as shown in FIG. It is input from.
[0030]
The reception state detection unit 16 includes an error counter 20, a first selector 21, an error register 22, a second selector 23, and an error correction impossible flag register 24.
[0031]
An error flag (Error Flag) is input to the enable terminal (EN) of the error counter 20. Further, a synchronization signal (Sync) is input to the load terminal (LD), and an error flag (Error Flag) is input to the load data terminal (LDData). The error counter 20 increments the internal count value (Q) by 1 when the enable terminal (EN) becomes active (H). When the load terminal (LD) becomes active (H), the value input to the load data terminal (LDData) is loaded as the internal count value (Q).
[0032]
That is, as shown in FIG. 3D, the error counter 20 is input to the enable terminal (EN) between the byte position where the synchronization signal (Sync) is generated and the byte position immediately before the next synchronization signal. Count the number of times the Error Flag is activated. That is, the error counter 20 counts the number of error bytes that have occurred in one RS block. In the error counter 20, even if the error flag is active (H) at the byte position where the synchronization signal (Sync) is active (H) (that is, the first byte position of the RS block), the error is detected. The flag cannot be counted. Therefore, in this error counter 20, by inputting an error flag (Error Flag) to the load data terminal (LDData), the synchronization signal (Sync) is active (H) and the error flag (Error Flag) is active (H). When “1”, the count value (Q) is loaded with “1”, and when the synchronization signal (Sync) is active (H) and the error flag (Error Flag) is not active (L), the count value (Q) ) Is loaded with “0”.
[0033]
The count value (Q) of the error counter 20 and the stored value of the error register 22 at the subsequent stage are input to the first selector 21. The first selector 21 selects and outputs one of the signals according to the state of the synchronization signal (Sync). The first selector 21 selects and outputs the count value of the error counter 20 when the synchronization signal (Sync) is active (H). When the synchronization signal is not active (L), the second selector 21 selects and outputs the stored value of the error register 22 at the subsequent stage. The value output from the first selector 21 is stored in the error register 22.
[0034]
That is, the first selector 21 and the error register 22 store the count value by the error counter 20 in the error register 22 when the synchronization signal is active (H) (that is, the first byte position of the RS block). At other timings, the stored value in the error register 22 is held. That is, the error register 22 holds the total number of error bytes generated in the previous RS block, as shown in FIG.
[0035]
The second selector 23 receives the error correction impossible flag and the stored value of the error correction impossible flag register 24 at the subsequent stage. The second selector 23 selects and outputs one of the signals according to the state of the synchronization signal (Sync). The second selector 23 selects and outputs the error correction impossible flag output from the RS decoding unit 15 when the synchronization signal (Sync) is active (H). When the synchronization signal is not active (L), the second selector 21 selects and outputs the stored value of the error correction impossible flag register 24 at the subsequent stage. The value output from the second selector 23 is stored in the error register 23.
[0036]
That is, in the second selector 23 and the error correction impossible flag register 24, when the synchronization signal (Sync) is active (H) (that is, the first byte position of the RS block), the error correction input from the RS decoder 15 is not possible. The flag value (“1” or “0”) is stored in the error uncorrectable flag register 24, and the stored value in the error uncorrectable flag register 24 is held at other timings. In other words, the error correction impossible flag register 24 holds a value (“0” or “1”) indicating whether or not the RS block is incapable of error correction, as shown in FIG. Note that if the error correction of the RS block is impossible, the RS decoding unit 15 outputs an error correction impossible flag that becomes active (H) at least at the first byte position of the RS block.
[0037]
As described above, the reception state detection unit 16 outputs, for each RS block, the total number of error bytes X generated in the RS block, and a flag Y indicating whether or not the RS block cannot perform error correction. The Rukoto.
[0038]
The error byte count X and the error correction impossible flag Y are supplied to the display unit 17 and the antenna control unit 18.
[0039]
The display unit 17 includes first to nth comparators 25-1 to 25-n, first to nth OR circuits 26-1 to 26-n, and first to (n + 1) th display units 27. -1 to 27- (n + 1).
[0040]
The first to nth comparators 25-1 to 25-n are provided with an input terminal A and an input terminal B, and the values input to the input terminal A and the values input to the input terminal B are obtained. In comparison, when the value input to the input terminal A is larger than the value input to the input terminal B, the output is set to High, and the value input to the input terminal B is input to the input terminal A. If it is larger than the value, the output is set to Low. The total number of error bytes X generated in the RS block held in the register 24 is input to the input terminals A of the comparators 25-1 to 2-n. Also, the first comparison value C1 is input to the input terminal B of the first comparator 25-1, the second comparison value C2 is input to the input terminal B of the second comparator 25-2, The third comparator 25-3 receives the third comparison value C3, and the fourth to nth comparison values C4 to Cn are input to the comparators. The comparison values C1 to Cn are threshold values between the levels for dividing the error amount generated in the RS block into a predetermined number of levels. Each comparison value is a condition of C1 <C2 <C3 <. As appropriate. For example, if n is 8, C1 to Cn are set to 0 to 8.
[0041]
That is, the first to nth comparators 25-1 to 25-n compare the total number of error bytes X generated in the RS block held in the register 24 with each of the comparison values C1 to Cn. If the error byte number X is larger than the comparison values C1 to Cn, the output is set to High, and if the error byte number X is smaller than the comparison values C1 to Cn, the output is set to Low. The output of the first comparator 25-1 is input to the first OR circuit 26-1, and the output of the second comparator 25-2 is input to the second OR circuit 26-2. The outputs of the comparators 25-3 to 25-n are input to the corresponding OR circuits 26-3 to 26-n.
[0042]
The first to nth OR circuits 26-1 to 26-n perform an OR logic operation on the outputs of the comparators 25-1 to 25-n and the error correction impossible flag Y.
[0043]
The first display unit 27-1 emits light when the output of the first OR circuit 26-1 is High, and turns off when the output of the first OR circuit 26-1 is Low. The second display unit 27-2 emits light when the output of the second OR circuit 26-2 is High, and turns off when the output of the second OR circuit 26-2 is Low. Similarly, the third display unit 27-3 to the nth display unit 27-n emit light when the output of the corresponding OR circuit 26-3 to 26-n is High, and turn off when the output is Low. The (n + 1) th display unit 27- (n + 1) is turned on when the error uncorrectable flag Y is High, and is turned off when the error uncorrectable flag Y is Low. The first to (n + 1) th display units 27-1 to 27-(n + 1) are arranged in a line in order in a place that can be seen by the user, such as outside the housing of the receiving device 1. Installed.
[0044]
The operation of the display unit 17 configured as described above will be described.
[0045]
The total error byte count X is compared with each comparison value C1 to Cn by each comparator 25-1 to 25-n. When the total error byte count X is equal to or less than the comparison value C1, the outputs of all the comparators 25-1 to 25-n are Low. When the total error byte count X is greater than the comparison value C1 and less than or equal to C2, only the output of the first comparator 25-1 is High and the outputs of the other comparators are Low. When the total error byte count X is greater than the comparison value C2 and less than or equal to C3, the outputs of the first comparator 25-1 to the second comparator 25-2 are High, and the outputs of the other comparators are Low. It becomes. Similarly, when X is C3 to C4, the first to third comparators 25-1 to 25-3 are High, and when X is C4 to C5, the first to fourth comparators 25-1 are used. ˜25-4 are High,..., And when X is greater than Cn, the outputs of all the first to nth comparators 25-1 to 25-n are High.
[0046]
Further, the RS decoding unit 15 issues an error correction impossible flag to the reception state detection unit 16 for a TS packet in which an error of 9 bytes or more exists in one TS packet and error correction cannot be performed. When the error correction impossible flag is issued, all the display units 27 from the first to the (n + 1) th are turned on.
[0047]
As a result, the display units 27-1 to 27- (n + 1) are displayed as shown in FIG.
[0048]
That is, when the transmission state is good, all the display units are turned off, and thereafter, the display units that are turned on increase one by one as the transmission state deteriorates. When the transmission state deteriorates and TS packets that cannot be corrected are generated, all the display units are forcibly turned on for the TS packets.
[0049]
As described above, in the receiving apparatus 1 according to the embodiment of the present invention, the number of errors for the Reed-Solomon block is detected based on the error position information obtained in the error correction process by Reed-Solomon decoding, and the error correction is performed based on the number of errors. A margin for capability is obtained for each Reed-Solomon block, and the margin is displayed as a reception state of the received signal.
[0050]
For this reason, in the receiving device 1 according to the embodiment of the present invention, for example, it is possible to quantitatively notify the user how much room is available before the current reception state becomes inferior, and the user has this notification. Thus, it is possible to take a countermeasure before the reception state is completely deteriorated.
[0051]
In the receiving apparatus 1 according to the embodiment of the present invention, the number of errors for the Reed-Solomon block is detected based on the error position information obtained in the error correction process by Reed-Solomon decoding, and the margin for error correction capability is based on the number of errors. The degree is obtained for each Reed-Solomon block, and the margin is output to the antenna control unit 18 as a reception state. For this reason, the antenna control unit 17 can quantitatively know whether the reception state is good or bad. For example, when the direction of the antenna is set, the direction can be optimized.
[0052]
In particular, in the receiving device 1 according to the embodiment of the present invention, the reception state is detected during the Reed-Solomon decoding process after the Viterbi decoding process. Therefore, it is possible to accurately grasp the reception state for all systems. Furthermore, the error rate curve (curve showing the error rate with respect to C / N) indicating the characteristics of the transmission line usually has a sharper change in the error rate as C / N becomes larger. Therefore, a low error rate is obtained after the Viterbi decoding process, and the residual error after Viterbi decoding changes sharply even with a slight change in C / N. Therefore, for example, the output sensitivity with respect to the antenna direction becomes very high, and the optimum antenna direction can be accurately grasped.
[0053]
The embodiment has been described by taking the digital satellite broadcast receiver as an example. However, the present invention is not limited to the digital satellite broadcast receiver, and performs transmission that performs error correction processing using a convolutional code and a Reed-Solomon code. Any system can be applied. For example, the present invention can be applied to a digital cellular phone system.
[0054]
Further, the means for notifying the user of the reception state is not limited to the one that is displayed and notified, and any means can be used as long as it can quantitatively notify the user of how much error correction processing is available. May be. For example, notification may be made by voice or text when adjusting the antenna or when a user presses a predetermined button or the like. In addition, the display content is not limited to the volume display as shown in FIG. 4. For example, as shown in FIG. 5, a plurality of indicator lights are arranged in a line. A display method that shifts may be used. In the case of such a display method, as shown in FIG. 6, in place of the OR circuits 26-1 to 26-n, AND circuits 28-1 to 28-n and inverting circuits 29-1 to 29-29 are provided. The control circuit may be configured using -n and OR circuits 30-1 to 30- (n-1).
[0055]
【The invention's effect】
In the receiving apparatus according to the present invention, the number of errors for the Reed-Solomon block is detected based on the error position information obtained in the error correction processing process by Reed-Solomon decoding, the margin for error correction capability is obtained based on the number of errors, and the margin Is output as the reception state of the received signal.
[0056]
Therefore, the receiving apparatus according to the present invention can accurately detect the reception state of the received signal with a simple configuration. For example, the detected reception state can be notified to the user or used for the direction control of the adaptive antenna. In particular, the reception state of the reception signal detected by the present invention is directly obtained based on the margin of the number of error occurrences with respect to the error correction capability by Reed-Solomon. Therefore, for example, it is possible to know how much room is available before the current reception state becomes inferior. Therefore, the user can take a countermeasure before the reception state is completely deteriorated. For example, even in a state where reception is possible, it is possible to detect whether the reception state is better or worse, and based on this detection result, the direction of the antenna is optimized, or the reception channel Can be switched.
[Brief description of the drawings]
FIG. 1 is a block configuration diagram of a digital satellite broadcast receiver according to an embodiment of the present invention.
FIG. 2 is a diagram for explaining a configuration of a reception state detection unit of the reception apparatus.
FIG. 3 is a diagram for explaining signal timing in the reception state detection unit;
FIG. 4 is a diagram for explaining display contents for notifying a user of a transmission state.
FIG. 5 is a diagram for explaining another display example of the transmission state;
6 is a diagram for explaining a configuration example of a reception state display control unit for performing display in another display example shown in FIG. 5; FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Receiving device, 2 Antenna, 11 Tuner, 12 Demodulation part, 13 Viterbi decoding, 14 Transmission path decoding part, 15 RS decoding part, 16 Reception state detection part, 17 Display part, 18 Antenna control part

Claims (3)

In a receiving apparatus for receiving a signal including transmission data that has been digitally modulated with respect to a predetermined carrier wave signal and subjected to convolutional encoding after a Reed-Solomon code is added,
Demodulation means for demodulating transmission data from the received signal received;
Transmission path decoding means for decoding the transmission data demodulated by the demodulation means in accordance with a transmission method;
Viterbi decoding means for Viterbi decoding transmission data output from the transmission path decoding means;
By identifying an error position polynomial using a syndrome calculated from transmission data output from the Viterbi decoding means, the position where an error occurs in each block obtained by dividing the transmission data into a plurality of blocks is specified. An error flag is detected for each block, error correction is performed to correct the detected error of the transmission data, and if there are less than 9 error bytes in each block, each detected block is detected. Error flag and a synchronization signal indicating the head byte position of each block when it is active, and when there are 9 or more error bytes in each block, the block is corrected An error uncorrectable flag indicating that it is impossible, and the position of the first byte of each block when active And Reed-Solomon decoding unit for outputting the to synchronizing signal,
For error-correctable blocks, the error flag for each block output by the Reed-Solomon decoding means is counted in synchronization with the synchronization signal, and the total error byte count for each block obtained by counting is error-corrected. For a block that cannot be corrected, when the synchronization signal output by the Reed-Solomon decoding unit is active, the error correction output from the Reed-Solomon decoding unit indicates that the block cannot be corrected. Reception state detection means for outputting each of the impossible flags ;
The total number of error bytes generated in each block output from the reception state detection means is compared with a predetermined threshold value, and if the result of the comparison is that the total number of error bytes is greater than the threshold value, H When the total number of error bytes is smaller than the threshold, the logical sum of the plurality of comparators that respectively output L, the output output from each of the comparators, and the error correction impossible flag is calculated, Display means comprising the same number of OR circuits as comparators;
A receiving device. The reception state detecting means includes
An error counter, a first selector, an error register, a second selector, and an error correction impossible flag register;
The above error counter is
By counting the error flag for each block output from the Reed-Solomon decoding means in synchronization with the synchronization signal, the number of error bytes generated in each block is counted,
The first selector is
For each block in which the synchronization signal is active, the count value of the error counter is selected and output, and when the synchronization signal is not active, the stored value of the error register is selected and output,
The above error register is
When the sync signal is active, the count value of the error counter is stored. When the sync signal is not active, the value stored in the error register is held in advance, so that the total error generated in the previous block is stored. Hold the number of bytes, and output the data of the total number of error bytes held to the display means,
The second selector is
When the synchronization signal is active, the error correction impossible flag output from the Reed-Solomon decoding means is selected and output. When the synchronization signal is not active, the stored value of the error correction impossible flag register is selected and output. And
The above error correction impossible flag register
When the synchronization signal is active, the error correction impossible flag value input from the Reed-Solomon decoding means is stored, the stored error correction impossible flag value is held, and the held error correction impossible flag value is displayed. The receiving apparatus according to claim 1, wherein when the synchronization signal is not active, the value stored in advance is held and the held value is output to the display means . Notification means for notifying the user of the reception state of the received signal detected by the reception state detection means by voice or text;
Further comprising an antenna control means for controlling the directivity of the antenna for receiving the received signal,
The antenna control unit, based on the reception state of the received signal detected by the receiving condition detecting means, the receiving condition is optimum so as to receive device 請 Motomeko 1 or 2, wherein that controls the directivity of the antenna .

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