JP4628620B2 - Digital AV signal processing device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a digital AV signal processing apparatus. More specifically, the present invention relates to a digital AV signal processing apparatus capable of controlling the speed at which digital data stored in a buffer is DA converted.
[0002]
[Prior art]
In recent years, with the spread of computer networks, a form of viewing AV contents in which a digital AV signal representing AV contents is distributed via the computer network and reproduced (DA conversion) while receiving the digital AV signal in the receiving side apparatus. Is spreading.
[0003]
Within a computer network, the transmission speed of data varies, and fluctuations (for example, jitter) with a short period of the speed can occur in the transmission data. In addition, since the clock is not synchronized between the transmission-side device (server or personal computer) and the reception-side device (digital AV signal processing device), the clock is between the transmission-side device clock and the reception-side device clock. There is a difference.
[0004]
Such jitter and clock difference are not a problem when transmitting normal data for processing by a computer, but jitter and clock difference are a problem when transmitting a digital AV signal. This is because unpleasant disturbance (for example, sound skipping) occurs in the audio signal and the video signal due to such jitter and clock difference.
[0005]
Therefore, it is necessary to control the speed at which the digital data stored in the buffer is DA-converted in order to remove unpleasant disturbances that occur in the audio signal and video signal. For this reason, a technique for controlling the speed at which the digital data stored in the buffer is DA-converted has been developed.
[0006]
FIG. 12 shows a configuration of a conventional digital AV signal processing apparatus 300. The digital AV signal processing apparatus 300 includes a buffer 31, a DA converter 32, a voltage-controlled oscillator (hereinafter referred to as “VCO”) 33, and a voltage-controlled oscillator controller (hereinafter referred to as “VCO controller”). 34.
[0007]
The buffer 31 stores digital data input to the digital AV signal processing device 300 through a transmission system (for example, a computer network), and outputs the digital data as output digital data. The DA converter 32 converts the output digital data into analog data. The conversion speed of the DA converter 32 is determined by the clock signal generated by the VCO 33.
[0008]
When the conversion speed of the DA converter 32 is higher than the input speed of the digital data input to the buffer 31, the data amount of the buffer 31 decreases. When the conversion speed of the DA converter 32 is slower than the input speed of the digital data input to the buffer 31, the data amount of the buffer 31 increases.
[0009]
The VCO controller 34 detects the amount of data in the buffer 31 and controls the frequency of the clock signal generated by the VCO 33 so that the conversion speed of the DA converter 32 becomes an appropriate value.
[0010]
The VCO 33 receives the output data DA3 output from the VCO controller 34. The VCO 33 increases the frequency of the clock signal as the value of the output data DA3 output from the VCO controller 34 increases. The VCO 33 lowers the frequency of the clock signal as the value of the data DA3 output from the adder 36 is smaller.
[0011]
The VCO controller 34 includes a comparator 35, an adder 36, a reference data amount memory 37, and a reference voltage memory 38.
[0012]
The reference data amount memory 37 stores a data amount BHLF that is half the total capacity of the buffer 31. The reference voltage memory 38 outputs output data DA2 that is data for generating a reference clock frequency. The adder 36 adds the value of the output data DA1 and the value of the output data DA2, and outputs the output data DA3.
[0013]
FIG. 13 shows the operating characteristics of the comparator 35. The horizontal axis represents the data amount BDAT of the buffer 31, and the vertical axis represents the output data DA1 output from the comparator 35. BMAX is a data amount of the entire capacity of the buffer 31, and BHLF is a data amount of half of the total capacity of the buffer 31.
[0014]
As the data amount BDAT increases, the value of the output data DA1 output from the comparator 35 increases. When the value of the output data DA1 increases, the value of the output data DA3 increases, and the frequency of the clock signal generated by the VCO 33 is increased to suppress the increase in the data amount BDAT. When the data amount BDAT decreases, the value of the output data DA1 output from the comparator 35 decreases. When the value of the output data DA1 decreases, the value of the output data DA3 decreases, and the frequency of the clock signal generated by the VCO 33 is lowered to suppress the decrease in the data amount BDAT.
[0015]
With the above operation, the speed at which the digital data stored in the buffer is DA converted is controlled.
[0016]
[Problems to be solved by the invention]
FIG. 14 shows changes over time in the input speed of digital data input to the digital AV signal processing device 300. The horizontal axis indicates time. The vertical axis represents the input speed of digital data. At times t1 to t2, times t4 to t5, and times t7 to t8, a short fluctuation (jitter) in the cycle of the input speed occurs. At times t3 to t6, a long fluctuation in speed cycle occurs because the clock frequency of the server or personal computer is unstable.
[0017]
FIG. 15 shows the data amount of the buffer 31 when digital data is input to the digital AV signal processing device 300 at the input speed shown in FIG. The horizontal axis represents time, and the vertical axis represents the data amount BDAT of the buffer 31. Times t1, t2, t3, t4, t5, t6, t7 and t8 correspond to the times t1, t2, t3, t4, t5, t6, t7 and t8 in FIG.
[0018]
FIG. 16 shows the frequency of the recovered clock signal generated by the VCO 33 when digital data is input to the digital AV signal processing device 300 at the input speed shown in FIG. The horizontal axis indicates the time, and the vertical axis indicates the frequency of the recovered clock signal generated by the VCO 33. Times t1, t2, t3, t4, t5, t6, t7 and t8 correspond to the times t1, t2, t3, t4, t5, t6, t7 and t8 in FIG.
[0019]
The influence of the short fluctuation of the input speed cycle shown in FIG. 14 (see time t1 to t2, time t4 to t5 and time t7 to t8 in FIG. 14) does not greatly affect the frequency of the recovered clock signal. That is, the fluctuation (pitch fluctuation) of the frequency of the reproduced clock signal shown in FIG. 16 is suppressed (see times t1 to t2, times t4 to t5 and times t7 to t8 in FIG. 16), and the reproduced sound quality is improved. .
[0020]
However, the conventional digital AV signal processing apparatus 300 controls only the deviation of the clock signal frequency from a predetermined value of the amount of digital data stored in the buffer (for example, a value BHLF which is half the capacity of the buffer). Therefore, if the data amount BDAT of the digital data stored in the buffer remains constant with a deviation from a predetermined value (time t3 to t6 in FIG. 15), the frequency of the clock signal The value remains constant (time t3 to t6 in FIG. 16). Therefore, when the input speed of the input digital data is accompanied by a fluctuation with a long cycle, a state in which the data amount of the digital data stored in the buffer deviates from a predetermined value may persist. In such a state, buffer overflow or underflow is likely to occur.
[0021]
The present invention has been made in view of the above problems, and the digital data stored in the buffer is eliminated so that the deviation of the data amount of the buffer caused by the fluctuation of the input speed of the input digital data with a long cycle is eliminated. An object of the present invention is to provide a digital AV signal processing apparatus capable of controlling the speed at which data is DA-converted.
[0022]
[Means for Solving the Problems]
A digital AV signal processing device according to the present invention includes a buffer for storing digital data input to the digital AV signal processing device and outputting the digital data as output digital data, and a DA converter for converting the output digital data into analog data. A voltage-controlled oscillator that generates a clock signal for controlling the conversion speed of the DA converter, and a data amount of the digital data stored in the buffer, and a predetermined first amount of the detected data amount And a voltage-controlled oscillator controller for controlling the frequency of the clock signal based on a deviation from the value of 1 and a time integral value of the deviation, thereby achieving the above object.
[0023]
The voltage-controlled oscillator controller is configured such that a ratio of a change in the frequency of the clock signal to a change in the deviation when the deviation is larger than a certain range is a variation in the deviation when the deviation is smaller than the certain range. The frequency of the clock signal may be controlled so as to be larger than the rate of change of the frequency of the clock signal with respect to.
[0024]
The buffer is a ring buffer, and the digital data input to the digital AV signal processing device is input to the ring buffer at a data write position of the ring buffer, and the ring buffer stores data in the ring buffer. The digital data is output at a read position, and the voltage controlled oscillator controller calculates the data amount of the digital data stored in the ring buffer based on the data read position and the data write position, The voltage-controlled oscillator controller has a predetermined value when the data amount becomes larger than a predetermined second value larger than the predetermined first value or when the data amount is smaller than the predetermined first value. When the value becomes smaller than the third value of Location and may change at least one of said data write position.
[0025]
The voltage-controlled oscillator controller may change at least one of the data read position and the data write position so that the data amount after change is substantially half of the capacity of the ring buffer.
[0026]
The digital data is input to the digital AV signal processing apparatus in the form of a plurality of packets, and the voltage controlled oscillator controller detects the data amount of the buffer in synchronization with the input timing of the plurality of packets. Good.
[0027]
The digital data is input to a digital AV signal processing apparatus in the form of a plurality of packet groups, and each of the plurality of packet groups has a predetermined number of first packets and a second data amount having a first data amount. A predetermined number of second packets having a plurality of packets arranged in a predetermined order, and the voltage-controlled oscillator controller synchronizes the data amount of the buffer in synchronization with a timing at which the plurality of packet groups are input. It may be detected.
[0028]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to FIGS.
[0029]
FIG. 1 shows a configuration of a digital AV signal processing apparatus 100 according to an embodiment of the present invention. The digital AV signal processing apparatus 100 includes a buffer 1, a DA converter 2, a VCO 3, and a VCO controller 4.
[0030]
The buffer 1 stores digital data input to the digital AV signal processing apparatus 100 through the transmission system, and outputs this digital data as output digital data. The DA converter 2 converts the output digital data into analog data. The conversion speed of the DA converter 2 is determined by the clock signal generated by the VCO 3.
When the conversion speed of the DA converter 2 is higher than the input speed of the digital data input to the buffer 1, the data amount of the buffer 1 decreases. When the conversion speed of the DA converter 2 is slower than the input speed of the digital data input to the buffer 1, the data amount of the buffer 1 increases. The VCO controller 4 detects the data amount of the digital data stored in the buffer 1, and a clock signal generated by the VCO 3 based on a deviation from a predetermined value of the detected data amount and a time integral value of the deviation. To control the frequency.
[0031]
The VCO controller 4 includes a first control unit 5, a second control unit 7, a reference data amount memory 13 for storing a data amount half the total capacity of the buffer 1, an adder 11, and a second hold Means 12.
[0032]
The first control means 5 includes a first comparator 6 (K1 indicates a gain) that compares the data amount BDAT of the buffer 1 with a data amount BHLF that is half of the total capacity of the buffer 1. The first comparator 6 detects a deviation between the data amount BDAT and the data amount BHLF, and outputs output data DA1 based on the deviation and the gain K1 to the adder 11.
[0033]
FIG. 2 shows operating characteristics of the first comparator 6. The horizontal axis represents the data amount BDAT of the buffer 1, and the vertical axis represents the output data DA1 output from the first comparator 6. BMAX is a data amount of the entire capacity of the buffer 1, and BHLF is a data amount half of the total capacity of the buffer 1. The operating characteristic of the first comparator 6 is set to a straight line passing through the point (BHLF, 0) with the gradient K1. The first control means 5 has an operation cycle set to 10 msec. The first control means 5 determines the time constant of the first control means 5 based on the operation characteristics (gradient K1) of the first comparator 6 and the operation cycle of the first control means 5.
[0034]
The second control means 7 includes a second comparator 8 (K2 indicates a gain) that compares the data amount BDAT of the buffer 1 with a data amount BHLF that is half the total capacity of the buffer 1, and a second comparator. 8 includes an integrator 9 for time-integrating the output data DA0 output from 8 and first hold means 10 for holding the output of the integrator 9.
[0035]
FIG. 3 shows the operating characteristics of the second comparator 8. The horizontal axis represents the data amount BDAT of the buffer 1, and the vertical axis represents the output data DA0 output from the second comparator 8. BMAX is a data amount of the entire capacity of the buffer 1, and BHLF is a data amount half of the total capacity of the buffer 1. The operation characteristic of the second comparator 8 is set to a straight line passing through the point (BHLF, 0) with the gradient K2. The operation period of the second control means 7 is set to 100 msec. The second control means 7 determines the time constant of the second control means 7 based on the operation characteristics (gradient K2) of the second comparator 8 and the operation cycle of the second control means 7.
[0036]
The gradient K2 is set to a value much smaller than the gradient K1. The operation period of the first control means 5 is set to 10 msec. The operation period of the second control means 7 is set to 100 msec. Here, 1 / time constant = gradient / operation cycle. Therefore, the time constant of the first control means 5 is smaller than the time constant of the second control means 7.
[0037]
The second comparator 8 detects a deviation between the data amount BDAT and the data amount BHLF, and outputs output data DA0 based on the deviation and the gain K2 to the integrator 9.
[0038]
The integrator 9 time-integrates the output data DA0 output from the second comparator 8 to obtain an integral value. The integrated value obtained by the integrator 9 is held by the first holding means 10.
[0039]
The first hold means 10 outputs the hold value to the adder 11 as output data DA2. The first hold means 10 updates the hold value at a cycle of 100 ms. The first hold means 10 is necessary when the control period of the second control means 7 is set longer than the control period of the first control means 5.
[0040]
The adder 11 adds the output data DA1 and the output data DA2, and obtains output data DA3 output from the VCO controller 4.
[0041]
The second hold means 12 outputs the output data DA3 from the adder 11 to the VCO3. The second hold means 12 updates the hold value at a cycle of 10 ms.
[0042]
As described above, the first control means 5, the second control means 7, the adder 11, the second hold means 12, and the reference data amount memory 13 are digitally stored in the buffer as a whole. It functions as the VCO controller 4 that detects the data amount of the data and controls the frequency of the clock signal based on the deviation of the detected data amount from a predetermined value and the time integral value of the deviation.
[0043]
FIG. 4 shows the operating characteristics of the VCO controller 4. The horizontal axis indicates the data amount BDAT of the buffer 1, and the vertical axis indicates the output data DA3 output from the VCO controller 4. BMAX is a data amount of the entire capacity of the buffer 1, and BHLF is a data amount half of the total capacity of the buffer 1.
[0044]
The operating point P0 indicates a state where the input speed of the input data is constant and the data amount is balanced at half the total capacity of the buffer 1 (BHLF-BDAT = 0). The output data DA3 of the VCO controller 4 at this time is output data DA30.
[0045]
Referring to FIG. 4, consider a case where digital data having a short fluctuation and a long fluctuation in input speed is input to digital AV signal processing apparatus 100 including buffer 1.
[0046]
Due to the short fluctuation of the input speed period, the data amount of the buffer 1 starts to increase, and the first control means 5 having a small time constant reacts. The value of the output data DA1 of the first control means 5 increases and the operating point moves from P0 to P1. The VCO controller 4 generates the output data DA31 and increases the clock frequency, so that the VCO controller 4 once enters the equilibrium state with the data amount BDAT1.
[0047]
Thereafter, the value of the output data DA2 of the second control means 7 having a large time constant gradually rises from the output data DA20, and shifts to P2, which is a direction to reduce the data amount deviation (BHLF-BDAT). When the deviation (BHLF−BDAT) of the data amount is reduced, the absolute value of the value of the output data DA1 of the first control means 5 is also attenuated. As a result, there is no change in the value of the output data DA3 and the translation is from P1 to P2.
[0048]
FIG. 5 shows fluctuations in the data amount of the buffer 1 when digital data having the characteristics shown in FIG. 14 is input to the digital AV signal processing apparatus 100 including the buffer 1. The horizontal axis indicates time. The vertical axis represents the data amount BDAT of the buffer 1. Times t1, t2, t3, t4, t5, t6, t7, and t8 correspond to times t1, t2, t3, t4, t5, t6, t7, and t8 in FIG.
[0049]
FIG. 6 shows fluctuations in the frequency of the recovered clock signal generated by the VCO 3 when digital data having the characteristics shown in FIG. 14 is input to the digital AV signal processing apparatus 100 including the buffer 1. The horizontal axis indicates time. The vertical axis indicates the frequency of the recovered clock signal generated by the VCO 3. Times t1, t2, t3, t4, t5, t6, t7, and t8 correspond to times t1, t2, t3, t4, t5, t6, t7, and t8 in FIG.
[0050]
From the comparison between FIG. 5 and FIG. 15 and the comparison between FIG. 6 and FIG. 16, the digital AV signal processing apparatus 100 can perform the conventional digital AV signal processing while ensuring the stability of the reproduction clock to the same level as the conventional example. As compared with the apparatus 300, it can be seen that the deviation from the predetermined value of the data amount of the buffer caused by the long fluctuation of the input speed cycle of the input digital data is extremely small.
[0051]
In the embodiment of the present invention, all the components of the VCO controller 4 are realized by microcomputer software. Since the processing load is extremely light, the microcomputer to be used does not need to be a dedicated microcomputer, and is realized by using a part of the processing capability of the system microcomputer to control the entire device.
[0052]
It is not essential that the digital AV signal processing apparatus 100 includes the DA converter 2. The digital data output from the digital AV signal processing apparatus 100 may be output to a speaker system with a built-in DA converter.
[0053]
The data amount of the buffer 1 is desirably about half of the total capacity of the buffer 1 in order to efficiently prevent buffer overflow and underflow. Therefore, the reference data memory 13 is set to store a data amount that is half the total capacity of the buffer 1. However, the amount of data stored in the reference data memory 13 may be substantially half of the total capacity of the buffer. This is because even in this case, buffer overflow and underflow can be efficiently prevented.
[0054]
According to the digital AV signal processing apparatus 100 of the embodiment of the present invention, the frequency of the clock signal is based on the deviation from the predetermined value of the data amount of the digital data stored in the buffer and the time integral value of the deviation. To control.
[0055]
When the deviation of the data amount of the digital data stored in the buffer from the predetermined value suddenly increases, the voltage controlled oscillator controller determines the predetermined value of the data amount of the digital data stored in the buffer. The frequency of the clock signal can be quickly controlled based on the deviation from. Therefore, when the input speed of the input digital data is accompanied by a short cycle variation, the data amount of the digital data stored in the buffer can be controlled to a predetermined value.
[0056]
When the amount of digital data stored in the buffer becomes constant when it is deviated from a predetermined value, the deviation time integral value increases with time, so the frequency value of the clock signal is constant. Never stay. Therefore, when the input speed of the input digital data is accompanied by a fluctuation with a long period, the data amount of the digital data stored in the buffer can be controlled to a predetermined value.
[0057]
(Use of comparators with non-linear operating characteristics)
In the present invention, it is not essential that the operation characteristics of the first comparator 6 and the second comparator 8 are linear.
[0058]
Operation of at least one of the first comparator 6 and the second comparator 8 when the deviation between the data amount BDAT of the buffer 1 and the data amount BHLF which is half the total capacity of the buffer exceeds a predetermined value You may comprise so that a characteristic may become steeper. Further, the operating characteristic of at least one of the first comparator 6 and the second comparator 8 may be a curve.
[0059]
FIG. 7 shows another operational characteristic of the first comparator 6. The horizontal axis represents the data amount BDAT of the buffer 1, and the vertical axis represents the output data DA1 output from the first comparator 6. BMAX is a data amount of the entire capacity of the buffer 1, and BHLF is a data amount half of the total capacity of the buffer 1. The operation characteristic of the first comparator 6 is set to a straight line passing through the point (BHLF, 0) with the gradient K10 when the data amount BDAT is the data amount BDAT1 to BDAT2. The operation characteristic of the first comparator 6 is set to a straight line with a gradient K11 when the data amount BDAT is the data amounts BDAT2 to BMAX. The operation characteristic of the first comparator 6 is set to a straight line having a gradient K12 when the data amount BDAT is 0 to BDAT1.
[0060]
The gradient K11 is greater than the gradient K10. The gradient K12 is greater than the gradient K10.
[0061]
When the comparator 6 is designed to have the operation characteristics shown in FIG. 7, even if a short fluctuation in the cycle of the input speed of the digital data input to the buffer 1 occurs, the underflow and overflow of the buffer 1 are effective. Can be prevented.
[0062]
For example, overflow or underflow can be prevented even when the data amount BDAT decreases due to abnormal jitter or the like and moves to an operating point with a data amount equal to or less than the data amount BDAT1.
[0063]
FIG. 8 shows another operational characteristic of the second comparator 8. The horizontal axis represents the data amount BDAT of the buffer 1, and the vertical axis represents the output data DA0 output from the second comparator 8. BMAX is a data amount of the entire capacity of the buffer 1, and BHLF is a data amount half of the total capacity of the buffer 1. The operation characteristic of the second comparator 8 is set to a straight line passing through the point (BHLF, 0) with the gradient K20 when the data amount BDAT is the data amount BDAT1 to BDAT2. The operation characteristic of the second comparator 8 is set to a straight line with a gradient K21 when the data amount BDAT is the data amounts BDAT2 to BMAX. The operation characteristic of the second comparator 8 is set to a straight line with a gradient K22 when the data amount BDAT is 0 to BDAT1.
[0064]
The gradient K21 is larger than the gradient K20. The gradient K22 is greater than the gradient K20. When the comparator 8 is designed so as to have the operating characteristics shown in FIG. 8, even if a fluctuation in the cycle of the input speed of the digital data input to the buffer 1 occurs, the underflow and overflow of the buffer 1 are effective. Can be prevented.
[0065]
Further, when the data amount BDAT in the buffer 1 is greatly deviated from the data amount BHLF which is half the total capacity of the buffer 1, the time interval of the second control unit 7 is shortened by changing the control interval of the second control unit 7. May be.
[0066]
As described above, according to the digital AV signal processing device of the embodiment of the present invention, the ratio of the change in the frequency of the clock signal to the amount of change in the deviation when the deviation is larger than the certain range is smaller than the certain range. It is set to be larger than the rate of change in the frequency of the clock signal with respect to the amount of change in the deviation. Therefore, buffer overflow and underflow can be efficiently prevented.
[0067]
(Use of ring buffer)
In the configuration of the digital AV signal processing apparatus 100, the buffer 1 may be the ring buffer 21. Hereinafter, the digital AV signal processing apparatus 100 including the ring buffer 21 will be described.
[0068]
FIG. 9 shows the concept of the ring buffer. The amount of data from the read position RP to the write position WP in the traveling direction indicated by the arrow A is the data amount (unread data amount) stored in the ring buffer 21. The amount of data from the writing position WP to the reading position RP in the traveling direction indicated by the arrow B is the amount of output digital data already output to the DA converter 2. The data from the writing position WP to the reading position RP, proceeding in the traveling direction indicated by the arrow B, is rewritten to the newly received digital data.
[0069]
Digital data input to the digital AV signal processing apparatus 100 is input to the ring buffer 21 at the data write position WP of the ring buffer 21. The ring buffer 21 outputs digital data at the data reading position RP in the ring buffer 21.
[0070]
The VCO controller 4 calculates the amount of digital data stored in the ring buffer 21 based on the data read position RP and the data write position WP. When the data amount becomes larger than a predetermined value larger than the data amount BHLF or when the data amount becomes smaller than a predetermined value smaller than the data amount BHLF, the VCO controller 4 At least one of the write positions WP is changed.
[0071]
When a large input delay occurs in the data input to the ring buffer 21, the read position RP catches up with the write position WP, causing an underflow. When a large amount of data that has been delayed due to the input delay is input to the ring buffer 21, the write position WP catches up with the read position RP, and overflow occurs.
[0072]
However, the VCO controller 4 changes at least one of the write position WP and the read position RP so that the write position WP cannot catch up with the read position RP and the read position RP does not catch up with the write position WP. Therefore, overflow and underflow of the ring buffer 21 can be prevented. Furthermore, in the case of underflow, the past data written in the ring buffer 21 is automatically transmitted, so there is no instantaneous interruption of sound, and the reproduced sound is the immediately preceding data, so that it is correlated with the current data. It has the advantage of being able to reproduce a sound that is high and natural.
[0073]
When the VCO controller 4 changes at least one of the data read position RP and the data write position WP, the VCO controller 4 has at least the write position WP and the read position RP so that the data amount is substantially half of the total capacity of the buffer 1. It is desirable to change one.
[0074]
(When digital data is in packet form)
Hereinafter, a case where the digital data input to the digital AV signal processing apparatus 100 is in the form of a plurality of packets will be described.
[0075]
FIG. 10 shows the time variation of the data amount of the buffer 1 when the digital data input to the digital AV signal processing apparatus 100 is in the form of a packet. The horizontal axis indicates time. The vertical axis represents the data amount BDAT of the buffer 1. BMAX is a data amount of the entire capacity of the buffer 1, and BHLF is a data amount half of the total capacity of the buffer 1.
[0076]
Each time a packet arrives, new data in the packet is stored in buffer 1 and then the amount of data in buffer 1 decreases uniformly until the next packet is received. As described above, when the digital data input to the digital AV signal processing apparatus 100 is in the form of a packet, the data amount BDAT in the buffer 1 increases or decreases in a sawtooth shape even when there is no jitter. Therefore, the VCO controller 4 is set so as to detect the data amount of the buffer 1 in synchronization with the timing when the packet is input. Furthermore, the total capacity BMAX of the buffer 1 should be sufficiently larger than the packet size. For example, the total capacity BMAX of the buffer 1 is more than twice the packet size.
[0077]
As shown in FIG. 10, the VCO controller 4 can detect an accurate data amount by reading the data amount at times t1, t2, t3,... In synchronization with the timing at which a packet is input. .
[0078]
As shown below, even when the digital data input to the digital AV signal processing apparatus 100 is divided into packets having different packet sizes, the data amount is read out in synchronization with the input timing of the packet. The VCO controller 4 can detect the accurate data amount of the buffer 1.
[0079]
FIG. 11 shows temporal variations in the data amount of the buffer 1 when the digital data input to the digital AV signal processing apparatus 100 is in the form of a packet that is divided so that the packet size is different. The horizontal axis indicates time. The vertical axis represents the data amount BDAT of the buffer 1. BMAX is a data amount of the entire capacity of the buffer 1, and BHLF is a data amount half of the total capacity of the buffer 1.
[0080]
When transmitting an IEC958 audio signal (sampling frequency: 48 kHz, transfer rate: 1.536 Mbps) via a universal serial bus (Universal Serial Bus, hereinafter referred to as “USB”), the USB has a 1 msec packet configuration. A 192-byte packet may be sent every 1 msec.
[0081]
On the other hand, when another IEC958 audio signal (sampling frequency: 44.1 kHz, transfer rate: 1.4112 Mbps) is packet-transmitted via USB, the USB has a 1-msec packet structure, so 1764 bytes cut out at 10 msec. It is necessary to divide the fixed length data unit into 10 element packets, for example, 9 176-byte packets and 1 180-byte packet.
[0082]
FIG. 11 shows the time variation of the data amount of the buffer 1 when this signal (sampling frequency is 44.1 kHz, transfer rate is 1.4112 Mbps).
[0083]
In this transmission mode, when the data amount is read at the input timing of the element packet, it can be seen that the data size of the buffer cannot be detected because the packet sizes are not uniform.
[0084]
In order to easily detect the correct amount of data, if the amount of data is detected in synchronization with the input timing of the packet group (10 element packets of 9 176 byte packets and 1 180 byte packet), The amount of data can be accurately grasped.
[0085]
In this way, digital data is input to the digital AV signal processing apparatus 100 in the form of a plurality of packet groups, and each of the plurality of packet groups includes nine first packets having a first data amount (176 bytes) and When one second packet having the second data amount (180 bytes) is composed of a plurality of packets arranged in a predetermined order, the VCO controller 4 receives the plurality of packet groups as the buffer data amount. Detect in sync with timing.
[0086]
As described above, when the digital data input to the digital AV signal processing apparatus 100 is in the form of a packet, the data amount BDAT in the buffer 1 increases or decreases in a sawtooth shape even when there is no jitter. Therefore, the VCO controller 4 included in the digital AV signal processing apparatus 100 can detect the accurate data amount of the buffer 1 by reading the data amount in synchronization with the timing at which the packet is input.
[0087]
【The invention's effect】
According to the digital AV signal processing apparatus of the present invention, the frequency of the clock signal is controlled based on the deviation from the predetermined value of the data amount of the digital data stored in the buffer and the time integral value of the deviation.
[0088]
When the deviation of the data amount of the digital data stored in the buffer from the predetermined value suddenly increases, the voltage controlled oscillator controller determines the predetermined value of the data amount of the digital data stored in the buffer. The frequency of the clock signal can be quickly controlled based on the deviation from. Therefore, when the input speed of the input digital data is accompanied by a short cycle variation, the data amount of the digital data stored in the buffer can be controlled to a predetermined value.
[0089]
When the amount of digital data stored in the buffer becomes constant when it is deviated from a predetermined value, the deviation time integral value increases with time, so the frequency value of the clock signal is constant. Never stay. Therefore, when the input speed of the input digital data is accompanied by a fluctuation with a long period, the data amount of the digital data stored in the buffer can be controlled to a predetermined value.
[0090]
Furthermore, according to the digital AV signal processing device of the present invention, the ratio of the change in the frequency of the clock signal to the amount of change in the deviation when the deviation is larger than the certain range corresponds to the amount of change in the deviation when the deviation is smaller than the certain range. It is set to be larger than the rate of change in the frequency of the clock signal. Therefore, buffer overflow and underflow can be efficiently prevented.
[0091]
Furthermore, according to the digital AV signal processing device of the present invention, it is possible to change at least one of the write position WP and the read position RP by using a ring buffer as a buffer. Therefore, overflow and underflow of the ring buffer can be prevented.
[0092]
Furthermore, according to the digital AV signal processing device of the present invention, even when the digital data input to the digital AV signal processing device is in a packet state, the data amount of the buffer is detected in synchronization with the timing at which the packet is input. Therefore, it is possible to detect an accurate buffer data amount.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a digital AV signal processing apparatus 100 according to an embodiment of the present invention.
FIG. 2 is a diagram showing operating characteristics of the first comparator 6;
FIG. 3 is a diagram showing operating characteristics of the second comparator 8;
FIG. 4 is a diagram showing operating characteristics of the VCO controller 4
FIG. 5 is a diagram showing fluctuations in the data amount of the buffer 1 when digital data having the characteristics shown in FIG. 14 is input to the digital AV signal processing apparatus 100 including the buffer 1;
6 is a diagram showing frequency fluctuation of a reproduction clock signal generated by the VCO 3 when digital data having the characteristics shown in FIG. 14 is input to the digital AV signal processing apparatus 100 including the buffer 1. FIG.
FIG. 7 is a diagram showing another operating characteristic of the first comparator 6;
FIG. 8 is a diagram showing another operating characteristic of the second comparator 8;
FIG. 9 is a diagram showing the concept of a ring buffer
FIG. 10 is a diagram showing temporal variation of the data amount of the buffer 1 when the digital data input to the digital AV signal processing apparatus 100 is in a packet state.
FIG. 11 is a diagram showing temporal variation of the data amount of the buffer 1 when the digital data input to the digital AV signal processing apparatus 100 is in a packet state where the data is divided so that the packet sizes are different.
12 is a diagram showing a configuration of a conventional digital AV signal processing apparatus 300. FIG.
FIG. 13 is a diagram showing operating characteristics of the comparator 35;
FIG. 14 is a diagram showing a change over time in the input speed of digital data input to the digital AV signal processing apparatus 300;
15 is a diagram showing the data amount of the buffer 31 when digital data is input to the digital AV signal processing device 300 at the input speed shown in FIG.
16 is a diagram showing the frequency of a regenerated clock signal generated by the VCO 33 when digital data is input to the digital AV signal processing device 300 at the input speed shown in FIG.
[Explanation of symbols]
1 buffer
2 DA converter
3 VCO
4 VCO controller
5 First control means
6 First comparator
7 Second control means
8 Second comparator
9 Integrator
10 First hold means
11 Adder
12 Second hold means
13 Reference data volume memory
100 Digital AV signal processor

Claims (6)

A buffer for storing digital data input to the digital AV signal processing device, and outputting the digital data as output digital data;
A DA converter for converting the output digital data into analog data;
A voltage controlled oscillator that generates a clock signal for controlling the conversion speed of the DA converter;
The amount of the digital data stored in the buffer is detected, and the frequency of the clock signal is determined based on a deviation of the detected data amount from a predetermined first value and a time integral value of the deviation. A digital AV signal processing device comprising a voltage-controlled oscillator controller for controlling the signal. The voltage-controlled oscillator controller is configured such that a rate of change of the frequency of the clock signal with respect to a change amount of the deviation when the deviation is larger than a certain range is a variation amount of the deviation when the deviation is smaller than the certain range. 2. The digital AV signal processing device according to claim 1, wherein the frequency of the clock signal is controlled to be larger than a rate of change of the frequency of the clock signal with respect to 1. The buffer is a ring buffer;
The digital data input to the digital AV signal processing device is input to the ring buffer at a data write position of the ring buffer;
The ring buffer outputs the digital data at a data read position in the ring buffer;
The voltage-controlled oscillator controller calculates the data amount of the digital data stored in the ring buffer based on the data read position and the data write position,
The voltage-controlled oscillator controller has a predetermined value when the data amount becomes larger than a predetermined second value larger than the predetermined first value or when the data amount is smaller than the predetermined first value. The digital AV signal processing device according to claim 1, wherein at least one of the data reading position and the data writing position is changed when the value becomes smaller than the third value. The voltage-controlled oscillator controller changes at least one of the data read position and the data write position so that the changed data amount is substantially half the capacity of the ring buffer. The digital AV signal processing device described. The digital data is input to a digital AV signal processing device in the form of a plurality of packets,
The digital AV signal processing apparatus according to claim 1, wherein the voltage-controlled oscillator controller detects the data amount of the buffer in synchronization with a timing at which the plurality of packets are input. The digital data is input to the digital AV signal processing apparatus in the form of a plurality of packet groups, and each of the plurality of packet groups has a predetermined number of first packets and a second data amount having a first data amount. A predetermined number of second packets having a plurality of packets arranged in a predetermined order;
The digital AV signal processing apparatus according to claim 1, wherein the voltage-controlled oscillator controller detects the data amount of the buffer in synchronization with a timing at which the plurality of packet groups are input.

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