JP4634153B2 - Magnetic random access memory and data read method thereof - Google Patents

Description

  The present invention relates to a semiconductor memory device, and more specifically, a reference cell capable of holding an intermediate resistance value between a high resistance value and a low resistance value of an MTJ layer in accordance with a resistance change of an MTJ (Magnetic Tunneling Junction) layer due to an applied voltage. The present invention relates to a magnetic random access memory (hereinafter referred to as “MRAM”) and a data reading method thereof.

The resistance value of the MTJ layer of the memory cell of the MRAM varies depending on the magnetization direction of the free magnetic film. When the magnetization direction of the free magnetic film is the same as the magnetization direction of the lower magnetic film provided under the tunneling film, the MTJ layer has a low resistance value R _L and is not the same. In some cases, it has a high resistance value R _H. In the following description, the “maximum resistance value” of the MTJ layer indicates the high resistance value R _H , and the “minimum resistance value” indicates the low resistance value R _L.

The MRAM is a memory device that stores data 1 and 0 by utilizing the fact that the resistance value of the MTJ layer varies depending on the magnetization state of the free magnetic film. Therefore, in order to read data recorded in the memory cell, a resistance value (hereinafter, intermediate resistance value) (R _H + R _L ) / 2 corresponding to the middle of the high resistance value R _H and the low resistance value R _L of the MTJ layer. Is provided in the MRAM. The reference cell includes a transistor and an MTJ layer connected to the transistor. The intermediate resistance value of the reference cell is the resistance value of the MTJ layer provided in the reference cell.

On the other hand, the resistance values R _H and R _L of the MTJ layer vary depending on the voltage applied to the MTJ layer. Therefore, as shown in FIG. 1, the resistance value (solid line) of the MTJ layer provided in the reference cell of the MRAM is also reduced by the low resistance value R _L ( The intermediate value (R _H + R _L ) / 2 between (1) and the high resistance value R _H (●) must always be maintained.

  However, the reference cell provided in the conventional MRAM does not satisfy such a requirement.

  For example, the reference cell of the MRAM according to the prior art includes a first MTJ layer 12, a second MTJ layer 14, a third MTJ layer 16, a fourth MTJ layer 18, and a first transistor 10 as shown on the left side of FIG. Consists of. In FIG. 2, a memory cell configured by the fifth MTJ layer 20 and the second transistor 24 is shown on the right side of the sensor amplifier SA.

  Since the resistance of the MTJ layer is measured, the MTJ layer is shown as a resistance in FIG. Hereinafter, it is assumed that the MTJ layer is displayed as a resistor in all circuit diagrams.

The first MTJ layer 12 and the second MTJ layer 14 each have a high resistance value R _H and a low resistance value R _L , and the third MTJ layer 16 and the fourth MTJ layer 18 each have a low resistance value R _L and a high resistance value R _H. It has. As shown in FIG. 2, the first MTJ layer 12 and the second MTJ layer 14 are connected in series, and the third MTJ layer 16 and the fourth MTJ layer 18 are also connected in series, but the first MTJ layer 12 and the second MTJ layer are connected. 14 and the third MTJ layer 16 and the fourth MTJ layer 18 are connected in parallel. The first transistor 10 is connected between the second MTJ layer 14 and the fourth MTJ layer 18.

As shown in FIG. 2, the same current Is is supplied to the reference cell and the memory cell. In FIG. 2, reference symbols V _Ref and V _Cell indicate voltages measured in the reference cell and the memory cell, respectively. The conventional MRAM including the reference cell and the memory cell as shown in FIG. 2 uses the difference between the voltages V _Ref and V _Cell measured by the sensor amplifier SA at the reference cell and the memory cell, respectively. The information stored in the memory cell is read and read as data.

However, the current Is supplied from the current source to the reference cell is divided into two, and a current of Is / 2 is supplied to the first MTJ layer 12, the second MTJ layer 14, the third MTJ layer 16, and the fourth MTJ layer 18, respectively. As a result, the voltage applied to each MTJ layer of the reference cell is approximately ½ of the voltage applied to the fifth MTJ layer 20 of the memory cell. Therefore, the equivalent resistance value of the reference cell varies as shown in FIG. 3, for example, and it is difficult to always maintain (R _H + R _L ) / 2.

As described above, since the equivalent resistance value of the reference cell cannot always be maintained at (R _H + R _L ) / 2, the voltage V _Ref measured in the reference cell also exhibits characteristics as shown in FIG.

In FIG. 4, the symbol ● indicates a graph showing the voltage V _{Cell, H} measured when the fifth MTJ layer 20 has a high resistance value, and ■ indicates the voltage measured when the fifth MTJ layer 20 has a low resistance value. voltage V _cell, a graph showing _L, and the solid line shows a graph illustrating the voltage V _Ref measured from the reference cell, referring to these graphs, the voltage V _Ref measured from the reference cell ( It can be seen that this is different from V _{Cell, H} + V _{Cell, L} ) / 2.

  As described above, since the voltage measured from the reference cell does not have an intermediate value between the maximum voltage and the minimum voltage measured from the memory cell, the conventional technique including the memory cell and the reference cell shown in FIG. In the case of the MRAM, the sensing margin is reduced and noise is generated, which may cause malfunction.

The reference cell and the memory cell shown in FIG. 5 according to the prior art have the same configuration as the reference cell and the memory cell shown in FIG. 2, but instead of supplying a current, the voltage is changed between the reference cell and the memory cell. The difference is that it is applied to. Therefore, in the case of the MRAM including the reference cell and the memory cell shown in FIG. 5, the information recorded in the memory cell is read using the difference between the current I _Ref measured by the reference cell and the current I _Cell measured by the memory cell. And read the data. However, in the case of the MRAM shown in FIG. 5 as well, in the same manner as in the case of the MRAM shown in FIG. 2, the voltage is applied to each of the first MTJ layer 12, the second MTJ layer 14, the third MTJ layer 16, and the fourth MTJ layer 18 of the reference cell. The voltage is small and is about ½ of the voltage applied to the fifth MTJ layer 20 of the memory cell. Accordingly, it is difficult to always maintain the equivalent resistance value of the reference cell at (R _H + R _L ) / 2, and the current I _Ref measured in the reference cell is also the maximum current value I _{Cell, H} and the minimum current value measured in the memory cell. I _Cell, intermediate value between _{L (I Cell, H + I} Cell, L) / 2 it is difficult to hold the.

Specifically, when the voltage-current characteristics of the MTJ layers provided in the memory cell and the reference cell of the MRAM shown in FIG. 5 are measured, the result is as shown in FIG. In FIG. 6, symbol ● is a graph showing the maximum current value I _{Cell, H} measured in the memory cell, symbol ■ is a graph showing the minimum current value I _{Cell, L} measured in the memory cell, The solid line is a graph showing the current value I _Ref measured in the reference cell. As shown in the graph of FIG. 6, the current value I _Ref measured in the reference cell is an intermediate value between the maximum current value I _{Cell, H} and the minimum current value I _{Cell, L} measured in the memory cell because the applied voltage is different. It can be seen that (I _{Cell, H} + I _{Cell, L} ) / 2 greatly deviates.

  Therefore, in the case of the MRAM including the memory cell and the reference cell shown in FIG. 5, the sensing margin may be reduced and noise may be generated as in the case of the MRAM shown in FIG.

FIG. 7 shows a conventional MRAM in which the reference cell is composed of the sixth MTJ layer 26 and the seventh MTJ layer 28 and the first transistor 10. The sixth MTJ layer 26 has a low resistance value R _L , and the seventh MTJ layer 28 has a higher resistance value R _H than the sixth MTJ layer 26. The sixth MTJ layer 26 and the seventh MTJ layer 28 are connected in parallel, and the first transistor 10 is connected between them. Here, the reference cell has a voltage O.V corresponding to ½ of the voltage Vs supplied to the memory cell. 5Vs is applied.

As described above, in the MRAM shown in FIG. 7, as in the case of the MRAM shown in FIG. 5, the voltage 0.5 Vs applied to the two MTJ layers 26 and 28 of the reference cell is applied to the fifth MTJ layer 20 of the memory cell. Since the voltage is approximately ½ of the applied voltage Vs, it is difficult to maintain (R _H + R _L ) / 2 as the equivalent resistance value of the reference cell. Therefore, the current value I _Ref measured from the reference cell of the MRAM shown in FIG. 7 is also an intermediate value between the maximum current value I _{Cell, H} and the minimum current value I _{Cell, L} measured from the memory cell as shown in FIG. (I _{Cell, H} + I _{Cell, L} ) / 2 cannot be held. For this reason, in the case of the MRAM shown in FIG. 7, the sensing margin is reduced, noise is generated, and malfunction may occur.

The technical problem to be solved by the present invention is to improve the above-mentioned problem. Even if the applied voltage changes, the equivalent resistance value of the MTJ layer of the reference cell is changed to the maximum resistance value of the MTJ layer of the memory cell. The object of the present invention is to provide an MRAM that can always be held at an intermediate value (R _H + R _L ) / 2 between (R _H ) and a minimum resistance value (R _L ).

  Another technical problem to be solved by the present invention is to provide a method for reading data from the MRAM.

  In order to solve the above technical problem, the present invention provides an MRAM including a memory cell including one transistor and one MTJ layer, and a reference cell serving as a reference when data stored in the memory cell is read. The reference cell includes a first MTJ layer and a second MTJ layer connected in parallel, and a first transistor and a second transistor connected in parallel, wherein the first transistor and the second transistor are respectively An MRAM is provided that is connected in series to a first MTJ layer and the second MTJ layer.

  In order to achieve the above technical problem, the present invention also includes a memory cell including one transistor and one MTJ layer, and a reference cell serving as a reference when data stored in the memory cell is read. In the MRAM, the reference cell includes a first MTJ layer and a second MTJ layer connected in parallel, and a first transistor connected in series to the first MTJ layer and the second MTJ layer. An MRAM is provided in which the driving capability is twice that of the memory cell transistor.

  In order to achieve the other technical problem, the present invention provides a memory cell including one transistor and one MTJ layer, and a first MTJ layer and a second MTJ layer connected in parallel. In a method of reading data from an MRAM, comprising: a first transistor and a second transistor, wherein the first transistor and the second transistor each include a reference cell connected in series to the first MTJ layer and the second MTJ layer. A data read method for an MRAM is provided, wherein a predetermined read current Is is supplied to the memory cell, and a current 2Is corresponding to twice the read current is supplied to the reference cell.

  In order to achieve the other technical problem, the present invention also provides a memory cell including one transistor and one MTJ layer, a first MTJ layer and a second MTJ layer connected in parallel, and a series thereof. And a reference cell including a first transistor having a driving capability twice that of the transistor, a predetermined read current Is is supplied to the memory cell, An MRAM data reading method is provided, wherein a current 2Is corresponding to twice the read current is supplied to a reference cell.

  According to the present invention, since the equivalent resistance value of the MTJ layer of the reference cell can always be held at an intermediate value between the maximum resistance value and the minimum resistance value of the MTJ layer of the memory cell even when the applied voltage changes, the sensing margin As a result, malfunction due to noise can be prevented.

  Hereinafter, an MRAM and a data read method thereof according to embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that the thicknesses of the layers and regions shown in the drawings are exaggerated so that the structure can be easily understood, and the actual dimensions are not accurately displayed.

  FIG. 8 is a diagram showing a circuit configuration of an MRAM memory cell and a corresponding first reference cell according to an embodiment of the present invention. As shown in FIG. 8, the first reference cell C <b> 1 includes a first MTJ layer 50 and a second MTJ layer 52, a first transistor 54 and a second transistor 56. The first MTJ layer 50 has a low resistance value, but preferably has the same value as the minimum resistance value of the third MTJ layer 58 included in the memory cell C2. The second MTJ layer 52 of the first reference cell C <b> 1 has a higher resistance value than the first MTJ layer 50. The resistance value of the second MTJ layer 52 is preferably the same as the maximum resistance value of the third MTJ layer 58. The relationship between the first MTJ layer 50 and the second MTJ layer 52 of the first reference cell C1 may be reversed. The first MTJ layer 50 and the second MTJ layer 52 of the first reference cell C1 are connected in parallel, and the first transistor 54 and the second transistor 56 are also connected in parallel. The first MTJ layer 50 and the first transistor 54 are connected in series, and the second MTJ layer 52 and the second transistor 56 are also connected in series. The memory cell C2 includes a third MTJ layer 58 and a third transistor 60. The first transistor 54 and the second transistor 56 of the first reference cell C1 are preferably the same as the third transistor 60 of the memory cell C2.

Data stored in the memory cell C2 supplies a predetermined read current Is from the current source to the memory cell C2, and simultaneously supplies a current 2Is corresponding to twice the read current Is to the first reference cell C1. The voltages V _Ref and V _Cell measured in the first reference cell C1 and the memory cell C2 are compared and read.

At this time, since the two MTJ layers 50 and 52 are connected in parallel in the first reference cell C1 as described above, the current 2Is supplied to the first reference cell C1 is branched and the first MTJ layer 50 and the first MTJ layer 50 and The 2MTJ layer 52 is supplied with the same current as the current Is supplied to the memory cell C2. Further, the first transistor 54 and the second transistor 56 of the memory cell C2, that is, the first transistor 54 and the second transistor 56, which are the same as the third transistor 60, are connected in series to the first MTJ layer 50 and the second MTJ layer 52 of the first reference cell C1, respectively. Therefore, the voltage applied to the first MTJ layer 50 and the second MTJ layer 52 of the first reference cell C1 is substantially the same as the voltage applied to the third MTJ layer 58 of the memory cell C2. Therefore, the equivalent resistance value of the first reference cell C1 is always an intermediate value (R _H) between the maximum resistance value R _H and the minimum resistance value R _L of the third MTJ layer 58 of the memory cell C1 even if the applied voltage changes. + R _L ) / 2 is held. FIG. 9 is a graph showing the voltage-resistance characteristics of the MTJ layer (50, 52, 58), and shows the above-described characteristics of the first reference cell C1.

  In FIG. 9, the symbol ● represents the change in the maximum resistance value of the third MTJ layer 58 of the memory cell C2 with respect to the applied voltage, and the symbol ■ represents the change in the minimum resistance value of the third MTJ layer 58. A solid line indicates a change in resistance value measured in the first reference cell C1.

  Referring to FIG. 9, the resistance value measured from the first reference cell C1 is an intermediate value between the maximum resistance value and the minimum resistance value of the third MTJ layer 58 of the memory cell C2 even when the applied voltage changes. You can see that

In this way, even if the applied voltage changes, the resistance value of the first reference cell C1 holds an intermediate value between the maximum resistance value and the minimum resistance value of the memory cell C2, so that the voltage V _Ref of the first reference cell C1 is also applied. An intermediate value (V _{Cell, H} + V _{Cell, L} ) / 2 between the maximum voltage V _{Cell, H} and the minimum voltage V _{Cell, L} of the memory cell C2 can be held regardless of the change in voltage (current value). FIG. 10 is a graph showing the voltage-current characteristics of the MTJ layer (50, 52, 58), and shows the characteristics as described above.

In FIG. 10, a symbol ● indicates a change in the maximum voltage V _{Cell, H} of the memory cell C2 with respect to a change in the current value. The symbol ■ indicates the change of the minimum voltage V _{Cell, L} of the memory cell C2 with respect to the change of the current value. The solid line shows the voltage change of the first reference cell C1 due to the applied voltage.

Referring to FIG. 10, even if the applied voltage changes and the current value changes, the voltage of the first reference cell C1 is an intermediate value between the maximum voltage V _{Cell, H} and the minimum voltage V _{Cell, L} of the memory cell C2. It can be seen that

  From this result, it can be seen that if the MRAM according to the embodiment of the present invention is used, a sufficient sensing margin can be secured and data can be read (read) stably without malfunction.

  On the other hand, in the first reference cell C1 shown in FIG. 8, the first transistor 54 and the second transistor 56 can be replaced with one transistor to form a reference cell (second reference cell). In this case, the one transistor is a pass transistor. In this case, since the currents passing through the two MTJ layers connected in parallel pass through the one transistor, the driving capability of the one transistor is twice the driving capability of the third transistor 60 of the memory cell C2. It is desirable to be.

  In the case of the MRAM including the second reference cell, the process of reading the stored data from the memory cell C2 is the same as that of the MRAM including the first reference cell C1 described above.

  In the first reference cell C1 shown in FIG. 8, the MTJ layers (first MTJ layer 50, second MTJ layer 52) and transistors (first transistor 54, second transistor 56) connected in series are opposite in position. Good.

  FIG. 11 shows an MRAM cell array including the second reference cells and memory cells. In FIG. 11, reference numeral 100 denotes a reference cell column including a plurality of second reference cells. One reference cell column 100 is provided for each memory cell block. The reference cell column 100 is supplied with a current 2Is that corresponds to twice the current Is supplied to the memory cell column. One column of the memory cell block is selected by the column selection transistors Y0, Y1, Y2, and Y3 in the lower stage of the array and compared with the reference cell column 100. In FIG. 11, a symbol DL is a digit line used when data is recorded in the MTJ layer of the memory cell. When supplying a current to the digit line DL, the ground line GL is floated so that no current flows through the pass transistor connected to the MTJ layer.

  FIG. 12 shows the supply to the memory cell and reference cell column 100 to read data stored in a predetermined selected word line of the MRAM array of FIG. 11, for example, a memory cell connected to the first word line WL0. It is a circuit diagram which shows what kind of path | route the performed electric current flows. In FIG. 12, the left side circuit is supplied with the memory cell of the memory cell column connected to the first word line WL0 to which the read current Is is supplied, and the right side circuit is supplied with the current 2Is corresponding to twice the read current Is. The second reference cell of the reference cell column 100 connected to the first word line WL0 is shown.

  Referring to FIG. 12, since all the remaining word lines excluding the first word line WL0 are in the off state, the read current Is supplied to the memory cells connected to the first word line WL0. Flows through the MTJ layer 102 of the memory cell and the transistor MT1 connected in series to the ground line GL connected to the transistor MT1. The current 2Is supplied to the reference cell column 100 is branched at the first node N1, and the first and second currents I1s and I2s are respectively supplied to the two MTJ layers 106 and 108 connected in parallel. The The first current I1s and the second current I2s have the same value. The first current I1s supplied to the MTJ layer 106 connected to the transistor CT1 flows to the ground line GL through the transistor CT1 in the on state. The second current I2s is a connection point between the MTJ layer 108 connected in series to the off-state transistor CT2 connected to the second node N2, the second word line WL1, and the transistor CT2 and the MTJ layer 108. The current flows to the ground line GL through the third node N3, the fourth node N4 which is a connection point between the transistor CT1 and the MTJ layer 106, and the transistor CT1 connected to the first word line WL0.

  Thus, the current supplied to the second reference cell passes through two MTJ layers 106 and 108 connected in parallel and then passes through one transistor CT1, so that the transistor provided in the second reference cell It is desirable that the drive capability of CT1 is twice that of the transistor MT1 provided in the memory cell.

  In FIG. 12, symbols MT2 and CT2 indicate a memory cell transistor and a second reference cell transistor connected to the second word line WL1, respectively. Reference numeral 104 denotes an MTJ layer of the memory cell connected to the second word line WL1.

As described above, the reference cell of the MRAM according to the present invention includes the MTJ layer having the maximum resistance value of the MTJ layer of the memory cell and the MTJ layer having the minimum resistance value of the MTJ layer of the memory cell in parallel. Two pass transistors connected in series to each MTJ layer and having the same driving capability as the pass transistors of the memory cells are provided. At this time, the two pass transistors provided in the reference cell can be replaced with one pass transistor having twice the driving capability of the pass transistor of the memory element. In the MRAM of the present invention having such a configuration, the same current as that supplied to the MTJ layer of the memory cell is supplied to each MTJ layer of the reference cell. Therefore, the equivalent resistance value measured from the reference cell always has an intermediate value between the maximum resistance value and the minimum resistance value measured from the memory cell. Further, the voltage VRef measured from the reference cell always has an intermediate value between the maximum voltage _{Vcell, H} and the minimum voltage V _{Cell, L} measured from the memory cell even if the applied voltage changes. Therefore, in the case of the MRAM of the present invention, a sufficient sensing margin can be ensured and malfunction due to noise can be prevented.

  Although the embodiments of the present invention have been specifically described in the above description, they are not intended to limit the technical scope of the invention and should be interpreted as examples of desirable embodiments. For example, a person having ordinary knowledge in the technical field to which the present invention belongs may use other types of transistors or have the same configuration as the reference cell included in the MRAM of the present invention. Only the configuration of the MTJ layer may be different. Further, instead of the transistor, other switching means capable of turning on / off current may be used. Therefore, the technical scope of the present invention should not be determined by the above-described embodiments, but should be determined only by the technical ideas described in the claims.

  The present invention can be used in any electronic product in which a semiconductor chip is used. For example, the present invention can be applied to computers, camcorders, digital home appliances, various game machines, data storage media, mobile phones, GPS, PDAs and the like.

3 is a graph illustrating desirable voltage-resistance characteristics of an MTJ layer included in an MRAM memory cell and an MTJ layer included in a reference cell. FIG. 3 is a circuit diagram of a memory cell and a reference cell of an MRAM according to a conventional technique. 3 is a graph showing voltage-resistance characteristics of an MTJ layer provided in the memory cell of the MRAM shown in FIG. 2 and an MTJ layer provided in a reference cell. 3 is a graph showing voltage-current characteristics of an MTJ layer provided in the memory cell of the MRAM shown in FIG. 2 and an MTJ layer provided in a reference cell. FIG. 3 is a circuit diagram of a memory cell and a reference cell of an MRAM according to a conventional technique. 6 is a graph showing voltage-current characteristics of an MTJ layer provided in the memory cell of the MRAM shown in FIG. 5 and an MTJ layer provided in a reference cell. FIG. 3 is a circuit diagram of a memory cell and a reference cell of an MRAM according to a conventional technique. It is a circuit diagram of a memory cell and a reference cell of an MRAM as an embodiment of the present invention. 10 is a graph showing voltage-resistance characteristics of an MTJ layer provided in the memory cell of the MRAM shown in FIG. 8 and an MTJ layer provided in a reference cell. 10 is a graph showing voltage-current characteristics of an MTJ layer provided in the memory cell of the MRAM shown in FIG. 8 and an MTJ layer provided in a reference cell. 1 is a circuit diagram showing an array of memory cells and reference cells of an MRAM as an embodiment of the present invention. FIG. FIG. 12 is a circuit diagram showing a flow of current supplied from the memory cell array shown in FIG. 11 to a memory cell and a corresponding reference cell.

Explanation of symbols

C2 memory cell C1 first reference cell 50 first MTJ layer 52 second MTJ layer 54 first transistor 56 second transistor 58 third MTJ layer 60 third transistor

Claims (3)

In a magnetic random access memory including a memory cell including one transistor and one MTJ layer, and a reference cell serving as a reference when reading data stored in the memory cell,
The reference cell is
A first MTJ layer and a second MTJ layer connected in parallel;
A first transistor connected in series to the first MTJ layer and the second MTJ layer;
The drive capability of the first transistor is twice the drive capability of the transistor of the memory cell. One of the first MTJ layer and the second MTJ layer has a maximum resistance value of the MTJ layer of the memory cell, and the other layer has a minimum resistance value of the MTJ layer of the memory cell. The magnetic random access memory according to claim 1 . A memory cell including one transistor and one MTJ layer;
Magnetic random access memory comprising: a first MTJ layer and a second MTJ layer connected in parallel; and a reference cell including a first transistor connected in series to the first transistor and having a driving capability twice that of the transistor In the data reading method of
A method of reading data from a magnetic random access memory, comprising: supplying a predetermined read current Is to the memory cell and supplying a current 2Is corresponding to twice the read current to the reference cell.

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