JP4637679B2 - Receiving machine - Google Patents

Description

  The present invention relates to a diversity receiver applied to a radio communication system and the like, and more particularly to phase control of a received signal based on a combined output of each received signal received by the diversity receiver. .

  The synthesis of received signals at a receiver, which is a conventional example, will be described with reference to FIGS. FIG. 5 is a block diagram showing a configuration of a diversity combining part of a conventional receiver. Of the received signals received by the respective antennas, the received signal 1 is directly input to the combiner 102, while the received signal 2 is input to the combiner 102 via the variable phase shifter 101. The variable phase shifter 101 is controlled by the phase controller 103 based on the synthesized output of the synthesizer 102 to change the phase of the received signal 2 so that the phase of the received signal 2 matches the phase of the received signal 1. ing. In this example, the case where the phase is delayed will be described. The phase delay amount in the variable phase shifter 101 is determined by the control voltage of the output of the phase controller 103 as shown in FIG. Since the relationship between the control voltage and the phase delay amount is as shown in FIG. 8, the control voltage increases when the phase delay amount of the variable phase shifter 101 is large, while the phase delay amount of the variable phase shifter 101 increases. When it is small, the control voltage is small. For example, when the phase of the received signal 2 is delayed by 1 degree from the phase of the received signal 1, the phase of the received signal 2 must be advanced by 1 degree, which is the same as delaying the phase of the received signal 2 by 359 degrees. Therefore, the control voltage when the phase delay amount is 359 degrees is output to the variable phase shifter 101 so that the phase of the reception signal 2 matches the phase of the reception signal 1. As a known example related to a diversity receiver that synthesizes reception signals received by respective antennas, there is, for example, Patent Document 1 (Japanese Patent Laid-Open No. 2004-112155).

  Next, control of the variable phase shifter 101 by the phase controller 103 will be described with reference to FIG. FIG. 6 is a diagram illustrating a change in control voltage supplied from the phase controller 103 to the variable phase shifter 101 and a change in amplitude of the combined output of the reception signal 1 and the reception signal 2. The upper part is the control voltage level, and the lower part is data indicating the amplitude level of the combined output of the received signal 1 and the received signal 2, that is, data indicating the amplitude level of the combined output of both received signals output from the combiner 102. For convenience of explanation, it is assumed that the upper control voltage change is immediately reflected in the lower amplitude change in the same time slot. In addition, as a control method, control is performed so that the amplitude of the combined output is maximized by changing the phase of the received signal 2 by a certain amount by changing the control voltage by a certain amount for each time slot. . In FIG. 6, the case where the phase of the received signal 1 and the phase of the received signal 2 match in the state of the time slot t3 will be described as an example. During the time slots t1 to t3, the composite amplitude increases as the phase of the received signal 2 is delayed by a certain amount by increasing the control voltage by a certain amount. However, if the phase of the reception signal 2 is delayed by further increasing the control voltage at the time slot t4, the combined amplitude decreases instead of the maximum amplitude because it deviates from the optimum phase. For this reason, by reducing the phase delay amount of the received signal 2 by reducing the control voltage at the time slot t5, the composite amplitude increases again by returning the phase of the received signal 2 to the optimum phase. However, if the phase delay amount of the received signal 2 is reduced by further reducing the control voltage at time slot t6, the combined amplitude decreases instead of the maximum amplitude because it deviates from the optimum phase. For this reason, by increasing the control voltage and increasing the phase delay amount of the received signal 2 at time slot t7, the composite amplitude is increased again by returning the phase of the received signal 2 to the optimum phase. As described above, phase synthesis is performed by changing a constant phase amount for each time slot so that the synthesized amplitude becomes maximum.

Next, another configuration of the variable phase shifter 101 will be described with reference to the block diagram of FIG. In this example, the variable phase shifter 101 uses the vector synthesis phase shifter shown in FIG. This vector synthesizer outputs the received signal 2 without changing the phase of the received signal 2 and outputs it by changing the phase of the received signal 2 by 90 ° and outputs to the respective phase shifters 701. Multipliers 702 and 703 that multiply the obtained coefficients, and a combiner 704 that combines the outputs of the multipliers 702 and 703. If this vector synthesis phase shifter performs control to delay the received signal by the phase amount θ, the output I of the phase shifter 701 is multiplied by the cos θ given to the multiplier 702 as a coefficient. It is possible to delay the output Q by a phase amount θ by applying sin θ as a coefficient to the multiplier 703 and multiplying the output Q, and then synthesizing.
JP 2004-112155 A

  In the above-described conventional receiver, for example, in the vector synthesis phase shifter of FIG. 7, sufficient accuracy may not be ensured in each element, and reception quality may be deteriorated or the apparatus may be expensive, causing problems in practical use. . Further, as shown in FIG. 8, the level (for example, control voltage) of the control signal output to the variable phase shifter when the amplitude of the combined output of the received signal is maximum is near 0 (for example, near 0 V) or the maximum. When the level is near the level (for example, when the maximum value of the control voltage is 12V, it is near 12V), the level of the control signal is changed because the level of the control signal is changed for each time slot as described above. The maximum level may change from 0 to 0, and the level of the control signal may change from 0 to the maximum level. When the level of the control signal changes from the maximum level to 0, for example, when a voltage-controlled phase shifter is used for the phase shifter, if the phase shifter changes over time or changes in temperature, the control signal level When the relationship with the phase delay amount changes, the phase delay amount of the phase shifter may not become 0 degrees. If the phase delay amount of the phase shifter does not become 0 degree, the phase of the phase-delayed received signal may not be matched with the phase of the other received signal. In this case, the combined output level of the received signal This causes a problem of lowering. Similarly, when the level of the control signal changes from 0 to the maximum level, a problem that the combined output level of the received signal decreases similarly occurs. Further, even when the level of the control signal changes to near 0 or near the maximum level, the problem that the combined output level of the received signal decreases similarly occurs.

  Therefore, in the present invention, even if the relationship between the level of the control signal and the amount of phase delay changes due to the aging and temperature change of the phase shifter, it is possible to suppress the phase shift of the received signal to be synthesized. An object is to provide a receiver that can be used.

  In order to achieve the above object, the present invention provides a phase shifter for delaying the phase of at least one received signal among a plurality of received signals received by a diversity method, and reception delayed in phase by the phase shifter. In a receiver including a combiner that combines a signal with another received signal and a phase controller that controls the phase shifter based on the output of the combiner, the phase delay amount of the received signal at the phase shifter When the phase delay amount is outside a predetermined range (for example, near 0 degrees or near 360 degrees), the phase controller outputs a control signal of a level corresponding to the above to the phase shifter. Therefore, the amount of change in the level of the corresponding control signal is controlled to be smaller than that in the vicinity of other than 0 degrees and other than 360 degrees.

  More specifically, a storage unit having a data table of a relationship between the level of the control signal and the phase delay amount used when outputting the control signal of a level corresponding to the phase delay amount to the phase shifter is provided in the phase The data table provided for the controller is a data table set such that when the phase delay amount is outside the predetermined range, the amount of change in the level of the corresponding control signal is smaller than when the phase delay amount is within the predetermined range. It is what.

  According to the present invention, when the relationship between the level of the control signal and the phase delay amount changes due to the aging and temperature change of the phase shifter, the phase delay amount is near 0 degrees or near 360 degrees, that is, the control When the signal level is near 0 or near the maximum level, the change in the phase delay amount with respect to the change in the control signal level becomes small, so that the phase delay amount with respect to the change in the control signal level due to aging and temperature change can be reduced. Even if it changes, the amount of change can be kept small. As a result, it is possible to reduce a shift in phase delay amount, and thus it is possible to provide a receiver that can suppress a shift in phase of received signals to be combined.

  Hereinafter, a receiver according to an embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram showing the configuration of the diversity combining portion of the receiver of this embodiment. Note that the receiver of the present embodiment is different from the conventional receiver only in the phase controller 103 ′, and therefore detailed description of the configuration of the receiver is omitted. The phase control unit 103 ′ of the receiver according to the present embodiment will be described. The phase control unit 103 ′ includes a storage unit 104 and a phase delay control unit 105. The phase delay amount control unit 105 uses the data table of the relationship between the control voltage and the phase delay amount stored in the storage unit 104, so that the variable phase shift is performed so that the amplitude of the combined output from the combiner 102 is maximized. The control voltage supplied to the device 101 is output. The variable phase shifter 101 is a voltage control type phase shifter. When the phase of the received signal 2 is delayed by a predetermined amount by the control voltage from the phase delay amount control unit 105, the amplitude of the combined output from the combiner 102 varies. Based on this variation, the phase delay amount control unit 105 controls the amplitude of the synthesized output from the synthesizer 102 to be maximized by raising and lowering the level of the control voltage.

  Next, a data table of the relationship between the control voltage and the phase delay amount stored in the storage unit 104 will be described with reference to FIG. FIG. 2 is a diagram illustrating the relationship between the control voltage and the phase delay amount in the data table stored in the storage unit 106. As shown in FIG. 2, the slope of the graph differs depending on the control voltage, and the slope of the graph is set to 8 degrees / V when the control voltage is near 0 V (for example, 0 to 3 V) or near 12 V (for example, 10 to 12 V). On the other hand, the slope of the graph is set to about 45.7 degrees / V when the control voltage is not near 0 V and other than around 12 V (for example, 3 to 10 V). That is, when the control voltage is near 0V or near 12V, the amount of change in the phase delay when the control voltage changes by a predetermined amount is set smaller than when the control voltage is not near 0V and other than 12V. ing.

  Next, the operation of the receiver of this embodiment having this setting data table will be described. In the receiver of this embodiment, the phase controller 103 ′ also changes the phase delay amount of the received signal 2 by changing the control voltage level by a fixed amount for each time slot based on the output of the combiner 102, and synthesizes it. Control is performed so that the output amplitude becomes maximum. That is, if the amplitude of the composite output increases and reaches the peak value due to the increase in the control voltage level, but the composite output amplitude decreases because the control voltage level further increases, the control voltage level is decreased. Control to return to the peak value. Conversely, if the amplitude of the composite output increases and reaches the peak value due to the decrease in the control voltage level, but the amplitude of the composite output decreases because the control voltage level further decreases, the control voltage level should be increased. To control to return to the peak value. Here, in this embodiment, by having the data table shown in FIG. 2, when the control voltage when the amplitude of the combined output reaches the peak value is near 0V or 12V, it is not near 0V and 12V. The variable phase shifter 101 is controlled so that the amount of change in the phase delay of the received signal 2 with respect to the change in the control voltage is smaller than when it is other than the vicinity. Therefore, even if the relationship between the control voltage and the phase delay amount changes due to aging and temperature change of the variable phase shifter 101, in the receiver of this embodiment, when the control voltage is near 0V or 12V, By making the change amount of the phase delay amount of the received signal with respect to the change small, the change amount of the phase delay amount with respect to the control voltage due to the secular change and temperature change of the variable phase shifter 101 can be suppressed to be small. As a result, the shift of the phase delay amount due to aging and temperature change can be reduced, so that the reduction in the combined output level of the received signal can be suppressed.

  In the receiver of the present embodiment, the case where the variable phase shifter that performs phase delay in the range of 0 to 360 degrees is controlled by the phase controller has been described, but the present invention is not limited to this. For example, as shown in FIG. 3, 180 degree variable phase shifters 301 and 302 that perform phase delay in a range of 0 to 180 degrees are provided, and a storage unit 304 and a phase delay amount control unit 305 are provided in the phase control unit 303. It is good also as a receiver of the composition provided. In the receiver having this configuration, the phase delay amount control unit 305 uses the data table of the relationship between the control voltage and the phase delay amount stored in the storage unit 304, so that the amplitude of the combined output from the combiner 102 is maximized. The phase control unit 303 controls the 180 degree variable phase shifters 301 and 302 by outputting the control voltage supplied to the 180 degree variable phase shifters 301 and 302 so that Since the phase is delayed by the two variable phase shifters (180-degree variable phase shifters 301 and 302), the data table of the storage unit 304 is changed as shown in FIG. 4 in comparison with the data table of FIG. Is set so that the change of the phase delay amount with respect to is small. That is, the inclination of the graph of FIG. 4 is set to be gentler than the inclination of the graph of FIG. For example, while the slope of the graph is set to 4 degrees / V when the control voltage is near 0 V (for example, 0 to 3 V) or near 12 V (for example, 10 to 12 V), the control voltage is other than near 0 V. In addition, the slope of the graph other than the vicinity of 12 V (for example, 3 to 10 V) is set to about 22.9 degrees / V. The slope of the graph when the control voltage is near 0 V (for example, 0 to 3 V) or near 12 V (for example, 10 to 12 V) is when the control voltage is other than near 0 V and near 12 V (for example, 3 to 10 V). By setting it to be smaller than the slope of the graph, the amount of phase delay deviation of the 180-degree variable phase shifters 301 and 302 can be reduced even when aging and temperature change occur. As a result, since the phase difference between the phase-delayed received signal and the other received signal is reduced, it is possible to suppress a decrease in the combined output level of the received signal.

  Further, even when there are three or more variable phase shifters (when there are three variable phase shifters, a 120-degree variable phase shifter is used), even if aging and temperature changes occur in the same manner. Since the phase difference between the phase-delayed received signal and the other received signal becomes small, it is possible to suppress a decrease in the combined output level of the received signal.

The block diagram which shows the structure of the diversity synthetic | combination part of the receiver which is one Example of this invention. The figure which shows the relationship between the control voltage supplied to a variable phase shifter, and the phase delay amount of a received signal with the receiver which is one Example of this invention. The block diagram which shows the structure of the diversity synthetic | combination part of the receiver which is one Example of this invention. The figure which shows the relationship between the control voltage supplied to a variable phase shifter, and the phase delay amount of a received signal with the receiver which is one Example of this invention. The block diagram which shows the structure of the diversity part of the receiver which is an example of the past. The figure which shows the control voltage change when the variable phase shifter is controlled by the phase controller in the receiver which is a conventional example, and the amplitude change of the composite output of both received signals. The block diagram which shows the structure of the variable phase shifter of the receiver which is an example of the past. The figure which shows the relationship between the control voltage supplied to a variable phase shifter, and the phase delay amount of a received signal with the receiver which is a conventional example.

Explanation of symbols

1, 2: Received signal 101: Variable phase shifter 102: Synthesizer 103, 103 ': Phase controller 104: Storage unit 105: Phase delay amount control unit 301, 302: 180 degree variable phase shifter 303: Phase control unit 304: Storage unit 305: Phase delay amount control unit 701: Phase shifter 702, 703: Multiplier 704: Synthesizer

Claims (2)

A phase shifter that delays the phase of at least one received signal among a plurality of received signals received by the diversity method; and a combiner that combines the received signal delayed in phase by the phase shifter with another received signal; A receiver including a phase controller that controls the phase shifter based on the output of the combiner;
The said phase controller the level control signal is output to the phase shifter corresponding to the phase delay amount of the received signal at the phase shifter, than when in the intermediate value of the control voltage of the phase controller, the The control signal is output so that the change amount of the phase delay amount of the received signal at the phase shifter corresponding to the control signal change amount becomes smaller near the minimum value and the maximum value of the control voltage of the phase controller. A receiver characterized by being a phase controller . The receiver of claim 1, wherein
The phase controller includes a storage unit having a data table of a relationship between the level of the control signal and the phase delay amount used when the control signal having a level corresponding to the phase delay amount is output to the phase shifter. In the data table, the shift corresponding to the control signal change amount is closer to the minimum value and the maximum value of the control voltage of the phase controller than to the intermediate value of the control voltage of the phase controller. A receiver characterized by being a data table set so that a change amount of a phase delay amount of a received signal in a phase shifter becomes small.