JP4640251B2 - Input control device - Google Patents

Description

  The present invention relates to an input control device that holds an input signal before an abnormality occurs when the input signal is abnormal, and more particularly to an input that can be used to realize a suitable input signal hold for an input control device of a process control device. The present invention relates to a control device.

  In various process controls including a plant, predetermined control data is set in advance for an input signal from the plant side, and various devices of the plant are controlled based on this. For this reason, if an abnormal input signal is input to the control system, there is a possibility that the operation of the plant must be stopped. Therefore, in order to always detect an abnormality in the input signal input from the plant side, in the technical field of the input control module that monitors the input signal, the input signal is input through two circuits, and one of them is a process value (hereinafter referred to as a process value). In general, it is used as a “PV value”) on the control computer side and the other is monitored as a diagnostic system. That is, when the diagnosis system detects an input abnormality, the PV value input to the computer side is held, and the computer side as the output destination is prevented from being updated to this abnormal PV value. (Hereinafter, an input control module having a mechanism for holding a PV value when an abnormal PV value is detected is referred to as an “input control device”).

  The conventional input control devices 50, 60, and 70 will be described with reference to FIGS. In addition, in the following description, what has the same function attaches | subjects and demonstrates the same code | symbol.

  In the input control device 50 shown in FIG. 6, the input signals are divided into two systems and input. One is input separately from the main circuit 1 and the other is input from the sub circuit 2. Input signals are input from the two systems of the main circuit 1 and the sub circuit 2 to the computer side, and the input on the main circuit 1 side is normally used as the PV value. That is, on the computer side, the PV value sent at a predetermined cycle is stored in a memory (not shown), and the stored PV value is updated as needed to be used for plant control. . On the other hand, the input signal acquired from the sub-circuit 2 side is compared with the PV value and used as a diagnostic system for diagnosing whether or not the input signal is abnormal.

  The comparator 3 is a comparator that receives the input signals output from the main circuit 1 and the sub circuit 2 and compares the voltage values of both input signals. When the values of both input signals are compared and the difference changes to a predetermined threshold value or more, a status signal is output to the filter circuit 4. The filter circuit 4 includes a timer, and when a status signal output from the comparator 3 is continuously detected for a predetermined time, an error status flag (fail signal) is output to the computer side. On the computer side, when this error status flag is detected, a failure of the input control device 50 can be determined (diagnosed).

  However, the input control device 50 requires a diagnosis time for the input from the sub-circuit 2 side. That is, there is a problem that a time lag occurs between the timing of acquiring the PV value from the main circuit 1 and the timing of acquiring the error status flag until the computer side acquires the error status flag from the comparator 3. FIG. 8 schematically shows the relationship between the change in PV value and the diagnosis time. In FIG. 8, the curve in the graph represents the transition of the change rate of the PV value. The initially normal PV value is assumed to change rapidly at time ta due to, for example, a failure of the main circuit 1. The change in the PV value at the time ta is detected by the comparator 3 and the status signal is output, but it takes time N until the error status signal is input to the computer side by the timer in the filter circuit 4. . During this time N, an abnormal input signal is output from the main circuit 1 side to the computer side as a PV value. However, while the error status flag cannot be acquired yet, the computer cannot determine that the PV value input from the main circuit 1 is an abnormal PV value, and an abnormal PV value on the memory. To control the plant. As a result, this abnormal PV value causes a problem that disturbances occur in various subsequent controls.

  Therefore, in order to prevent an abnormal update of the PV value on the computer side, a method of delaying the output of the PV value on the main circuit 1 side according to the diagnosis time of the diagnosis system is generally performed. The input control device 60 shown in FIG. 7 is configured to delay the output of the PV value on the main circuit 1 side by the diagnosis time of the diagnosis system (assuming t3 [s] is set), and further, an error status A switch 6 that cuts off the conduction on the main circuit 1 side by the input of a flag is provided. More specifically, the input control device 60 prevents an abnormal PV value from being input to the computer during a time lag of t3 [s] that occurs between the main circuit 1 side and the sub circuit 2 side. Therefore, a buffer device that delays the signal output from the main circuit 1 side by a time corresponding to t3 [s] is provided (a plurality of “PVs” shown in FIG. 7 are t3 delayed by the buffer device). PV value for [s] is shown. For example, even if an abnormal PV value occurs due to a failure on the main circuit 1 side or the like, during the diagnosis time (t3 [s]) of the diagnostic system, a normal PV value buffered in the buffering device (abnormal PV value and The PV value before) is input to the computer side. After an error status flag is output from the filter circuit 4 by the diagnostic system after t3 [s], the switch 6 is opened and the input to the computer side is cut off before an abnormal PV value is conducted from the main circuit 1 side. . The computer that has received the error status flag is configured to hold (hold) the PV value that has been normally output (hereinafter referred to as “previous PV value”). That is, when the switch 6 is opened by the error status flag output from the comparator 3, the PV value output from the main circuit 1 is normal, so the switch 6 is opened in the memory on the computer side. The previous normal PV value is held (updated on the memory).

  However, since the input control device 60 needs to be provided with a RAM (Random Access Memory) as a buffer device, there is a problem that a cost burden is required in securing hardware resources. Furthermore, there is a problem that the primary response from the plant side deteriorates due to buffering.

  Therefore, in order to solve the problem of the diagnosis time in the input control devices 50 and 60 and the problem of ensuring the primary response from the plant side, a configuration of the input control device 70 as shown in FIG. 9 can be considered. In the input control device 70, unlike the input control device 60, the switch 6 is immediately opened based on the status signal output from the comparator 3 without providing a buffer device on the main circuit 1 side. In other words, before the abnormal PV value is output from the main circuit 1 to the computer side, the computer side can hold the previous PV value.

However, the configuration of the input control device 70 has a problem that the response of the device becomes too sensitive to changes in the input signal, making it difficult to control the input signal. That is, in an actual circuit configuration, it is normal that a minute change or a timing error occurs in a signal flowing in each circuit element of the input control device due to individual differences between the circuits on the main circuit 1 side and the sub circuit 2 side. is there. There is a sufficient possibility that the comparator 3 may erroneously recognize that the signal is a minute change, a timing error, or an abnormal PV value. If the switch 6 is opened and the PV value is held every time this erroneous recognition is performed, there is a problem that the primary response from the plant side cannot be obtained on the computer side. That is, even if it is possible to prevent disturbance to the operation of the plant, there are not a few cases where the input signal input to the computer side is not the primary response, and it becomes impossible to realize highly accurate plant control. There's a problem.
Further, in order to prevent such a problem of erroneous recognition of the comparator 3, it can be considered that each circuit element constituting the input control device 70 is constituted by a more accurate element. Because of this problem, there is also a problem that it is difficult in practice.
JP 2004-207830 A

  The present invention has been made to solve the above-mentioned problems, and a first object is to reliably hold or reset the previous PV value when a failure of the input control device occurs. The second objective is to make the plant control system fail-safe. The second purpose is to deal with individual differences in each circuit constituting the input control device with respect to changes in the input signal itself from the plant side. By realizing the hold operation of the PV value without being affected, it is possible to obtain a normal primary response with high accuracy on the computer side, and a third object is to realize these at a low cost. That is.

In order to solve the above problem, the invention described in claim 1 is characterized in that a plurality of independent input circuits (for example, the main circuit 1 and the sub circuit 2 shown in FIG. 1) to which the same input signal is input, An output circuit that outputs the output signal of any one of the input circuits as a process value, and a diagnostic circuit that diagnoses whether there is an abnormality in the input signal based on the output signal of each input circuit (for example, in FIG. A comparator 3), and a shut-off means (for example, switch 6 shown in FIG. 1) that receives the diagnosis result signal of the diagnostic circuit and shuts off the output circuit when the result signal indicates abnormality of the input signal. In the input control device characterized by comprising:
Change detection circuits (corresponding to each of the input circuits) that detect a change in the input signal based on an output signal of each input circuit (for example, the first change detection unit 7 and the second change detection unit 7 shown in FIG. Change detector 8);
A first pulse signal generation circuit (for example, pulse output units 9 and 10 shown in FIG. 1) provided for each of the change detection circuits, which receives an output signal of the change detection circuit and outputs a predetermined pulse signal. When,
A first arithmetic circuit (for example, a logical arithmetic circuit 11 shown in FIG. 1) for calculating a logical product of output signals of the first pulse signal generation circuit ;
An inverting circuit for inverting the output signal of the first arithmetic circuit (for example, a negative arithmetic circuit 13 shown in FIG. 1);
A second arithmetic circuit (for example, FIG. 1) that calculates the logical product of the output signal of the inverting circuit and the output signal of the diagnostic circuit, and outputs the calculation result signal to the blocking means as the opening / closing command signal of the blocking means. Logical operation circuit 14) shown in FIG.
It is characterized by providing.

According to a second aspect of the invention, the input control device according to claim 1,
The first pulse signal generation circuit outputs a pulse signal for at least a sampling time of the input signal.

According to a third aspect of the present invention, in the input control device according to the first or second aspect, when an asserted result signal output by a logical product operation of the first arithmetic circuit is received, the output is started. A second pulse signal generation circuit (for example, the pulse output unit 12 shown in FIG. 1) that continues output for a predetermined time from when the asserted result signal is negated is further provided.

According to a fourth aspect of the present invention, in the input control device according to the third aspect , the predetermined time during which the second pulse signal generation circuit generates a pulse is caused by at least an individual difference between the plurality of input circuits. It is a difference in timing of outputting an input signal.

The invention according to claim 5 is the input control device according to claim 4 ,
A fail signal output circuit (for example, the filter circuit 4 shown in FIG. 1) that outputs a fail signal of the input signal by receiving a result signal indicating abnormality of the input signal output from the diagnostic circuit for a predetermined time is further provided. ,
The fail signal output circuit receives the pulse signal output from the second arithmetic circuit and clears the predetermined time.

According to a sixth aspect of the present invention, in the input control device according to any one of the first to fifth aspects, the input signal is an analog signal or a digital signal.

In the invention according to claim 1, a plurality of independent input circuits to which the same input signal is input, an output circuit that outputs an output signal of any one of the input circuits as a process value, and A diagnostic circuit for diagnosing the presence or absence of an abnormality of the input signal based on an output signal of each input circuit, and a diagnostic result signal of the diagnostic circuit, and when the result signal indicates an abnormality of the input signal, the output circuit In the input control device characterized by comprising a blocking means for blocking,
A change detection circuit provided corresponding to each of the input circuits, and detecting a change in the input signal based on an output signal of the input circuit;
A first pulse signal generation circuit that is provided for each of the change detection circuits, receives an output signal of the change detection circuit, and outputs a predetermined pulse signal;
A first arithmetic circuit for calculating a logical product of output signals of the first pulse signal generation circuit ;
An inverting circuit for inverting the output signal of the first arithmetic circuit;
A second arithmetic circuit that calculates a logical product of the output signal of the inverting circuit and the output signal of the diagnostic circuit, and outputs the operation result signal to the blocking means as an opening / closing command signal of the blocking means; It was characterized.

  For this reason, even if one of the multiple input circuits stops functioning due to a failure, etc., and the process value becomes abnormal, the diagnostic circuit diagnoses this abnormality and outputs the result, and the output circuit is shut off by the shut-off means Therefore, there is an effect that it is possible to prevent the abnormal process value from being output to the control computer side of the plant.

A change detection circuit that is provided corresponding to each input circuit and detects a change in the input signal based on the output signal of each input circuit, and receives the output signal of the change detection circuit, and receives a predetermined pulse signal. By providing a first pulse signal generation circuit for output and a first calculation circuit for calculating the logical product of the output signals of the first pulse signal generation circuit , each input signal is assigned to each input signal due to individual differences of the input circuit. Even when the diagnostic circuit mistakenly recognizes that the input control device has failed due to the timing error that occurs, it can be determined that such an error is a misrecognition caused by individual differences in the input circuit. . That is, based on a signal output from a change detection provided corresponding to each input circuit, a first arithmetic circuit that determines whether a change in the input signal is due to a failure or the like, and the first arithmetic circuit By providing a second arithmetic circuit that outputs a control signal for controlling the shutoff of the output circuit by the shutoff means based on the result signal of the arithmetic circuit and the output signal output from the diagnostic circuit, the operation of the shutoff means accurately Therefore, there is an effect that a normal process value hold process can be performed more accurately.

The invention described in Claim 2 is the input control apparatus according to claim 1, wherein the first pulse signal generation circuit as being to output the sampling time of the pulse signal of at least the input signal Yes.

According to the second aspect of the present invention, when the output signal from the change detection circuit is input to the first logic operation circuit, it can be input in a state in which there is a certain synchronization or synchronization timing. That is, the output signal from the change detection circuit is not input in a state where the output signal from the change detection circuit is synchronized or synchronized with the first logic operation circuit due to an error in the timing of the input signal output from each input circuit due to individual differences of the input circuit. There is also a fear. Usually, this error can be contained in an error within a sampling interval for sampling an input signal in each input circuit. Therefore, such an error is within the sampling period of each input circuit at the maximum. Therefore, each change detection circuit generates a pulse signal for at least the sampling time, so that the asserted signal output from the change detection circuit is reliably synchronized or synchronized with the first logic operation circuit. There is an effect that it can be input.

According to a third aspect of the present invention, in the input control device according to the first or second aspect, when an asserted result signal output by a logical product operation of the first arithmetic circuit is received, the output is started. A second pulse signal generation circuit that continues output for a predetermined time from when the asserted result signal is negated is further provided.

According to a fourth aspect of the present invention, in the input control device according to the third aspect , the predetermined time during which the second pulse signal generation circuit generates a pulse is based on at least an individual difference between the plurality of input circuits. It is the difference of the timing which outputs the said input signal which arises, It is characterized by the above-mentioned.

According to the third and fourth aspects of the invention, the output result of the first logical operation circuit can be reliably input to the second logical operation circuit via the inverting circuit. That is, in the second logical operation circuit, a logical product operation is performed based on the output signal from the first logical operation circuit input via the inverting circuit and the result signal output from the diagnostic circuit. The diagnostic circuit outputs a result signal to the second logic operation circuit based on changes in the signals output from the plurality of input circuits. At this time, an error in the output timing of the signals output from the plurality of input circuits resulting from individual differences between the plurality of input circuits is erroneously recognized as a failure of the input control device and the like, and an abnormality in the input signal is detected in the second logic operation circuit. By outputting the result signal to notify, the second logical operation circuit may output a control signal for releasing the result interruption unit of the logical product operation (that is, unnecessary PV value hold processing is performed). will have to go.). In order to stop the output of the control signal, the output signal from the first logic operation circuit is reliably input to the second logic operation circuit by continuously generating pulses from the second pulse signal generation circuit for a predetermined time. be able to.

In particular, the output signal output from the first logic operation circuit performs a logical product operation based on the signals output from the change detection circuit and the first pulse signal generation circuit, respectively. The signals output from the change detection circuit and the first pulse signal generation circuit are also output to the first logic operation circuit based on the input signals output from the plurality of input circuits. Since each of these signals is also affected by an error in the output timing of the signal due to the individual difference for each input circuit, the timing at which each signal is input to the first logic operation circuit may be extremely short. There is also.
Therefore, even if the assert signal output from the first logic operation circuit is for a very short time, when the assert signal is input, output is started, and then the asserted signal result is negated. By providing the second pulse signal generation circuit that continues output for a predetermined time from time to time, it is possible to reliably input a signal for stopping the output of the control signal instructing opening of the cutoff means from the second logic operation circuit. become able to.

  Furthermore, the predetermined time is set to be at least the time difference between the timings at which the input signals generated due to individual differences among the plurality of input circuits are output, and the input of signals generated in each circuit of the input control device due to this difference is set. During the transient state of the output timing, it is possible to reliably stop the output of the control signal from the second logic operation circuit. As a result, the unnecessary PV value hold can be canceled and the primary response from the plant side can be accurately input to the computer side.

The invention according to claim 5 is the input control device according to claim 4 ,
A fail signal output circuit for outputting a fail signal of the input signal by receiving a result signal indicating abnormality of the input signal output from the diagnostic circuit for a predetermined time;
The fail signal output circuit receives the pulse signal output from the second arithmetic circuit and clears the predetermined time.

According to the fifth aspect of the present invention, there is provided a fail signal output circuit for receiving a result signal output from the diagnostic circuit and outputting a status signal indicating that the input signal is abnormal by receiving the result signal for a predetermined time. In addition, it is possible to prevent the fail signal from being output to the computer side more frequently than necessary due to minute changes in the input signal.
Further, the predetermined time counted by the fail signal output circuit is cleared by the pulse signal output from the second pulse generation circuit, so that the fail signal is transmitted to the computer side based on the result signal input from the diagnostic circuit. Can continue to stop being entered. That is, there is an effect that a normal primary response from the plant side is continuously input to the computer side, and a highly accurate input is performed without a fail signal being input.

According to the sixth aspect of the present invention, the present invention has an effect that accurate input control can be performed regardless of whether the input signal is an analog signal or a digital signal.

The best mode for carrying out the present invention will be described below. FIG. 1 is a circuit diagram showing a schematic configuration of an input control device 40 to which the present invention is applied.
The input control device 40 is input from the main circuit 1 that inputs one of the input signals a input to the two systems, the sub-circuit 2 that inputs the other input signal, the main circuit 1 and the sub-circuit 2. Comparing the signals b and c and detecting a PV value abnormality, the comparator 3 outputs a signal i (status signal). When the signal i output from the comparator 3 is detected for a predetermined time, an error status flag is displayed on the computer side. The filter circuit 4 that outputs the signal, the first change detection unit 7 that monitors the change in the signal b output from the main circuit 1, and the signal d output from the first change detection unit 7 generate a predetermined pulse signal d '. A pulse output unit 9 to be generated, a second change detection unit 8 for monitoring a change in the signal c output from the sub-circuit 2, and a signal e output from the second change detection unit 8 to generate a predetermined pulse signal e ′. Pal Output unit 10, pulse output unit 9, logical operation circuit 11 that performs a logical product operation based on the pulse signal output from pulse output unit 10, and output signal f from logical operation circuit 11, and then signal f is negated Then, a pulse output unit 12 that outputs a predetermined pulse signal g for a predetermined time, a negative operation circuit 13 that performs a negative operation on the pulse signal g output from the pulse output unit 12, and an output signal i of the status signal of the comparator 3 And a logical operation circuit 14 that performs a logical product operation based on the output h from the negative operation circuit 13 and the conduction of the PV value output from the main circuit 1 to the computer side based on the operation result signal k of the logical operation circuit 14. It is composed of a switch 6 that cuts off.
Below, the more specific structure of each part is demonstrated.

  In the input control device 40, input is performed to two systems of the input circuit a, the main circuit 1 to which one input signal is input and the sub-circuit 2 to which the other input signal is input. The input signal a input to the main circuit 1 is then output as a signal b and input to the computer side as a PV value. The input signal a input to the sub-circuit 2 is then output as a signal c and input to the computer side as a diagnostic system input.

The signals b and c output from the main circuit 1 and the sub circuit 2 are also input to the comparator 3.
The comparator 3 compares the values (voltage values) of the signals b and c, and outputs a signal i, that is, a status signal when a change greater than a predetermined value occurs in both. In addition, when the change beyond a predetermined value has not arisen in both, the signal similar to PV value is output.
When the status signal (signal i) is output from the comparator 3, it is input to the filter circuit 4 and a logic operation circuit 14 described later.

  The filter circuit 4 is provided with a timer for measuring the detection time of the input status signal (signal i). When a predetermined time elapses after the status signal (signal i) is input, an error status flag (signal j) is output to the computer side. On the computer side, the abnormality of the input signal is determined based on the signal j.

The signal b output from the main circuit 1 is also input to the first change detection unit 7. The first change detection unit 7 monitors the change in the value (voltage value) of the signal b input from the main circuit 1. When detecting a change greater than a predetermined threshold, the first change detection unit 7 An instruction signal d instructing generation of a pulse is output.
Further, the signal c output from the sub circuit 2 is also input to the second change detection unit 8. The second change detection unit 8 is also configured in the same manner as the first change detection unit 7, and monitors changes in the value (voltage value) of the signal c input from the sub circuit 2. When detecting a change that is greater than or equal to a predetermined threshold, an instruction signal e that instructs the pulse output unit 10 to generate a predetermined pulse is output.

  FIG. 2 shows a configuration example of the first change detection unit 7 and the second change detection unit 8. In the first change detection unit 7 and the second change detection unit 8, the signal b or c input from the main circuit 1 or the sub circuit 2 is input in two systems. One of the signals b or c input separately is input to the buffer 20 and is delayed for a predetermined time. Thereafter, the other signal separately input and the signal output from the buffer 20 are input to the comparator 21, and the change in voltage value between the signal delayed by the buffer 20 and the other signal is compared. When the difference between the two changes is equal to or greater than a predetermined threshold value, the signal d ′ and the signal e ′ are respectively output to the logic operation circuit 11 via the pulse output unit 9 or 10.

The pulse output unit 9 and the pulse output unit 10 receive an instruction signal d or e and generate predetermined pulse signals d ′ and e ′. The pulse output units 9 and 10 generate pulses for at least the sampling time of the input control device 40 after the input of the signal d or signal e input from the first change detection unit 7 or the second change detection unit 8 is asserted. It is preferable to configure so as to continue to occur. That is, the logical operation circuit 11 to be described later performs a logical product operation based on the input from the main circuit 1 side and the input from the sub circuit 2 side, and both inputs are “true” (logically “1”). In this case, the signal f is output. For this reason, due to individual differences in circuit elements and the like of the main circuit 1 and the sub circuit 2, there is a timing shift between the signal d and the signal e output from the first change detector 7 and the second change detector 8. It may occur. Due to this timing shift, it is conceivable that there is no timing at which both signals are synchronized at the timing when the logical operation circuit 11 performs a logical product operation.
Therefore, the input control device 40 generates pulse signals (d ′ and e ′) at least for the sampling interval of the input signal from the pulse output units 9 and 10 after the input of the signal d and the signal e is negated, and the timing described above. Even if the above deviation occurs, a time for synchronizing both signals is secured at the timing when the logical operation circuit 11 performs the logical product operation.

The pulse signals output from the pulse output units 9 and 10 are input to the logic operation circuit 11. The logical operation circuit 11 is an AND circuit that performs a logical product operation based on the pulse signals input from the pulse output units 9 and 10. More specifically, when both pulse signals are input, the asserted signal f is output.

  The pulse output unit 12 receives the signal f input from the logic operation circuit 11, outputs a pulse signal g when the signal f is asserted, and then performs a negative operation for a predetermined time from the moment of negation. The pulse signal g is continuously output to the circuit 13 and the filter circuit 4. When the status signal (signal i) from the comparator 3 is input, the filter circuit 4 receives the input of the pulse signal g to clear the timer that has been counting until then. That is, when the filter circuit 4 receives the input of the pulse signal g, the input control is performed by the input error of the signal b and the signal c generated by the comparator 3 due to individual differences in circuit elements constituting the main circuit 1 and the sub circuit 2. Based on the signal f input from the logical operation circuit 11 or the like, which is erroneously recognized as a failure of the device 40, outputs a status signal (signal i) to the filter circuit 4 and monitors the change between the signal b side and the signal c side. This is a case where the pulse signal g is output from the pulse output unit 12. Since the filter circuit 4 outputs an error status flag (signal j) after waiting for the elapse of a predetermined time by the timer, the filter circuit 4 is cleared by the input of the pulse signal g, thereby causing the comparator 3 to be erroneously recognized. The status signal (signal i) output to the logic operation circuit 14 can be masked.

  The negative operation circuit 13 is a NOT circuit that performs a negative operation on the pulse signal g input from the pulse output unit 12. The signal inverted by the negative operation circuit 13 is output to the logic operation circuit 14.

  The logical operation circuit 14 is an AND circuit that performs a logical product operation based on signals output from the comparator 3 and the negative operation circuit 13. When the signals output from the negative operation circuit 13 and the comparator 3 are “(logically) 1”, the signal k is output to the switch 6 to be opened, and the PV value from the main circuit 1 is cut off. It has become. When this block is performed, the computer side updates the PV value before the block on the memory (that is, holds the previous PV value).

Next, the operation of the input control device 40 having the above configuration will be described. The input control device 40 ensures that the normal PV value before the abnormality is opened by opening the switch 6 when an abnormality occurs in the PV value due to a failure of the main circuit 1 or the sub circuit 2 or the like. Even if there is no abnormality in the holding and PV value, the switch 6 is opened erroneously due to an erroneous recognition of the PV value due to individual differences of the circuit elements constituting the main circuit 1 and the sub circuit 2. The main purpose is to prevent excessive operation and to secure a primary response from the plant side.
Therefore, in the following description, (1) PV value hold operation when a failure or the like actually occurs and (2) operation when erroneously recognized as a failure or the like will be described.

(1) [PV value hold operation in which a failure or the like actually occurs]
First, an operation when a failure occurs on the main circuit 1 side or the sub circuit 2 side will be described. Although the case where the main circuit 1 side fails will be described as an example, the same conclusion is reached when the sub circuit 2 side fails.

  The comparator 3 logically outputs a status signal (logically “1”) indicating an abnormality in the PV value when a certain difference occurs between the input signals b and c output from the main circuit 1 side and the sub circuit 2 side. The result is output to the arithmetic circuit 14. The logical operation circuit 14 performs an AND operation based on the status signal and the signal h output from the negative operation circuit 13.

Here, the signal h output from the negative operation circuit 13 is “1”. That is, since a change occurs in the signal b when the main circuit 1 fails, the first change detection unit 7 is activated, and a signal (signal d) instructing the generation of a pulse is output to the pulse output unit 9. On the other hand, the second change detection unit 8 is not activated because the signal on the sub-circuit 2 side is normal (the signal has no change). Further, no pulse signal is generated from the pulse output unit 10. Therefore, a logical “1” signal is input to the logical operation circuit 11 from the pulse output unit 9 and a logical “0” signal is input from the pulse output unit 10, and the result of the logical product operation performed in the logical operation circuit 11. Becomes “0”. Accordingly, the logic operation circuit 11 does not output a signal (signal f) that instructs the pulse output unit 12 to generate a pulse.
Since the pulse output unit 12 does not receive the input of the signal (signal f) instructing the generation of the pulse, the signal g output from the pulse output unit 12 does not change (logically “0”), and the negative operation circuit 13 and the filter circuit 4. The signal g output to the negative operation circuit 13 is inverted to “1” by the negative operation, and the result is output to the logic operation circuit 14 as a signal h.

  In the filter circuit 4 as well, since the signal g input from the pulse output unit 12 is a “(logically) 0” signal, the timer is not cleared, and the error status flag is set to the computer side after a predetermined time has elapsed. Is output.

  In the logical operation circuit 14, the logical operation circuit 14 is based on the signal h (logically “1”) output from the negative operation circuit 13 and the signal i (logically “1”) output from the comparator 3. Derives “1” by AND operation and outputs the result to the switch 6 as a signal k. The switch 6 receiving the input of the signal k opens the switch. That is, thereafter, the hold processing for updating the previous PV value is performed on the computer side.

  As described above, in the event of a failure in either the main circuit 1 or the sub circuit 2, the input control device 40 can reliably realize the hold of the PV value.

(2) [Operation when misrecognized as a failure, etc.]
Next, the operation of the input control device 40 when the comparator 3 is erroneously recognized as a failure or the like will be described. As described in the description of the input control device 70 as the prior art, in the actual circuit configuration, the input values of the main circuit 1 and the sub circuit 2 are usually fine due to individual differences between the main circuit 1 side and the sub circuit 2 side. In most cases, a change or timing error occurs. In the input control device 40 according to the present embodiment, the comparator 3 erroneously recognizes this minute change or timing error as a device failure or the like, and opens the switch 6 (that is, PV value hold). It can be prevented. As a result, unnecessary holding of the PV value can be prevented, and the primary response from the plant side can be input to the computer side.

The timing chart of FIG. 3 shows the timing at which the signals input (output) to each part of the input control device 40 change.
In the following description, the case where the signal detection on the sub-circuit 2 side is delayed as compared with the signal detection on the main circuit 1 side will be described as an example.
First, it is assumed that the input signal a has changed before the timing t0. In response to this change, the signal b output from the main circuit 1 appears between timings t0 and t1.
Also, no change occurs in the signal c output from the sub-circuit 2 between the timings t0 and t1. That is, this is due to a time lag caused by individual differences in circuit elements.
In FIG. 3, changes in the signal b and the signal c are expressed so as to gradually change, as in the actual voltage value change.

  At timing t1, the first change detector 7 detects a change (point A) in the signal b output from the main circuit 1, and outputs an instruction signal (signal d) for generating a pulse to the pulse output unit 9. (Point A ′). Even at the timing t1, the signal c output from the sub-circuit 2 is still not changed.

On the other hand, the comparator 3 detects a change in the signal b and the signal c (change in voltage value) and outputs a status signal (signal i) to the logic operation circuit 14 and the filter circuit 4. In the logical operation circuit 14 that has received the status signal (logically) “1”, from the logical product operation with the (logically) “1” signal input from the negative operation circuit 13, ( A signal k which is logically “1” is output to the switch 6. The switch 6 that receives the input of the signal k opens the switch, and the PV value is held.
The timer of the filter circuit 4 that has received the input of the status signal (signal i) also starts measuring a predetermined time until the error status flag (signal j) is output to the computer side.

On the other hand, the pulse output unit 9 receives a signal (signal d) instructing generation of a pulse input from the first change detection unit 7 and outputs a pulse signal to the logic operation circuit 11. Note that the output time of the pulse signal is preferably at least the sampling period of the input signal. That is, the pulse signal asserted to the logic operation circuit 11 is not input at the same timing (or to the logic operation circuit 11) due to a timing error caused by a difference in circuit elements between the main circuit 1 and the sub circuit 2. There is also a case where there is no timing at which both asserted pulse signals are input.
Therefore, an assert signal d ′ (or e) corresponding to at least the sampling period of the input signal is output by the pulse output unit 9 (or 10) with respect to the change in the signal detected by the first change detection unit 7 (or the second change detection unit 8). In addition to the change times of the signal d and the signal e detected by the first change detection unit 7 and the second change detection unit 8, an assert signal having a sampling period or more is output to the logical operation circuit 11. Can be compensated for. As a result, signals that are logically “1” can be simultaneously input to the logical operation circuit 11 (or there is a timing at which they are simultaneously input).

Next, a change corresponding to the input signal a occurs in the signal c output from the sub circuit 2 between timings t1 and t2.
At timing t2, the second change detector 8 detects a change in the signal c (point B) (point B ′), and outputs a pulse output instruction signal (signal e) to the pulse output unit 10. The pulse output unit 10 to which the signal (signal e) instructing the output of the pulse is input generates a pulse for at least the sampling period even after the asserted signal input from the second change detection unit 8 is negated. To do.

  At timing 2, the logical operation circuit 11 detects the asserted pulse signal input from the pulse output units 9 and 10. In FIG. 3, time tx indicates a time interval in which the pulse signals d ′ and e ′ output from the pulse output units 9 and 10 are input by the logic operation circuit 11 at the same time. The logical operation circuit 11 performs a logical product operation based on the pulse signal d ′ (logically “1”) and the signal e ′ (logically “1”) input during this tx, and results in “1”. Lead. That is, it is logically “1”, and the asserted signal is output to the pulse output unit 12 (signal f).

The pulse output unit 12 receives this signal f, then generates a pulse signal (signal g) for a predetermined time, and outputs it to the negative operation circuit 13 and the filter circuit 4. More specifically, the signal g is asserted when the signal f is asserted, and the pulse signal g is continuously generated for a predetermined time after the signal f is negated.
In the negative operation circuit 13, a negative operation for logically setting the signal g to “0” is performed, and as a result, the signal h is output to the logical operation circuit 14. The signal i (logically “1” signal) is already input from the comparator 3 to the logical operation circuit 14 at the stage of timing t1. Accordingly, the result of the logical product operation performed by the logical operation circuit 14 is “0” because it is the logical product of the signal i (“1”) and the signal h (“0”). At the moment when this result is derived, the logical operation circuit 14 outputs an output of a signal (signal k) instructing opening to the switch 6 that has been output since the input of the signal i from the comparator 3 at the timing t 1. Will stop. As a result, the switch 6 from which the input of the signal k is stopped is closed, and the signal b (PV value) output from the main circuit 1 is input again to the computer side.

  On the other hand, in the filter circuit 4 that has received the input of the signal g output from the pulse output unit 12, the timer that has started timing is cleared when the status signal (signal i) is input from the comparator 3 at timing t1. (Timing t2). Further, while the signal g continues to be output from the pulse output unit 12 thereafter, the timer of the filter circuit 4 is continuously cleared, and the status signal (signal i) output from the comparator 3 to the filter circuit 4 is the error status signal. (Signal j) is not output to the computer side.

  As described above, according to the input control device 40, there is an effect that the PV value hold process can be reliably performed when a failure of the main circuit 1 or the sub circuit 2 occurs.

In addition, when a change occurs in the input signal a, a first change detection unit 7 and a pulse output unit 9 that detect and output a change in the signal b, and a second change detection unit that detects and outputs a change in the signal c. 8 and the pulse output unit 10, and a logical operation for judging whether the signal output from these signals is input at the same time to determine whether the input signal a itself is a change or a signal change due to a device failure or the like. The circuit 11 and the pulse output unit 12 that outputs a pulse for a predetermined time based on the signal output from the logic operation circuit 11 may change the input signal a itself or a signal change caused by a failure of the device. It can be automatically determined whether or not there is. When this determination is a change in the input signal a itself, the logical product operation result of the logical operation circuit 14 is set to “0”, the switch 6 is closed, the timer of the filter circuit 4 is cleared, and the error status flag is set to the computer side. Can be prevented.
As a result, when there is a failure on the main circuit 1 side or the sub circuit 2 side, the previous PV value update process can be performed, and the change in the input signal a itself due to individual differences of each circuit element is regarded as a failure or the like. In the case of misrecognition, the misrecognition is masked, and the switch 6 can be opened immediately to ensure that the primary response from the plant side is input to the computer side. There is an effect that the accuracy of the value can be improved.

  Furthermore, since the input control device 40 having such an effect can be realized at a low cost by a relatively simple circuit configuration, there is an effect that the practicality is improved.

[Application Example 1]
Next, an application example 1 using the input control device 40 described above will be described with reference to FIG. The input control module 41 of the application example 1 is configured such that the main circuit 1 and the sub circuit 2 are independently input, and the input control device 40 performs input signal diagnosis and PV value hold processing at the time of abnormality. Yes. When an abnormality occurs, the previous PV value before the abnormality is held by opening the switch 6 is held.

  After the previous PV value is held, the selector 85 uses the previous PV value as it is based on the instruction signal from the logic operation circuit 86, changes it to a value designated in advance by the user, or resets it. It is possible to switch the crab.

The logical operation circuit 86 is a logical circuit that performs an AND operation, and the user can preset the use of the previous PV value, the change to the specified value, or the reset as described above. When an error status flag is output from the input control device 40, a logical product operation is performed, and an instruction signal for instructing one of these settings is output to the selector 85.
Generally, in the technical field of plant control, even if an abnormality is detected in an input signal from the plant side, the operation of the plant is often not stopped. For this reason, when an abnormality is detected in the input signal, an input signal to be used as an alternative can be set. Furthermore, there are a plurality of options for the input signal used as an alternative, and it is practical to continue the operation of the plant by appropriately selecting these options according to the situation of the manufacturing process, the product being manufactured, etc. There is a favorable situation.

  Therefore, in the input control module 41, when an abnormality is detected in the input signal due to a failure or the like, the previous PV value can be updated, or the user's user can change the specified value 82 or the reset value (default value) 83 as shown in FIG. According to the setting, the PV value can be substituted and fail-safe can be performed.

  As described above, by applying the input control device 40 to the input control module 41, it is possible to reliably prevent an abnormal PV value from being input to the plant control system, and to replace the PV value with the input signal. The previous PV value can be set to an arbitrary value desired by the user, and there is an effect that the accuracy of control of the input signal is remarkably improved in the system management of the plant.

[Application 2]
Next, an input control device 46 will be described as an application example when input signals from the plant side are multiplexed. The input control module 42 shown in FIG. 5 is configured such that input signals from the plant side are input to three or more systems. The input control device 46 can perform suitable input control even when such input systems are multiplexed (three or more). FIG. 10 shows an example of the circuit configuration of the input control device 46 when the input system is multiplexed (in this application example, three input circuits are shown).

  Differences in configuration between the input control device 46 and the input control device 40 include a comparator 104 instead of the comparator 3, a logical operation circuit 103 instead of the logical operation circuit 11, and a third change detection unit 101 and The pulse output unit 102 is added.

  The comparator 104 receives signals output from the main circuit 1, the sub circuit 2, and the sub circuit 100. The comparator 104 compares changes in these three input signals, and outputs a status signal that is logically “1” to the logical operation circuit 103 when the voltage value changes to a predetermined value or more, and simultaneously performs filtering. A status signal is also transmitted to the circuit 4. More specifically, the signal is output not only when all three signals change, but also when any one signal changes to a voltage value different from the other two signals.

  The third change detection unit 101 has the same configuration as the first change detection unit 7 and the second change detection unit 8, and monitors changes in signals input from the sub circuit 100. When there is a change in the signal input from the sub-circuit 100, a pulse generation instruction signal is transmitted to the pulse output unit 102, and the asserted pulse signal for at least the sampling time of the input signal from the pulse output unit 102 is a logic operation circuit. 103. In the logical operation circuit 103, logical product operation is performed based on the pulse signals output from the pulse output units 9, 10 and 102. In the logic operation circuit 103, when a pulse signal is input from all of the pulse output units 9, 10, and 102, a pulse generation instruction signal for instructing the logic operation circuit 11 to generate a pulse is output.

  That is, even if a signal detection timing error caused by individual differences between the circuit elements constituting the main circuit 1, the sub circuit 2, and the sub circuit 100 occurs, the pulse output units 9, 10 and 102 can detect the timing error. A pulse signal that compensates for time is output. For this reason, it is reliably determined whether the change in the signal recognized by the comparator 104 is a change in the input signal itself input from the plant side or a change in the signal due to a circuit failure or the like. be able to.

  As described above, even if the input system is multiplexed (three or more), the function of the input control device 46 is sufficiently effective, and a highly accurate primary response can be input in the plant control management system. it can.

  As mentioned above, although the best form for implementing this invention was demonstrated, this invention is not limited to the said various example.

1 is a circuit diagram showing an outline of an input control device in the best mode of the present invention. FIG. 3 is a circuit diagram showing a configuration example of a first change detection unit and a second change detection unit in the circuit diagram of the input control device shown in FIG. 1. 2 is a timing chart showing an operation in the input control device shown in FIG. 1. It is the block diagram which showed one application example using the input control apparatus shown in FIG. It is the block diagram which showed one application example using the input control apparatus shown in FIG. It is the circuit diagram which showed an example of the conventional input control apparatus. It is the circuit diagram which showed an example of the conventional input control apparatus. It is the graph which showed the change with the change of an input signal, and its diagnostic time. It is the circuit diagram which showed an example of the conventional input control apparatus. FIG. 6 is a schematic diagram showing an example of a circuit configuration when the input control device shown in FIG. 1 is used in the aspect of application example 2.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Main circuit 2,100 Subcircuit 3,104 Comparator 4 Filter circuit 6 Switch 7 1st change detection part 8 2nd change detection part 9,10,12,102 Pulse output part 11,14,86,103 Logic operation circuit 13 Negative operation circuit 20 Buffer 21 Comparator 40, 46, 50, 60, 70 Input control device 41, 42 Input control module 81 Previous PV value 82 Specified value 83 Reset 85 Selector 101 Third change detector

Claims (6)

A plurality of independent input circuits to which the same input signal is input, an output circuit that outputs an output signal of any one of the input circuits as a process value, and an output signal of each input circuit A diagnostic circuit for diagnosing the presence or absence of an abnormality of the input signal; and a blocking means for receiving the diagnosis result signal of the diagnostic circuit and blocking the output circuit when the result signal indicates an abnormality of the input signal. In an input control device characterized by:
A change detection circuit provided corresponding to each of the input circuits, and detecting a change in the input signal based on an output signal of the input circuit;
A first pulse signal generation circuit that is provided for each of the change detection circuits, receives an output signal of the change detection circuit, and outputs a predetermined pulse signal;
A first arithmetic circuit for calculating a logical product of output signals of the first pulse signal generation circuit ;
An inverting circuit for inverting the output signal of the first arithmetic circuit;
A second arithmetic circuit that calculates a logical product of the output signal of the inverting circuit and the output signal of the diagnostic circuit, and outputs the calculation result signal to the blocking unit as an opening / closing command signal of the blocking unit;
An input control device comprising: The input control device according to claim 1 ,
The input controller according to claim 1, wherein the first pulse signal generation circuit outputs a pulse signal corresponding to at least a sampling time of the input signal. In the input control device according to claim 1 or 2 ,
A second pulse signal that starts output upon receipt of an asserted result signal output by a logical product operation of the first arithmetic circuit, and continues output for a predetermined time after the asserted result signal is negated An input control device further comprising a generation circuit. The input control device according to claim 3 ,
The input control device according to claim 1, wherein the predetermined time during which the second pulse signal generation circuit generates a pulse is a timing difference at which the input signal is output resulting from at least an individual difference between the plurality of input circuits. The input control device according to claim 4 ,
A fail signal output circuit for outputting a fail signal of the input signal by receiving a result signal indicating abnormality of the input signal output from the diagnostic circuit for a predetermined time;
The fail signal output circuit receives the pulse signal output from the second arithmetic circuit and clears the predetermined time. In the input control device according to any one of claims 1 to 5 ,
The input control device characterized in that the input signal is an analog signal or a digital signal.

Images