JP4641104B2 - Semiconductor photodetection device - Google Patents

Description

【００５５】
図１に示したトランジスタＴ２を縦型ＮＰＮバイポーラトランジスタとする。また、これに隣接するトランジスタＴ１を縦型ＰＮＰバイポーラトランジスタＴ１とする。トランジスタＴ１の形成領域においては、Ｐ型ウエル領域５をコレクタ領域Ｔ１_Cとし、この表面層内にＮ型不純物を添加することにより、ベース領域Ｔ１_Bとなる高濃度Ｎ型半導体層を形成し、さらにこの内側にＰ型不純物を添加することにより、エミッタ領域Ｔ１_Eとなる高濃度Ｐ型半導体層を形成する。また、当該トランジスタの形成領域においては、図１に示したｐ層３は、縦方向に延びるＰ＋層３とされ、Ｐ＋層３は基板１とＰ型ウエル領域５との界面において、Ｎ＋層２によって上下に分断されている。
【００５６】
縦型ＰＮＰバイポーラトランジスタＴ１に隣接して、縦型ＮＰＮバイポーラトランジスタＴ２が形成されている。当該トランジスタの形成領域においては、Ｐ型不純物ドープ領域５内に下部のＮ＋層２に連続するようなＮ型のウエル領域６を形成し、このＮ型ウエル領域６をコレクタ領域Ｔ２_Cとし、この表面層内にＰ型不純物を添加することにより、ベース領域Ｔ２_Bとなる高濃度Ｐ型半導体層を形成し、さらにこの内側にＮ型不純物を添加することにより、エミッタ領域Ｔ２_Eとなる高濃度Ｎ型半導体層を形成する。
【００５７】
なお、基板表面はＳｉＯ₂からなる保護膜（酸化膜）ＰＲＣＴによって被覆されており、保護膜ＰＲＣＴに設けられたスルーホールを介して、上記各半導体層に接続される複数の電極ｅが図示の如く設けられ、各電極ｅの直下には、その下の半導体層とのオーミック接触をとるための高濃度半導体層Ｅ_P，Ｅ_Nが設けられている。
【００５８】
また、本実施形態の半導体光検出器においては、縦型ＰＮＰトランジスタＴ１の形成領域内及び近傍において、その周囲を囲むように位置する第２半導体素子隔離領域３は、Ｐ型高抵抗エピタキシャル半導体層４がその上に形成される半導体基板１とＰ型高抵抗エピタキシャル半導体層４の間の界面から、エピタキシャル半導体層４及び半導体基板１双方内にＰ型の不純物を拡散することによって形成されると共にＰ型不純物ドープ領域５内に到達しており、前記界面からＰ型の不純物を前記双方内に拡散することによってトランジスタＴ１の周囲に位置する第２半導体素子隔離領域３と同時に形成されるトランジスタＴ１の形成領域内のＰ型埋込半導体層３が、縦型ＰＮＰトランジスタコレクタ領域Ｔ１_Cに到達している。
【００５９】
この場合、トランジスタＴ１の周囲に位置する第２半導体素子隔離領域３とトランジスタＴ１の形成領域内に位置するＰ型埋込半導体層３の不純物濃度は同一となる。このＰ型埋込半導体層３はトランジスタのコレクタ寄生抵抗を低下させ、電流増幅率を高め、高速動作を可能にする。
【００６０】
本例においては、エピタキシャル半導体層４は一層であるが、これは２層以上であってもよい。以下、このような例について説明する。
【００６１】
図３は図１に示した半導体光検出装置の更に好適な別の例を示す当該装置の縦断面図である。
【００６２】
本装置の基本構造は図１に示したものと略同一であるので、本装置の製造方法と共に、その構造について説明する。
【００６３】
本装置は、ＰＩＮホトダイオードＰＤに加えて、縦型ＰＮＰバイポーラトランジスタＴ１、縦型ＮＰＮトランジスタＴ２、横型ＰＮＰトランジスタＴ３、ＣＭＯＳトランジスタＴ４を同一の半導体基板１上に形成したものである。
【００６４】
本装置は、ＰＩＮホトダイオードＰＤの形成される領域及び縦型ＰＮＰバイポーラトランジスタＴ１の形成される領域以外の領域は、上述の装置の半導体基板１を、低濃度のＰ型半導体基板１’及び当該基板１’上に成長させた低濃度のＰ型エピタキシャル半導体層４からなるものとして読み替えたものである。
【００６５】
なお、ＰＩＮホトダイオードＰＤの形成される領域及び縦型ＰＮＰバイポーラトランジスタＴ１の形成される領域においては、このような読み替えを行わない。まず、これらの領域について説明する。なお、括弧内の符号は、読み替えを行った場合の要素について示す。
【００６６】
まず、半導体基板１の表層にＮ型不純物を添加し、Ｎ＋層２を形成する。次に、半導体基板１上に下部のエピタキシャル半導体層４（１）を成長させる。更に、このエピタキシャル半導体層４（１）の表面から深部に延び、最終的な拡散によってＮ＋層２に到達するＮ型半導体層６をＮ型不純物の添加によって形成する。更に、Ｐ層３と、最終的には上記Ｎ型半導体層６に接続される高濃度のＮ＋層６（２）とを、Ｐ型高抵抗エピタキシャル半導体層４（１）の表面層内に形成する。
【００６７】
続いて、上部のＰ型高抵抗エピタキシャル半導体層４を、下部のＰ型高抵抗エピタキシャル半導体層４（１）上に形成する。次に、上部のエピタキシャル半導体層４の第２領域Ｒ２内にＰ型不純物ドープ領域５を形成する。このＰ型不純物ドープ領域５のＰＮＰバイポーラトランジスタＴ１形成予定領域内の表面層内に、Ｎ型不純物を添加し、ベース領域となるＮ型半導体層Ｔ１_Bを形成する。しかる後、Ｎ型半導体層Ｔ１_B内に、Ｐ型不純物を添加し、エミッタ領域となるＰ型半導体層Ｔ１_Eを形成する。なお、ベース領域となるＮ型半導体層Ｔ１_Bの周囲に位置するＰ型不純物ドープ領域５は、このトランジスタのコレクタ領域として機能し、Ｐ型不純物ドープ領域５の当該コレクタ領域部分には高濃度のＰ型電極層Ｅ_Pが接続されている。
【００６８】
このＰ型電極層Ｅ_Pは、エピタキシャル半導体層４の表面層内に形成されるＰ＋層（アノード）、及びＰＩＮホトダイオードＰＤとトランジスタＴ１との間のＰ型不純物ドープ領域内に位置する別のＰ型電極層Ｅ_Pと同時に形成されるが、この形成は、これらの領域にＰ型不純物を添加し、基板をアニールすることによって行われる。
【００６９】
以上の工程に用いられるアニール処理によって、第１領域Ｒ１内のＮ型層２、６、６（２）が縦方向に連続することとなり、他の領域のＰ型層３が基板１に到達することとなる。なお、ＰＮＰバイポーラトランジスタＴ１の直下に位置するＰ＋層３は、他の領域に形成されたＰ層３よりも不純物濃度が高く、且つ拡散の深さが浅く、これらは別工程で形成される。
【００７０】
次に、図１に示した装置の半導体基板１を、低濃度のＰ型半導体基板１’及び当該基板１’上に成長させた低濃度のＰ型エピタキシャル半導体層４からなるものとして読み替えた場合の構造、すなわち、トランジスタＴ２、Ｔ３、Ｔ４の形成について説明する。
【００７１】
この場合、半導体基板１が既に形成されているので、Ｎ＋層２、Ｐ層３を各機能素子間に形成し、しかる後、上部のエピタキシャル半導体層４を半導体基板１上に形成し、次に、Ｐ型不純物ドープ領域５を形成する。Ｐ型不純物ドープ領域５内においては、Ｎ＋層２上に重なるように、Ｎ層（Ｎ型ウエル領域）６を形成する。
【００７２】
縦型ＮＰＮバイポーラトランジスタＴ２の形成予定領域においては、このＮ型ウエル領域６をコレクタ領域Ｔ２_Cとし、その内側にＰ型不純物を添加することにより、ベース領域となるＰ型半導体層Ｔ２_Bを形成し、更に、その内側にＮ型不純物を添加することにより、エミッタ領域となるＮ型半導体層Ｔ２_Eを形成する。なお、Ｎ型のコレクタ領域Ｔ２_Cには、Ｎ型不純物を更に添加することにより形成された高濃度のＮ型電極層Ｅ_Nが接続されている。なお、エミッタ領域Ｔ２_Eにはポリシリコンからなるエミッタ電極Ｔ２_Eeが設けられている。
【００７３】
すなわち、縦型ＮＰＮバイポーラトランジスタの形成領域においては、Ｐ型不純物ドープ領域５内にＮ型のウエル領域６が形成され、図１に示したトランジスタＴ２は、Ｎ型のウエル領域６をコレクタ領域Ｔ２_Cとし、このコレクタ領域Ｔ２_Cの内側にＰ型のベース領域Ｔ２_B及びＮ型のエミッタ領域Ｔ２_Eが形成されてなる縦型ＮＰＮバイポーラトランジスタＴ２である。このトランジスタＴ２においても、そのＰ型層とＮ型層との界面から広がる空乏層は上記半導体素子隔離領域の少なくとも１つによって、隣接素子への広がりが抑制される。
【００７４】
横型バイポーラトランジスタＴ３の形成予定領域においては、Ｎ型ウエル領域６の一部分をベース領域Ｔ３_Bとし、その横方向両側にＰ型不純物を添加することにより、エミッタ領域及びコレクタ領域となるＰ型半導体層Ｔ３_E，Ｔ３_Cを形成し、Ｎ型ウエル領域６内に、高濃度にＮ型不純物を添加することにより、ベース領域Ｔ３_Bに接続されたＮ型電極層Ｅ_Nを形成する。
【００７５】
横型バイポーラトランジスタの形成領域においては、Ｐ型不純物ドープ領域５内にＮ型のウエル領域６が形成されており、図１に示したトランジスタＴ２は、このＮ型のウエル領域６の一部分をベース領域Ｔ３_Bとし、Ｎ型のウエル領域６内であって、そのベース領域の横方向両側にそれぞれＰ型のエミッタ領域Ｔ３_E及びＰ型のコレクタ領域Ｔ３_Cが形成されてなる横型ＰＮＰバイポーラトランジスタに置換したものである。
【００７６】
また、図１に示したトランジスタＴ２は、Ｐ型不純物ドープ領域５内に形成されたＭＯＳ型トランジスタＴ４に置換してもよい。すなわち、ＣＭＯＳトランジスタＴ４の形成領域においては、Ｎ型ウエル領域６を、直下のＮ＋層２の一部領域のみ上に重なるように形成しており、Ｎ＋層２上のＮ型ウエル領域６内においてはＰチャネルＭＯＳトランジスタ、Ｐ型不純物ドープ領域５内においてはＮチャネルＭＯＳトランジスタが形成される。
【００７７】
上記ＰチャネルＭＯＳトランジスタは、Ｎ型ウエル領域６内の表面層の離隔した２箇所にＰ型不純物を添加することにより、そのソース領域及びゲート領域を構成するＰ型半導体領域Ｔ４_S1，Ｔ４_D1を形成し、Ｎ型ウエル領域６内の所定箇所にＮ型不純物を添加することにより、チャネル層の電位を制御するためのＮ型半導体領域Ｔ４_C1を形成する。
【００７８】
上記ＮチャネルＭＯＳトランジスタは、Ｐ型不純物ドープ領域５内の表面層の離隔した２箇所にＮ型不純物を添加することにより、そのソース領域及びゲート領域を構成するＮ型半導体領域Ｔ４_S2，Ｔ４_D2を形成し、Ｐ型不純物ドープ領域５内の所定箇所にＰ型不純物を添加することにより、チャネル層の電位を制御するためのＰ型半導体領域Ｔ４_C2を形成する。
【００７９】
なお、上記ＭＯＳトランジスタのそれぞれのチャネル層上には絶縁層を介してポリシリコンからなるゲート電極Ｔ４Ｇ₁，Ｔ４Ｇ₂が配置される。また、基板表面全体はＳｉＯ₂からなる保護膜ＰＲＣＴによって被覆されており、保護膜ＰＲＣＴに設けられたスルーホールを介して、上記各半導体層に接続される複数の電極ｅが図示の如く設けられ、各電極ｅの直下には、その下の半導体層とのオーミック接触をとるための高濃度半導体層Ｅ_P，Ｅ_Nが設けられている。また、これらの電極を介して、上述のバイポーラトランジスタとＣＭＯＳトランジスタは、ＰＩＮホトダイオードＰＤの出力を増幅するＢｉ−ＣＭＯＳトランジスタ集積回路を構成するように電気的に接続されている。なお、素子隔離用の半導体領域は対応する電極ｅを介してグランドに接続することができる。
【００８０】
以上、説明したように、図３に示した装置は、図１に示した装置と同一の基本構成を有すると共に、複数種のトランジスタを基板内に備えている。
【００８１】
なお、図３に示す半導体光検出装置において、各半導体の伝導型及び不純物濃度は以下に示す通りであり、これらの不純物濃度の大小関係は以下から一意的に決定される。また、これらの濃度は、各層が不純物の添加によって形成されている場合にはピーク濃度を示すものであり、これは基板表面側に位置する層に関しては表面ピーク濃度に一致する。
【００８２】
【表２】

【００８３】
更に、図１に示したトランジスタＴ２は、その位置と導電型を適当に設定することにより、図３においては、Ｐ型不純物ドープ領域５をコレクタ領域Ｔ１_Cとし、このコレクタ領域５の内側にＮ型のベース領域Ｔ１_B及びＰ型のエミッタ領域Ｔ１_Eが形成されてなる縦型ＰＮＰバイポーラトランジスタＴ１に置換することができ、ＰＮＰバイポーラトランジスタＴ１のコレクタ領域Ｔ１_CはＮ型の第３半導体縦型ＰＮＰ素子分離領域２，６、６（２）によって横方向に囲まれている。
【００８４】
この場合、縦型ＰＮＰトランジスタコレクタ領域Ｔ１と第３半導体素子隔離領域２，６、６（２）の間には低濃度のエピタキシャル半導体層４が残留しているので、これらの間の寄生容量を低減することができる。
【００８５】
また、本実施形態の半導体光検出器は縦型ＰＮＰトランジスタＴ１を備えており、トランジスタＴ１の形成領域内及び近傍において、Ｐ型の高抵抗エピタキシャル半導体層４は、積層された下部及び上部エピタキシャル半導体層４（１），４からなり、トランジスタＴ１の周囲に位置する第２半導体素子隔離領域３は、上部及び下部Ｐ型高抵抗エピタキシャル半導体層４（１），４の間の界面から上部及び下部Ｐ型高抵抗エピタキシャル半導体層４（１），４双方内にＰ型の不純物を拡散することによって形成されると共にＰ型不純物ドープ領域５内に到達しており、前記界面から双方内にＰ型の不純物を拡散することによってトランジスタＴ１の周囲に位置する第２半導体素子隔離領域３と異なる期間に形成されるＰ型埋込半導体層（トランジスタＴ１の形成領域内部に位置するＰ＋層）３がトランジスタＴ１のコレクタ領域Ｔ１_Cに到達している。
【００８６】
この場合、トランジスタＴ１の周囲に位置する第２半導体素子隔離領域３とトランジスタＴ１の形成領域内に位置するＰ型埋込半導体層３の不純物濃度は異なり、このＰ型埋込半導体層３はトランジスタのコレクタ寄生抵抗を低減し縦型ＰＮＰトランジスタの電流増幅率を上げて高速動作を可能にする観点から、このＰ型埋込半導体層３の不純物濃度は第２半導体素子隔離領域３よりも高く設定される。
次に、図３に示した構造の光半導体装置と従来の装置との比較を行う。
【００８７】
図４は本装置と従来の装置との比較を行うための説明図である。図面の左半分が、トランジスタＴ２’を具備した従来の装置の断面構造を示し、右半分が実施形態に係るトランジスタＴ２を具備した装置の断面構造を示す。同図においては、本発明のＰ層３は縦方向に延びており、細部の構成については記載を省略する。
【００８８】
図４（ａ）は正確に拡散が行われた場合、図４（ｂ）は従来技術においてＰ基板との界面に位置するＰ型埋込層の拡散が不十分な場合（拡散距離をａ，ｂで示す）、図４（ｃ）は、この拡散が行き過ぎた場合の装置断面構造を示している。実施形態においては、Ｐ型不純物ドープ領域５の拡散が正確に行われた場合、不十分な場合、行き過ぎた場合を、それぞれ図４（ａ）、図４（ｂ）、図４（ｃ）において示す。
【００８９】
拡散が不十分な場合、従来の装置においては縦方向に延びるＰ＋層が埋め込まれたＰ層に到達せず、高抵抗層エピタキシャル層の隙間を空乏層が広がりパンチスルーして素子隔離をすることができないが、本実施形態の装置においては、Ｐ型不純物ドープ領域５の拡散が浅い場合においても、隔離層３の上部へのせり上がりがあるためＰ型ドープ層と容易につながり良好な素子隔離をすることができる。
【００９０】
拡散が行き過ぎた場合、従来の装置においては埋め込まれたＮ＋層が拡散したＰ層内に埋め込まれるため上部のＮ型エピ層と電気的に分離し、Ｎ＋層が機能しなくなるが、本実施形態の装置においては、Ｎ＋層は縦型ＮＰＮコレクタ埋め込み拡散領域として機能している。また、この構造の場合には、本実施形態の上側のＰ＋層は省略することができる。
【００９１】
以上、説明したように、トランジスタＴの周囲をＰ型の素子隔離領域３で囲み、ＰＩＮホトダイオードＰＤもＮ型のＰＤ周辺カソード領域６で囲み、これらの間にＰ型の素子隔離領域３を介在させる。各素子のＰＮ接合から広がる空乏層は素子隔離領域３によって抑制されるものの、ＰＩＮホトダイオードＰＤにおけるＰ型高抵抗エピタキシャル半導体層４は低濃度であり、トランジスタＴ２の形成領域の周囲においても低濃度の半導体層４が残っているので、Ｐ型高抵抗エピタキシャル半導体層４内において空乏層が広がることで、素子間の寄生容量を小さくすることができ、全体の応答速度を向上させることができる。
【００９２】
また、上述の実施形態に係る半導体光検出装置の利点について説明すると、本装置においては、トランジスタ分離のために、表面から基板若しくは同型の極性領域まで拡散する高濃度Ｐ型層（図４の従来装置におけるＰ＋層）が不要となるので、分離に伴うトランジスタの占有面積を小さくすることができる。
【００９３】
また、本装置においては、埋込用のＰ層３、ウエル用のＰ層を形成する場合において、Ｐ型不純物の拡散の制御精度が低い場合にも素子間分離を行うことができるので、集積回路設計の自由度を向上させることができ、生産の安定性を高めることができる。
【００９４】
また、本装置においては、縦型ＰＮＰバイポーラトランジスタＴ１をＰＩＮホトダイオードＰＤと同時に形成することができる。すなわち、トランジスタＴ１を横方向に囲むＮ型の縦型ＰＮＰ素子分離領域６と、ＰＩＮホトダイオードＰＤの周辺カソード領域６は同一工程で形成することができ、また、トランジスタＴ１のエミッタ領域Ｔ１_EはＰＩＮホトダイオードＰＤのアノード領域１０等と同時に形成することができるので、製造時間を短縮することができる。
【００９５】
また、エピタキシャル半導体層４は、１層又は２層以上とすることができる。
【００９６】
更に、Ｐ型不純物ドープ領域５は深くまで拡散させる必要がないので、加熱に要するコストを削減することができ、また、長時間の熱処理に伴うＮ＋層２の縦方向拡散を抑制することができる。
【００９７】
また、Ｐ型不純物ドープ領域とＰ型の素子隔離領域３が縦方向に連続するように、これらの形成工程を分けてＰ型不純物を拡散させるので、全体の厚み、すなわち、エピタキシャル半導体層４の厚みを大きくすることができ、これにより、ＰＩＮホトダイオードＰＤにおける光感応領域（吸収領域Ｉ層）４を広げ、検出感度を向上させることができる。
【００９８】
また、低濃度のエピタキシャル半導体層４が設けられ、また、これは厚く設定できるので、各素子間の寄生容量（接合容量）、例えば、トランジスタのＮ型埋込層２の接合容量を低減することができる。
【００９９】
【発明の効果】
本発明の半導体光検出装置によれば、応答速度を向上させることができる。
【図面の簡単な説明】
【図１】実施の形態に係る半導体光検出装置の縦断面図である。
【図２】図１に示した半導体光検出装置の更に好適な例を示す当該装置の縦断面図である。
【図３】図１に示した半導体光検出装置の更に好適な別の例を示す当該装置の縦断面図である。
【図４】本装置と従来の装置との比較を行うための説明図である。
【符号の説明】
１…半導体基板、２…Ｎ型埋込層、３…半導体素子隔離領域、４…エピタキシャル半導体層、５…Ｐ型不純物ドープ領域（縦型ＰＮＰトランジスタコレクタ領域）、６…ＰＤ周辺カソード領域（縦型ＰＮＰ素子分離領域）、１０…アノード領域、Ｅ_N…高濃度Ｎ型電極層、Ｅ_P…高濃度Ｐ型電極層、ＰＤ…ＰＩＮホトダイオード、Ｒ１…第１領域、Ｒ２…第２領域、Ｔ…トランジスタ、Ｔ１…縦型ＰＮＰバイポーラトランジスタ、Ｔ１_B…ベース領域、Ｔ１_C…コレクタ領域、Ｔ１_E…エミッタ領域、Ｔ２…縦型ＮＰＮバイポーラトランジスタ、Ｔ２_B…ベース領域、Ｔ２_C…コレクタ領域、Ｔ２_E…エミッタ領域、Ｔ２_Ee…エミッタ電極、Ｔ２´…従来例の縦型ＮＰＮバイポーラトランジスタ、Ｔ３…横型ＰＮＰバイポーラトランジスタ、Ｔ３_B…ベース領域、Ｔ３_C…コレクタ領域、Ｔ３_E…エミッタ領域、Ｔ４…ＣＭＯＳトランジスタ、Ｔ４Ｇ₁，Ｔ４Ｇ₂…ゲート電極、Ｔ４_S1…ソース領域、Ｔ４_D1…ドレイン領域、Ｔ４_S2…ソース領域、Ｔ４_D2…ドレイン領域、ｅ…電極。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor photodetection device provided with a PIN photodiode.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, there has been known a semiconductor photodetector device in which a photodiode and another semiconductor element are integrated on the same semiconductor substrate. The semiconductor photodetection device described in Japanese Patent No. 283914 is formed by integrating a PIN photodiode and an NPN bipolar transistor in the same semiconductor substrate.
[0003]
In the PIN photodiode, an N-type buried diffusion layer is formed on the surface of a P-type semiconductor substrate, a low-concentration P-type epitaxial semiconductor layer is formed thereon, and a high-concentration P-type diffusion is formed on the surface of the P-type epitaxial semiconductor layer. A layer is formed. A high-concentration N-type semiconductor layer for element isolation is continuously formed around the surface region of the N-type buried diffusion layer, and this high-concentration N-type semiconductor layer extends toward the substrate surface. A well-like N-type isolation region is formed as a whole together with the N-type buried diffusion layer. The surface of the semiconductor substrate finally obtained by forming a plurality of layers is simply referred to as the substrate surface.
[0004]
The NPN bipolar transistor is formed next to the PIN photodiode. This NPN bipolar transistor has an N-type semiconductor region as a collector region, and a P-type base region and an N-type emitter region formed therein. A high-concentration N-type buried diffusion layer is formed below the N-type collector region. On the other hand, through the high-concentration N-type semiconductor layer continuous in the substrate thickness direction, the collector potential is on the substrate surface side. Led to.
[0005]
The above NPN bipolar transistors are formed in the P-type semiconductor region. The P-type semiconductor region surrounds the P-type buried diffusion layer interposed between the NPN bipolar transistor and the P-type semiconductor substrate, and the periphery of the surface region of the P-type buried diffusion layer, from here toward the substrate surface. The extended high-concentration P-type semiconductor layer for element isolation. That is, the P-type buried diffusion layer and the high-concentration P-type semiconductor layer for element isolation constitute a well-shaped P-type isolation region as a whole.
[0006]
That is, the PIN photodiode is formed in the well-shaped N-type isolation region as a whole, although the N-type layer (N-type buried diffusion layer) is shared with the well-shaped N-type isolation region. The NPN bipolar transistor is formed in a well-shaped P-type isolation region. An N-type layer is interposed between the well-shaped N-type isolation region and the well-shaped P-type isolation region.
[0007]
[Problems to be solved by the invention]
However, in the semiconductor photodetection device, since the high-concentration element isolation region is in close contact with the transistor, the parasitic capacitance increases and the response speed cannot be improved. The present invention has been made in view of such problems, and an object of the present invention is to provide a semiconductor photodetector device having a structure capable of improving the response speed.
[0008]
[Means for Solving the Problems]
In order to solve the above-described problems, a semiconductor photodetector according to the present invention is formed in a first region while a P-type high-resistance epitaxial semiconductor layer is vertically sandwiched between N-type and P-type semiconductor layers. A PIN photodiode, a P-type impurity doped region formed in the second region by increasing the impurity concentration on the surface side of the epitaxial semiconductor layer in the second region different from the first region, and the P In a semiconductor photodetection device comprising a transistor formed in a doped impurity region and an N-type cathode region laterally surrounding the PIN photodiode, in the epitaxial semiconductor layer between the PIN photodiode and the transistor A P-type barrier that suppresses the spread of a depletion layer extending laterally from the PIN photodiode and the transistor direction. The area is provided, wherein between the isolation region and said PIN photodiode and said transistor, wherein said epitaxial semiconductor layer remains partially.
[0009]
In this device, since a part of the P-type high resistance epitaxial semiconductor layer remains between the isolation region and the PIN photodiode and the transistor, the parasitic capacitance formed by the depletion layer extending from the isolation region and the PIN photodiode is reduced. As a result, these response speeds can be improved.
[0010]
The transistor is a vertical PNP bipolar transistor in which the P-type P-type impurity doped region is used as a collector region, and an N-type base region and a P-type emitter region are formed inside the collector region. The collector region of the PNP bipolar transistor is surrounded by an N-type isolation region and surrounded by an N-type buried layer.
[0011]
In this case, the depletion layer extending from the interface between the N-type base region and the P-type impurity doped region (vertical PNP transistor collector region) is suppressed by the isolation region, thereby preventing punch-through between adjacent elements. Is done. When a low-concentration epitaxial semiconductor layer remains between the transistor and the isolation region, the junction capacitance between the substrate and the element can be reduced.
[0012]
An N-type well region is formed in the P-type impurity doped region, and the transistor has a part of the N-type well region as a base region, and is in the N-type well region in the lateral direction of the base region. It may be a lateral PNP bipolar transistor in which a P-type emitter region and a P-type collector region are formed on both sides, respectively.
[0013]
An N-type well region is formed in the P-type impurity doped region, and the transistor has the N-type well region as a collector region, and a P-type base region and an N-type emitter region are formed inside the collector region. It may be a vertical NPN bipolar transistor.
[0014]
The transistor may be a MOS transistor formed in a P-type impurity doped region.
[0015]
Also, the semiconductor photodetection of the present invention apparatus Is provided with a vertical PNP transistor, the isolation region has a P-type high-resistance epitaxial semiconductor from an interface between the semiconductor substrate on which the P-type high-resistance epitaxial semiconductor layer is formed and the P-type high-resistance epitaxial semiconductor layer. Formed by diffusing P-type impurities in both the layer and the semiconductor substrate and reaching the P-type impurity doped region, and isolating by diffusing P-type impurities into the both from the interface It is preferable that a P-type buried semiconductor layer formed simultaneously with the region reaches the collector region.
[0016]
In this case, the impurity concentration of the isolation region and the P-type buried semiconductor layer is the same. The P-type buried semiconductor layer reduces the collector parasitic resistance of the transistor, increases the current amplification factor, and enables high-speed operation.
[0017]
Also, the semiconductor photodetection of the present invention apparatus Is provided with a vertical PNP transistor, the P-type epitaxial semiconductor layer is composed of stacked lower and upper epitaxial semiconductor layers, and the isolation region is between the upper epitaxial semiconductor layer and the lower epitaxial semiconductor layer. It is formed by diffusing a P-type impurity from the boundary surface into the upper epitaxial semiconductor layer and the lower epitaxial semiconductor layer and reaches the P-type impurity doped region, and the P-type impurity from the boundary surface. A high-concentration P-type buried semiconductor layer formed in a different period from the isolation region by diffusing impurities reaches the collector region of the vertical PNP bipolar transistor.
[0018]
In this case, the impurity concentration of the isolation region and the P type buried semiconductor layer for the vertical PNP transistor collector is different, and the P type buried semiconductor layer for the vertical PNP transistor collector reduces the collector parasitic resistance of the transistor, and From the viewpoint of increasing the current amplification factor and aiming at a structure capable of high-speed operation, the impurity concentration of the P-type buried semiconductor layer for the vertical PNP transistor collector is set higher than that of the isolation region.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
The semiconductor photodetection device according to the embodiment will be described below. The same reference numerals are used for the same elements, and redundant description is omitted.
[0020]
FIG. 1 is a longitudinal sectional view of a semiconductor photodetection device according to an embodiment. Note that description of electrodes and protective films connected to each semiconductor is omitted.
[0021]
In this apparatus, an N-type buried semiconductor layer (third semiconductor vertical length) is formed in the entire region in the first region R1 in the surface region of the P-type semiconductor substrate 1 and in a partial region of the second region R2 surrounding the first region R1. A lower part of the type PNP element isolation region (hereinafter referred to as N + layer) 2 is formed. Further, a P-type buried semiconductor layer (second semiconductor element isolation region (isolation region) is formed in the surface region of the P-type semiconductor substrate 1 in the vicinity of the boundary between the first region R1 and the second region R2 and in a specific region in the second region R2. ): Hereinafter, P layer 3 is formed.
[0022]
This semiconductor photodetection device uses Si as a semiconductor, and “high concentration” means an impurity concentration of 1 × 10 6. ¹⁸ / Cm ^Three In the drawing, “+” is attached to the conductivity type, and “low concentration” means an impurity concentration of 1 × 10 ¹⁵ / Cm ^Three In the drawing, “−” is attached to the conductivity type and shown. Further, “vertical direction” is the thickness direction of the semiconductor substrate 1, and “lateral direction” means a direction orthogonal to the vertical direction.
[0023]
First, the first region R1 will be described. On the surface of the semiconductor substrate 1 on which the embedded semiconductor layers 2 and 3 are formed, a low concentration P-type epitaxial semiconductor layer 4 is formed. A high-concentration P-type semiconductor layer (hereinafter referred to as P + layer) 10 is formed in the surface region of the first region R1 of the epitaxial semiconductor layer 4, and an N + layer (cathode) 2 that continues vertically in the first region R1. The epitaxial semiconductor layer 4 and the P + layer (anode) 10 constitute a PIN photodiode. A first semiconductor element isolation region (cathode region) 6 made of an N-type semiconductor is connected to the N + layer 2 toward the substrate surface side so as to surround the PIN photodiode PD in the lateral direction.
[0024]
The N-type first semiconductor photodiode peripheral cathode region 6 has a higher impurity concentration than the epitaxial semiconductor layer 4, transmits a bias potential to the N + layer 2, and promotes depletion of the P-type high-resistance epitaxial semiconductor layer 4. is doing.
[0025]
Next, the second region R2 will be described. A P-type impurity doped region 5 is formed on the surface side of the epitaxial semiconductor layer 4 in the second region R2. A transistor T2 is formed in the P-type impurity doped region 5. Since the transistor T2 has a PN junction, the depletion layer also diffuses laterally from this junction interface.
[0026]
The P layer 3 previously formed on the semiconductor substrate 1 side is diffused in the vertical direction by heat treatment, so that the depletion layer spreads from the PN junction interface adjacent to the transistor T2 or the P-type impurity doped region 5 in the horizontal direction. And punch-through in the lateral direction of the depletion layer is suppressed. A part of the low-concentration P-type epitaxial semiconductor layer 4 is located between the P layer 3 and the transistor T2, and since the P layer 3 is not in direct contact with the transistor T2, the parasitic capacitance between them is reduced. Thus, the response speed of the transistor T2 can be improved.
[0027]
In addition, since the P-type high-resistance epitaxial semiconductor layer 4 is also interposed between the PIN photodiode PD and the P layer 3, it is possible to reduce the parasitic capacitance between them and improve the response speed of the PIN photodiode PD. it can.
[0028]
At a specific position in the P-type impurity doped region 5, an N-type semiconductor layer (an upper portion of the third semiconductor element isolation region, an N-type well region) 6 separated from the transistor T2 with the P-type impurity doped region 5 interposed therebetween. Is provided. In this example, the transistor T2 is formed in the N-type semiconductor layer 6. However, when the transistor is a vertical PNP bipolar transistor, this is different from the semiconductor layer 6 in the P-type impurity doped region 5. It is formed at a dislocated position.
[0029]
The N-type semiconductor layer 6 is continuous with the N + layer 2 previously formed in the P-type semiconductor substrate 1, and further suppresses the lateral expansion of the depletion layer generated from the transistor T2. Of course, a PN junction is formed between the N-type third semiconductor element isolation regions 2 and 6 and the P-type semiconductor substrate 1 and the P-type impurity doped region 5. It is blocked by the high concentration P layer 3.
[0030]
The PIN photodiode PD and the transistor T2 are connected by a wiring (not shown). When this apparatus is used, a reverse bias voltage is applied to the PIN photodiode PD, and the output current of the PIN photodiode PD is constituted by the transistor T2 and the like. Amplified by preamplifier. For the preamplifier, a bipolar transistor of T1, T2, T3 and / or a field effect transistor of T4 can be used.
[0031]
Next, the manufacturing method of this apparatus is demonstrated. This device is manufactured by sequentially performing the following steps (1) to (12).
[0032]
(1) A P-type semiconductor substrate 1 is prepared.
[0033]
(2) A mask in which a region where the N + layer 2 is to be formed is opened is formed on the surface of the semiconductor substrate 1. In this step or the following steps, the mask is formed using a normal photolithography technique.
[0034]
(3) An N-type impurity is added into the surface layer of the semiconductor substrate 1 in the region where the N + layer 2 is to be formed. In this addition step and the following N-type impurity addition step, a diffusion method or an ion implantation method can be used. In this step and the following steps, “Sb (antimony)” is used as an impurity added as an N-type impurity. Note that the conductivity type of the surface layer region is reversed by addition of impurities.
[0035]
(4) A mask having an opening in a region where the P layer 3 is to be formed is formed on the surface of the semiconductor substrate 1.
[0036]
(5) A P-type impurity is added into the surface layer of the semiconductor substrate 1 in the region where the P layer 3 is to be formed. In this addition step and the following P-type impurity addition step, a diffusion method or an ion implantation method can be used. In this step and the following steps, “B (boron)” is used as an impurity added as a P-type impurity.
[0037]
(6) After the step (5) or after each of the steps (3) and (5), the semiconductor substrate 1 is annealed to activate the added impurities.
[0038]
(7) A P-type epitaxial semiconductor layer 4 is grown on the surface of the semiconductor substrate 1. The impurity concentration of the epitaxial layer is desirably as low as possible within a range where the polarity is stably maintained. ¹⁵ / Cm ² Below.
[0039]
(8) A mask that covers the first region R1 where the PIN photodiode PD is to be formed and is opened in the second region R2 is formed on the epitaxial semiconductor layer 4, and P is formed in the surface layer region in the second region R2. A p-type well region 5 is formed by adding type impurities.
[0040]
(9) A mask having a region in which the element isolation region 6 is to be formed is formed on the epitaxial semiconductor layer 4, and an N-type impurity is added to the region to be formed to form the element isolation region 6.
[0041]
(10) After the step (8) or after each of the steps (8) and (9), the semiconductor substrate 1 is annealed to activate the added impurities.
[0042]
(11) A mask in which a region where the P + layer (anode) 10 is to be formed is opened is formed on the P-type high-resistance epitaxial semiconductor layer 4, and a P-type impurity is added into the region to be formed to form the P + layer 10. . The vertical PNP transistor is formed in the P-type impurity doped region in accordance with a normal formation method. The transistors T2 other than the vertical PNP transistor are formed in the N-type layer 6.
[0043]
(12) The semiconductor substrate 1 is annealed to activate the added impurities, and then a protective film and electrodes (not shown) are formed to complete the apparatus.
[0044]
The P-type impurity doped region 5 and the P layer 3 are diffused in the vertical direction and are continuous by the above-described annealing multiple times. In addition, the N-type semiconductor layer 6 and the N + layer 2 are also diffused in the vertical direction by the above-described annealing multiple times and are continuous.
[0045]
As described above, the semiconductor photodetection device includes the P-type epitaxial semiconductor layer 4 vertically sandwiched between the N-type and P-type semiconductor layers 2 and 10 and the PIN formed in the first region R1. A photodiode PD and a P-type impurity doped region 5 formed in the second region R2 by increasing the impurity concentration on the surface side of the epitaxial semiconductor layer 4 in the second region R2 different from the first region R1, A semiconductor comprising a transistor T2 formed in the P-type impurity doped region 5, in particular, an N-type semiconductor layer 6, and an N-type first semiconductor photodiode peripheral cathode region 6 that laterally surrounds the PIN photodiode PD. In the photodetector, in the epitaxial semiconductor layer 4 between the PIN photodiode PD and the transistor T2, the PIN photodiode PD and A P-type second semiconductor element isolation region 3 that suppresses the spread of a depletion layer extending laterally from the direction of the transistor T2 is provided, and an epitaxial semiconductor layer is provided between the second semiconductor element isolation region 3 and the PIN photodiode PD and transistor T2. A part of 4 remains.
[0046]
Here, the isolation region 3 does not mean PN junction isolation, but means a region where the impurity concentration is increased in the low concentration layer in order to suppress the spread of the depletion layer in the high resistance portion, and the power supply voltage is applied. Even if punch through does not occur, it is moderate (1x10 ¹⁵ /cm ^Three ) The above impurity concentration layer.
[0047]
In this apparatus, since a part of the P-type high resistance epitaxial semiconductor layer 4 remains between the second semiconductor element isolation region 3 and the PIN photodiode PD and the transistor T2, the second semiconductor element isolation region 3 and the PIN photodiode PD are separated from each other. The parasitic capacitance formed by the spreading depletion layer is reduced, and the response speed can be improved.
[0048]
In this example, the transistor T2 is formed in the N-type semiconductor layer 6. However, instead of the transistor T2, the transistor T2 is formed at a position away from the semiconductor layer 6 in the P-type impurity doped region 5. In the case of using T1: see FIG. 2, a vertical PNP bipolar structure in which a P-type impurity doped region 5 is used as a collector region, and an N-type base region and a P-type emitter region are formed inside the collector region 5. The collector region of the PNP bipolar transistor is preferably surrounded by the N-type third semiconductor vertical PNP element isolation regions 6 and 2 in the lateral direction.
[0049]
In this case, since the low-concentration epitaxial semiconductor layer 4 remains between the vertical PNP transistor collector region and the third semiconductor vertical PNP element isolation regions 6, 2, the parasitic capacitance between them is reduced. be able to. In addition, although the P-type high resistance epitaxial semiconductor layer 4 shown in the figure is one layer, this may be two or more layers.
[0050]
FIG. 2 is a longitudinal sectional view of the semiconductor photodetection device shown in FIG.
[0051]
Since the basic structure of the apparatus is substantially the same as that shown in FIG. 1, the structure of the apparatus will be described together with the manufacturing method of the apparatus.
[0052]
In this device, a PIN photodiode PD, a vertical PNP bipolar transistor T1, and a vertical NPN transistor T2 are formed on the same semiconductor substrate 1. The structure of the PIN photodiode PD is the same as that of FIG. 1 except that the impurity concentration in the surface central region of the anode region 10 is lower than the surroundings.
[0053]
In the semiconductor photodetector shown in FIG. 2, the conductivity type and impurity concentration of each semiconductor are as shown below, and the magnitude relationship between these impurity concentrations is uniquely determined from the following. These concentrations indicate peak concentrations when each layer is formed by addition of impurities, and this corresponds to the surface peak concentration for the layer located on the substrate surface side.
[0054]
[Table 1]

[0055]
The transistor T2 shown in FIG. 1 is a vertical NPN bipolar transistor. A transistor T1 adjacent to the transistor T1 is a vertical PNP bipolar transistor T1. In the formation region of the transistor T1, the P-type well region 5 is used as the collector region T1. _C By adding an N-type impurity in the surface layer, the base region T1 _B A high-concentration N-type semiconductor layer is formed, and a P-type impurity is further added to the inside thereof to thereby form an emitter region T1. _E A high-concentration P-type semiconductor layer is formed. Further, in the transistor formation region, the p layer 3 shown in FIG. 1 is a P + layer 3 extending in the vertical direction, and the P + layer 3 is an N + layer 2 at the interface between the substrate 1 and the P-type well region 5. It is divided up and down by.
[0056]
A vertical NPN bipolar transistor T2 is formed adjacent to the vertical PNP bipolar transistor T1. In the transistor formation region, an N-type well region 6 is formed in the P-type impurity doped region 5 so as to be continuous with the lower N + layer 2, and this N-type well region 6 is used as a collector region T2. _C By adding a P-type impurity in the surface layer, the base region T2 _B A high-concentration P-type semiconductor layer is formed, and an N-type impurity is added to the inside of the P-type semiconductor layer. _E A high concentration N-type semiconductor layer is formed.
[0057]
The substrate surface is SiO ₂ A plurality of electrodes e which are covered with a protective film (oxide film) PRCT made of and connected to each of the semiconductor layers through through holes provided in the protective film PRCT are provided as shown in the figure. Immediately below is a high-concentration semiconductor layer E for making ohmic contact with the underlying semiconductor layer. _P , E _N Is provided.
[0058]
Further, in the semiconductor photodetector of the present embodiment, the second semiconductor element isolation region 3 located so as to surround the periphery of the vertical PNP transistor T1 in the formation region thereof is the P-type high resistance epitaxial semiconductor layer. 4 is formed by diffusing P-type impurities into both the epitaxial semiconductor layer 4 and the semiconductor substrate 1 from the interface between the semiconductor substrate 1 and P-type high-resistance epitaxial semiconductor layer 4 formed thereon. The transistor T1 that reaches the P-type impurity doped region 5 and is formed simultaneously with the second semiconductor element isolation region 3 located around the transistor T1 by diffusing P-type impurities into both of the interfaces from the interface The P type buried semiconductor layer 3 in the formation region of the vertical PNP transistor collector region T1 _C Has reached.
[0059]
In this case, the impurity concentrations of the second semiconductor element isolation region 3 located around the transistor T1 and the P-type buried semiconductor layer 3 located in the formation region of the transistor T1 are the same. This P-type buried semiconductor layer 3 reduces the collector parasitic resistance of the transistor, increases the current amplification factor, and enables high-speed operation.
[0060]
In this example, the epitaxial semiconductor layer 4 is a single layer, but it may be two or more layers. Hereinafter, such an example will be described.
[0061]
FIG. 3 is a longitudinal sectional view of another preferred example of the semiconductor photodetector shown in FIG.
[0062]
Since the basic structure of the apparatus is substantially the same as that shown in FIG. 1, the structure of the apparatus will be described together with the manufacturing method of the apparatus.
[0063]
In this device, in addition to a PIN photodiode PD, a vertical PNP bipolar transistor T1, a vertical NPN transistor T2, a horizontal PNP transistor T3, and a CMOS transistor T4 are formed on the same semiconductor substrate 1.
[0064]
In this device, the region other than the region where the PIN photodiode PD is formed and the region where the vertical PNP bipolar transistor T1 is formed is the same as the semiconductor substrate 1 of the above-described device, the low-concentration P-type semiconductor substrate 1 ′ and the substrate. This is read as a low-concentration P-type epitaxial semiconductor layer 4 grown on 1 ′.
[0065]
Note that such reading is not performed in a region where the PIN photodiode PD is formed and a region where the vertical PNP bipolar transistor T1 is formed. First, these areas will be described. In addition, the code | symbol in parenthesis shows about the element at the time of replacing.
[0066]
First, an N-type impurity is added to the surface layer of the semiconductor substrate 1 to form an N + layer 2. Next, the lower epitaxial semiconductor layer 4 (1) is grown on the semiconductor substrate 1. Further, an N-type semiconductor layer 6 extending from the surface of the epitaxial semiconductor layer 4 (1) to the deep part and reaching the N + layer 2 by final diffusion is formed by adding an N-type impurity. Further, a P layer 3 and a high-concentration N + layer 6 (2) that is finally connected to the N-type semiconductor layer 6 are formed in the surface layer of the P-type high-resistance epitaxial semiconductor layer 4 (1). To do.
[0067]
Subsequently, the upper P-type high-resistance epitaxial semiconductor layer 4 is formed on the lower P-type high-resistance epitaxial semiconductor layer 4 (1). Next, a P-type impurity doped region 5 is formed in the second region R2 of the upper epitaxial semiconductor layer 4. An N-type impurity is added to the surface layer of the P-type impurity doped region 5 in the region where the PNP bipolar transistor T1 is to be formed, and an N-type semiconductor layer T1 serving as a base region _B Form. Thereafter, the N-type semiconductor layer T1 _B A P-type impurity is added therein to form a P-type semiconductor layer T1 serving as an emitter region. _E Form. Note that the N-type semiconductor layer T1 serving as the base region _B The P-type impurity doped region 5 located around the P region functions as a collector region of the transistor, and the collector region portion of the P-type impurity doped region 5 has a high-concentration P-type electrode layer E. _P Is connected.
[0068]
This P-type electrode layer E _P Is a P + layer (anode) formed in the surface layer of the epitaxial semiconductor layer 4 and another P-type electrode layer E located in a P-type impurity doped region between the PIN photodiode PD and the transistor T1. _P At the same time, this formation is performed by adding a P-type impurity to these regions and annealing the substrate.
[0069]
By the annealing process used in the above steps, the N-type layers 2, 6, 6 (2) in the first region R 1 are continuous in the vertical direction, and the P-type layer 3 in the other region reaches the substrate 1. It will be. Note that the P + layer 3 located immediately below the PNP bipolar transistor T1 has a higher impurity concentration and a shallower diffusion depth than the P layer 3 formed in other regions, and these are formed in separate steps.
[0070]
Next, when the semiconductor substrate 1 of the apparatus shown in FIG. 1 is replaced with a low-concentration P-type semiconductor substrate 1 ′ and a low-concentration P-type epitaxial semiconductor layer 4 grown on the substrate 1 ′. That is, the formation of the transistors T2, T3, and T4 will be described.
[0071]
In this case, since the semiconductor substrate 1 has already been formed, the N + layer 2 and the P layer 3 are formed between the functional elements, and then the upper epitaxial semiconductor layer 4 is formed on the semiconductor substrate 1, and then Then, a P-type impurity doped region 5 is formed. In the P-type impurity doped region 5, an N layer (N-type well region) 6 is formed so as to overlap the N + layer 2.
[0072]
In the region where the vertical NPN bipolar transistor T2 is to be formed, this N-type well region 6 is used as the collector region T2. _C And by adding a P-type impurity inside the P-type semiconductor layer T2 serving as a base region _B And an N-type impurity is added to the inside of the N-type semiconductor layer T2 to form an emitter region. _E Form. Note that the N-type collector region T2 _C Includes a high-concentration N-type electrode layer E formed by further adding an N-type impurity. _N Is connected. The emitter region T2 _E Includes an emitter electrode T2 made of polysilicon. _Ee Is provided.
[0073]
That is, in the formation region of the vertical NPN bipolar transistor, an N-type well region 6 is formed in the P-type impurity doped region 5, and the transistor T2 shown in FIG. _C And this collector region T2 _C P-type base region T2 inside _B And N-type emitter region T2 _E Is a vertical NPN bipolar transistor T2. Also in this transistor T2, the depletion layer extending from the interface between the P-type layer and the N-type layer is prevented from spreading to adjacent elements by at least one of the semiconductor element isolation regions.
[0074]
In the region where the lateral bipolar transistor T3 is to be formed, a part of the N-type well region 6 is part of the base region T3. _B And by adding a P-type impurity to both sides in the lateral direction, a P-type semiconductor layer T3 that becomes an emitter region and a collector region _E , T3 _C And the base region T3 is added to the N-type well region 6 by adding an N-type impurity at a high concentration. _B N-type electrode layer E connected to _N Form.
[0075]
In the formation region of the lateral bipolar transistor, an N-type well region 6 is formed in the P-type impurity doped region 5, and the transistor T2 shown in FIG. T3 _B P-type emitter regions T3 in the N-type well region 6 on both lateral sides of the base region. _E And P-type collector region T3 _C This is replaced with a lateral PNP bipolar transistor in which is formed.
[0076]
The transistor T2 shown in FIG. 1 may be replaced with a MOS transistor T4 formed in the P-type impurity doped region 5. That is, in the formation region of the CMOS transistor T4, the N-type well region 6 is formed so as to overlap only a partial region of the N + layer 2 immediately below, and in the N-type well region 6 on the N + layer 2 Is a P-channel MOS transistor, and an N-channel MOS transistor is formed in P-type impurity doped region 5.
[0077]
In the P-channel MOS transistor, a P-type semiconductor region T4 constituting a source region and a gate region is formed by adding a P-type impurity to two spaced apart portions of the surface layer in the N-type well region 6. _S1 , T4 _D1 And an N-type semiconductor region T4 for controlling the potential of the channel layer by adding an N-type impurity to a predetermined location in the N-type well region 6 _C1 Form.
[0078]
In the N-channel MOS transistor, an N-type semiconductor region T4 constituting a source region and a gate region is formed by adding an N-type impurity to two spaced apart portions of the surface layer in the P-type impurity doped region 5. _S2 , T4 _D2 And a P-type semiconductor region T4 for controlling the potential of the channel layer by adding a P-type impurity to a predetermined location in the P-type impurity doped region 5 _C2 Form.
[0079]
A gate electrode T4G made of polysilicon is formed on each channel layer of the MOS transistor via an insulating layer. ₁ , T4G ₂ Is placed. The entire substrate surface is SiO ₂ A plurality of electrodes e connected to each of the semiconductor layers through through-holes provided in the protective film PRCT are provided as shown in the figure, and directly below each electrode e. High-concentration semiconductor layer E for making ohmic contact with the underlying semiconductor layer _P , E _N Is provided. Further, the bipolar transistor and the CMOS transistor described above are electrically connected via these electrodes so as to constitute a Bi-CMOS transistor integrated circuit that amplifies the output of the PIN photodiode PD. The semiconductor region for element isolation can be connected to the ground via the corresponding electrode e.
[0080]
As described above, the device shown in FIG. 3 has the same basic configuration as the device shown in FIG. 1 and includes a plurality of types of transistors in the substrate.
[0081]
In the semiconductor photodetector shown in FIG. 3, the conductivity type and impurity concentration of each semiconductor are as shown below, and the magnitude relationship between these impurity concentrations is uniquely determined from the following. These concentrations indicate peak concentrations when each layer is formed by addition of impurities, and this corresponds to the surface peak concentration for the layer located on the substrate surface side.
[0082]
[Table 2]

[0083]
Further, the transistor T2 shown in FIG. 1 has a P-type impurity doped region 5 as a collector region T1 in FIG. 3 by appropriately setting its position and conductivity type. _C And an N-type base region T1 inside the collector region 5 _B And P-type emitter region T1 _E Can be replaced by a vertical PNP bipolar transistor T1, and a collector region T1 of the PNP bipolar transistor T1. _C Is laterally surrounded by N-type third semiconductor vertical PNP element isolation regions 2, 6, 6 (2).
[0084]
In this case, since the low-concentration epitaxial semiconductor layer 4 remains between the vertical PNP transistor collector region T1 and the third semiconductor element isolation regions 2, 6, 6 (2), the parasitic capacitance between them is reduced. Can be reduced.
[0085]
In addition, the semiconductor photodetector of this embodiment includes a vertical PNP transistor T1, and the P-type high-resistance epitaxial semiconductor layer 4 is formed by stacking the lower and upper epitaxial semiconductor layers in and near the formation region of the transistor T1. The second semiconductor element isolation region 3 consisting of the layers 4 (1) and 4 and located around the transistor T1 is located above and below the interface between the upper and lower P-type high resistance epitaxial semiconductor layers 4 (1) and 4. It is formed by diffusing P-type impurities in both of the P-type high-resistance epitaxial semiconductor layers 4 (1), 4 and reaches the P-type impurity doped region 5, and P-type is introduced into both from the interface. P type buried semiconductor layer (transistor) formed in a different period from the second semiconductor element isolation region 3 located around the transistor T1 by diffusing impurities of Located inside formation region of register T1 P + layer) 3 is the collector region T1 of the transistor T1 _C Has reached.
[0086]
In this case, the impurity concentration of the second semiconductor element isolation region 3 located around the transistor T1 and the P-type buried semiconductor layer 3 located in the formation region of the transistor T1 are different. The impurity concentration of the P-type buried semiconductor layer 3 is set higher than that of the second semiconductor element isolation region 3 from the viewpoint of reducing the collector parasitic resistance of the transistor and increasing the current amplification factor of the vertical PNP transistor to enable high-speed operation. Is done.
Next, the optical semiconductor device having the structure shown in FIG. 3 is compared with a conventional device.
[0087]
FIG. 4 is an explanatory diagram for comparing the present apparatus with a conventional apparatus. The left half of the drawing shows the cross-sectional structure of a conventional device including the transistor T2 ′, and the right half shows the cross-sectional structure of the device including the transistor T2 according to the embodiment. In the figure, the P layer 3 of the present invention extends in the vertical direction, and the detailed configuration is not described.
[0088]
4A shows a case where diffusion is performed accurately, and FIG. 4B shows a case where the diffusion of the P-type buried layer located at the interface with the P substrate is insufficient in the prior art (the diffusion distance is a, FIG. 4 (c) shows a cross-sectional structure of the device when this diffusion is excessive. In the embodiment, the case where the diffusion of the P-type impurity doped region 5 is performed accurately, the case where it is insufficient, and the case where it goes too far are shown in FIGS. 4A, 4B and 4C, respectively. Show.
[0089]
In the case of insufficient diffusion, the conventional device does not reach the P layer in which the P + layer extending in the vertical direction is buried, and the depletion layer spreads through the gap between the high-resistance layer epitaxial layers, thereby isolating the element. However, in the apparatus according to the present embodiment, even when the diffusion of the P-type impurity doped region 5 is shallow, there is a rise to the upper part of the isolation layer 3, so that it is easily connected to the P-type doped layer and has good element isolation. Can do.
[0090]
In the case where diffusion is excessive, in the conventional device, the embedded N + layer is embedded in the diffused P layer, so that it is electrically separated from the upper N-type epi layer, and the N + layer does not function. In this device, the N + layer functions as a vertical NPN collector buried diffusion region. In the case of this structure, the upper P + layer of this embodiment can be omitted.
[0091]
As described above, the periphery of the transistor T is surrounded by the P-type element isolation region 3, the PIN photodiode PD is also surrounded by the N-type PD peripheral cathode region 6, and the P-type element isolation region 3 is interposed therebetween. Let Although the depletion layer extending from the PN junction of each element is suppressed by the element isolation region 3, the P-type high-resistance epitaxial semiconductor layer 4 in the PIN photodiode PD has a low concentration, and a low concentration is also present around the region where the transistor T2 is formed. Since the semiconductor layer 4 remains, the depletion layer expands in the P-type high-resistance epitaxial semiconductor layer 4, thereby reducing the parasitic capacitance between the elements and improving the overall response speed.
[0092]
Further, the advantages of the semiconductor photodetection device according to the above-described embodiment will be described. In this device, a high-concentration P-type layer that diffuses from the surface to the substrate or the same type polar region for transistor isolation (conventional FIG. 4). Since the P + layer in the device is not necessary, the area occupied by the transistor accompanying the separation can be reduced.
[0093]
Further, in this apparatus, when the buried P layer 3 and the well P layer are formed, element isolation can be performed even when the control accuracy of P-type impurity diffusion is low. The degree of freedom in circuit design can be improved, and production stability can be improved.
[0094]
In the present apparatus, the vertical PNP bipolar transistor T1 can be formed simultaneously with the PIN photodiode PD. That is, the N-type vertical PNP element isolation region 6 that laterally surrounds the transistor T1 and the peripheral cathode region 6 of the PIN photodiode PD can be formed in the same process, and the emitter region T1 of the transistor T1. _E Can be formed at the same time as the anode region 10 of the PIN photodiode PD, and the manufacturing time can be shortened.
[0095]
Moreover, the epitaxial semiconductor layer 4 can be made into one layer or two layers or more.
[0096]
Further, since it is not necessary to diffuse the P-type impurity doped region 5 deeply, the cost required for heating can be reduced, and the vertical diffusion of the N + layer 2 due to the long-time heat treatment can be suppressed. .
[0097]
Further, since the P-type impurity is diffused by dividing these formation steps so that the P-type impurity doped region and the P-type element isolation region 3 are continuous in the vertical direction, the total thickness, that is, the epitaxial semiconductor layer 4 The thickness can be increased, whereby the photosensitive region (absorption region I layer) 4 in the PIN photodiode PD can be expanded and the detection sensitivity can be improved.
[0098]
Further, a low-concentration epitaxial semiconductor layer 4 is provided and can be set thick, so that the parasitic capacitance (junction capacitance) between the elements, for example, the junction capacitance of the N-type buried layer 2 of the transistor is reduced. Can do.
[0099]
【The invention's effect】
According to the semiconductor photodetection device of the present invention, the response speed can be improved.
[Brief description of the drawings]
FIG. 1 is a longitudinal sectional view of a semiconductor photodetection device according to an embodiment.
FIG. 2 is a vertical sectional view of the semiconductor photodetection device shown in FIG. 1 showing a more preferable example.
FIG. 3 is a longitudinal sectional view of another preferred example of the semiconductor photodetector shown in FIG. 1;
FIG. 4 is an explanatory diagram for comparing the present apparatus with a conventional apparatus.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... N type buried layer, 3 ... Semiconductor element isolation region, 4 ... Epitaxial semiconductor layer, 5 ... P type impurity doped region (vertical PNP transistor collector region), 6 ... PD peripheral cathode region (vertical) Type PNP element isolation region), 10... Anode region, E _N ... High-concentration N-type electrode layer, E _P ... high concentration P-type electrode layer, PD ... PIN photodiode, R1 ... first region, R2 ... second region, T ... transistor, T1 ... vertical PNP bipolar transistor, T1 _B ... Base region, T1 _C ... Collector area, T1 _E ... emitter region, T2 ... vertical NPN bipolar transistor, T2 _B ... Base region, T2 _C ... Collector area, T2 _E ... emitter region, T2 _Ee ... emitter electrode, T2 '... conventional vertical NPN bipolar transistor, T3 ... horizontal PNP bipolar transistor, T3 _B ... Base region, T3 _C ... Collector area, T3 _E ... Emitter region, T4 ... CMOS transistor, T4G ₁ , T4G ₂ ... Gate electrode, T4 _S1 ... Source region, T4 _D1 ... Drain region, T4 _S2 ... Source region, T4 _D2 ... drain region, e ... electrode.

Claims (7)

A PIN photodiode formed in the first region while sandwiching a P-type high-resistance epitaxial semiconductor layer in the vertical direction between the N-type and P-type semiconductor layers, and the second photodiode in the second region different from the first region By increasing the impurity concentration on the surface side of the epitaxial semiconductor layer, a P-type impurity doped region formed in the second region, a transistor formed in the P-type impurity doped region, and the PIN photodiode in the lateral direction In a semiconductor photodetection device comprising an N-type cathode region surrounded by
A P-type isolation region is provided in the epitaxial semiconductor layer between the PIN photodiode and the transistor to suppress the depletion layer extending laterally from the PIN photodiode and the transistor direction, and the isolation region and the PIN A semiconductor photodetector according to claim 1, wherein a portion of the epitaxial semiconductor layer remains between the photodiode and the transistor.   The transistor is a vertical PNP bipolar transistor in which the P-type impurity doped region is used as a collector region, and an N-type base region and a P-type emitter region are formed inside the collector region. The semiconductor photodetector according to claim 1, wherein the collector region is laterally surrounded by an N-type isolation region.   An N-type well region is formed in the P-type impurity doped region, and the transistor has a part of the N-type well region as a base region, and is located in the N-type well region and next to the base region. 2. The semiconductor photodetection device according to claim 1, which is a lateral PNP bipolar transistor in which a P-type emitter region and a P-type collector region are formed on both sides in the direction.   An N-type well region is formed in the P-type impurity doped region, and the transistor has the N-type well region as a collector region of an NPN bipolar transistor, and a P-type base region and an N-type region inside the collector region. 2. The semiconductor photodetection device according to claim 1, wherein the semiconductor photodetection device is a vertical NPN bipolar transistor in which an emitter region is formed.   2. The semiconductor photodetection device according to claim 1, wherein the transistor is a MOS transistor formed in the P-type impurity doped region. The isolation region is formed by diffusing P-type impurities in both the epitaxial semiconductor layer and the semiconductor substrate from an interface between the semiconductor substrate on which the epitaxial semiconductor layer is formed and the epitaxial semiconductor layer. Formed and has reached the P-type impurity doped region,
A P-type buried semiconductor layer formed simultaneously with the isolation region by diffusing P-type impurities into the both from the interface reaches the collector region of the vertical PNP bipolar transistor. The semiconductor photodetection device according to claim 2. The P-type epitaxial semiconductor layer includes a stacked lower and upper epitaxial semiconductor layers,
The isolation region is formed by diffusing P-type impurities into the upper epitaxial semiconductor layer and the lower epitaxial semiconductor layer from the interface between the upper epitaxial semiconductor layer and the lower epitaxial semiconductor layer, and the P Reaching the type impurity doped region,
A high-concentration P-type buried semiconductor layer formed in a different period from the isolation region by diffusing the P-type impurity from the boundary surface reaches the collector region of the vertical PNP bipolar transistor. The semiconductor photodetection device according to claim 2.

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