JP4641573B2 - Dry etching method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
In the present invention, W (tungsten), WSi ₂ In particular, the present invention relates to a method of dry etching a laminated layer in which a W-based conductive material layer such as (tungsten silicide) is overlaid on a poly-Si (silicon) layer or a single layer of a W-based conductive material, and a Cl (chlorine) -containing gas and O ₂ After the W-based conductive material layer is just etched by dry etching using a mixed gas with (oxygen) gas as an etching gas, an over-etching is performed by adding a Br (bromine) -containing gas or an I (iodine) -containing gas to the mixed gas. By doing so, it is possible to ensure an anisotropic shape and reduce etching damage.
[0002]
[Prior art]
Conventionally, WSi ₂ As a wiring forming method using a laminate (W polycide layer) in which a layer is superposed on a poly-Si layer, a method as shown in FIGS. 11 to 13 is known (see, for example, JP-A-7-94469).
[0003]
In the process of FIG. 11, the poly-Si layer 3 and the WSi are formed on the gate oxide film 2 covering the surface of the silicon substrate 1. ₂ After sequentially depositing layer 4, WSi ₂ Resist layers 5a to 5d are formed on the layer 4 by photolithography. The resist layers 5a and 5b are arranged at a large interval in the sparse pattern region a, and the resist layers 5b to 5d are arranged at a small interval in the dense pattern region b.
[0004]
In the process of FIG. 12, F (fluorine) containing gas (for example, S ₂ F ₆ Gas etching) using poly-Si layer 3 and WSi ₂ The stack of the layers 4 is just etched in the sparse pattern region a so that the thickness becomes zero or a value in the vicinity thereof. As a result, WSi having a pattern corresponding to each of the resist layers 5a to 5d. ₂ Layers 4a-4d remain. Further, in the dense pattern region b, the etching rate is reduced due to the so-called RIElag phenomenon (or microloading effect), so that the etched portion of the poly Si layer 3 is compared with the etched portion 3e of the poly Si layer 3 in the sparse pattern region a. 3f remains thick.
[0005]
In the process of FIG. 13, Br-containing gas (for example, HBr gas) and O ₂ Overetching is performed by plasma etching using a mixed gas of gas to remove portions to be etched such as 3e and 3f in the poly-Si layer 3. Br gas such as HBr and O ₂ Plasma etching using a gas mixture with gas has high selectivity of the poly-Si layer 3 with respect to the gate oxide film 2. As a result of the over-etching, poly Si layers 3a to 3d having patterns respectively corresponding to the resist layers 5a to 5d remain. At the time of over-etching, the reaction product adhering to the pattern side wall becomes WSi. ₂ Since side etching of the layers 4a to 4d and the poly-Si layers 3a to 3d is suppressed, it is possible to give an anisotropic shape to the stack of 4a / 3a, 4b / 3b, 4c / 3c, 4d / 3d, and the like. After over-etching, the resist layers 5a to 5d are removed. A stack of 4a / 3a or the like is used as a gate electrode or a wiring layer.
[0006]
Conventionally, as a wiring forming method using a W layer, a method as shown in FIGS. 14 to 16 has been proposed.
[0007]
In the process of FIG. 14, a W layer 8 is formed on an insulating film 7 such as silicon oxide that covers the surface of a semiconductor substrate 6 such as silicon. Then, resist layers 9a and 9b are formed on the W layer 8 so as to be close to each other.
[0008]
In the process of FIG. 15, SF is used as the F-containing gas. ₆ The W layer 8 is just etched so that the thickness becomes zero or a value in the vicinity thereof in a resist-free region wider than the distance between the resist layers 9a and 9b by plasma etching using the above. As a result, W layers 8a and 8b respectively corresponding to the resist layers 9a and 9b remain, and a thin W layer 8c remains between the W layers 8a and 8b due to the RIElag phenomenon.
[0009]
In the step of FIG. 16, following the step of FIG. 15, over-etching is performed by plasma etching similar to the step of FIG. 15 to remove the W layer 8c and leave the W layers 8a and 8b. Thereafter, the resist layers 9a and 9b are removed. The W layers 8a and 8b are used as wiring layers.
[0010]
SF in FIGS. 15 and 16 ₆ In order to perform anisotropic etching in the plasma etching process according to, it is necessary to increase the energy of ions incident on the substrate or lower the temperature of the substrate. In addition, a method of securing an anisotropic shape by suppressing side etching with a reaction product has been proposed. For example, JP-A-7-147271 discloses SF. ₆ N ₂ And NH ₃ It has been shown that side etching is suppressed by WN, which is a reaction product, by etching the W layer with plasma of a gas to which is added. JP-A-10-326774 also discloses SF. ₆ To CHF ₃ And N ₂ A method of etching the W layer with a plasma of a gas to which is added is shown. In JP-A-7-169744, a Ti or Ti compound film is laid under the W layer, and side etching is performed with low vapor pressure titanium fluoride generated by the reaction between F and Ti, which are etching active species. It has been shown to suppress.
[0011]
[Problems to be solved by the invention]
According to the method of FIGS. 11 to 13, etching damage is likely to occur in the base. That is, in the over-etching process of FIG. 13, the selection ratio of the poly-Si layer 3 to the gate oxide film 2 is high as described above. However, in the just-etching process of FIG. The selection ratio of the poly-Si layer 3 to the oxide film 2 is low, and the gate oxide film 2 may be etched. In order to prevent this, it is necessary to strictly control the process so that the just etching is stopped before the thickness of the poly-Si layer 3 becomes zero. Further, since the gate portion including the gate insulating film 2 is exposed to plasma at the time of just etching in FIG. 12 and at the time of overetching in FIG. 13, it is easily damaged by ion bombardment.
[0012]
On the other hand, according to the method of FIGS. 14 to 16, since the etching is performed with the plasma of fluorine-based gas, the selectivity of W to the silicon oxide constituting the insulating film 7 is low, and insulation is performed during overetching as shown in FIG. The film 7 is etched on the side of the W layers 8a and 8b. For this reason, there is an inconvenience that the wiring step becomes large.
[0013]
An object of the present invention is to provide a novel dry etching method capable of reducing etching damage while ensuring an anisotropic shape.
[0014]
[Means for Solving the Problems]
The dry etching method according to the present invention includes a first step of forming a stacked layer in which a tungsten-based conductive material layer is stacked on a polysilicon layer on an insulating film covering a substrate, and a sparse pattern on the tungsten-based conductive material layer. A second step of forming a plurality of resist layers so that a resist layer absent region in the pattern region and a resist layer absent region in the dense pattern region are formed; and a first mixed gas of chlorine-containing gas and oxygen gas The thickness of the tungsten-based conductive material layer becomes zero or a value in the vicinity of the non-existing region of the resist layer in the sparse pattern region by dry etching using a plurality of resist layers as a mask. And the thickness of the resist layer absent region in the dense pattern region is larger than the thickness of the resist layer absent region in the sparse pattern region. A third step of etching to a value, and following the third step, a second mixed gas of bromine-containing gas, chlorine-containing gas, and oxygen gas is used as an etching gas, and the plurality of resist layers are used as masks. The plurality of resist layers are removed by removing the tungsten-based conductive material in the absence of the resist layer in the dense pattern region while suppressing side etching of the tungsten-based conductive material layer with a tungsten-based bromine compound by dry etching. A fourth step of forming a plurality of tungsten-based conductive material layers each having a corresponding pattern, wherein the second mixed gas is The polysilicon layer is a gas that etches the tungsten-based conductive material layer without etching. By increasing the etching selectivity ratio of the tungsten-based conductive material to polysilicon, the tungsten-based conductive material in the non-existing region of the resist layer in the sparse pattern region and the non-existence of the resist layer in the dense pattern region after the completion of the fourth step. Etching rate with tungsten-based conductive material in the existing region Sparse The pattern dependency is canceled.
[0015]
According to the first dry etching method, Cl ₂ Chlorine-containing gases such as ₂ W, WSi by dry etching using gas mixture as etching gas ₂ After just etching a W-based conductive material layer such as HBr, a bromine-containing gas such as HBr is added to the mixed gas. The Then, over-etching of the W-based conductive material is performed, followed by dry etching of the poly-Si single layer. For overetching, O ₂ By setting the gas flow rate ratio high, the selection ratio of the W-based conductive material to the poly-Si can be increased, and the W-based conductive material can be selectively removed. For over-etching, bromine-containing gas of By setting the flow rate ratio to a predetermined value, the W-based conductive material can be etched while ensuring an anisotropic shape. Furthermore, since just etching and over etching are performed in a state where a poly-Si layer exists on an insulating film as a base film, the base film (insulating film) may be etched or exposed to ion bombardment. In addition, the etching damage can be reduced.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
1 to 3 show a wiring forming method according to an embodiment of the present invention.
[0019]
In the process of FIG. 1, a gate insulating film 12 made of silicon oxide is formed on the surface of a semiconductor substrate 10 such as silicon by a thermal oxidation method or the like. A poly-Si layer 14 and WSi are formed on the gate insulating film 12 by CVD (chemical vapor deposition) or the like. ₂ Layer 16 is deposited sequentially. Poly-Si layer 14 and WSi ₂ The layer 16 is for forming a gate electrode or a wiring layer, and the poly-Si layer 14 is lowered in resistance by doping with a conductivity type determining impurity.
[0020]
WSi ₂ On the layer 16, resist layers 18a to 18d are formed according to a desired gate electrode / wiring pattern by a known photolithography process. The resist layers 18a and 18b are arranged at large intervals in the sparse pattern region A, and the resist layers 18b to 18d are arranged at small intervals in the dense pattern region B.
[0021]
In the process of FIG. ₂ Gas and O ₂ Gas mixture (Cl ₂ / O ₂ WSi by plasma etching using gas ₂ The layer 16 is just etched in the sparse pattern region A so that the thickness becomes zero or a value in the vicinity thereof. Etching at this time is performed using an ECR (electron cyclotron resonance) plasma etching apparatus of FIG. 4 as an example, and the etching conditions are as follows:
Pressure: 1mTorr
Microwave power: 1000W
High frequency power: 50W
Gas flow rate: Cl ₂ / O ₂ = 50 / 10sccm
It was.
[0022]
As a result of the just etching, WSi having a pattern corresponding to each of the resist layers 18a to 18b. ₂ Layers 16a-16d remain. In the dense pattern region B, the etching rate is reduced due to the RIE lag phenomenon, so that the relatively thin WSi. ₂ Layers 16e and 16f are WSi ₂ Between layers 16b, 16c and WSi ₂ Remain between the layers 16c and 16d.
[0023]
After this, Cl ₂ / O ₂ HBr / Cl with HBr gas added to the gas ₂ / O ₂ WSi is overetched by plasma etching using gas. ₂ Layers 16e and 16f are removed. The etching at this time is performed by using the etching apparatus of FIG. 4 as an example, and the etching conditions are as follows:
Pressure: 1mTorr
Microwave power: 1000W
High frequency power: 50W
Gas flow rate: HBr / Cl ₂ / O ₂ = 8.5 / 21.5 / 20sccm
It was.
[0024]
O in over-etching ₂ The reason why the flow rate was increased was that WSi relative to poly-Si. ₂ WSi such as 16e, 16f, etc. ₂ This is to facilitate removal of the layer. O ₂ High flow rate Cl ₂ / O ₂ In the etching process, W is a WOCl with a high vapor pressure. ₄ WSi ₂ Etch the sidewalls of the layers 16a to 16d (side etching) to obtain WSi ₂ The anisotropic shape of the layers 16a to 16d is impaired. Therefore, during over-etching, Cl ₂ / O ₂ WOBr with low vapor pressure by adding HBr to gas ₄ And WBr ₅ To produce WSi ₂ Etching is performed while forming a protective film on the side walls of the layers 16a to 16d (suppressing side etching). As a result, WSi ₂ The anisotropic shapes of the layers 16a to 16d are ensured. Further, just etching and over-etching are performed in a state where the poly-Si layer 14 exists on the gate insulating film 12, so that the gate insulating film 12 is not etched or exposed to ion bombardment, and etching damage is caused. Is reduced.
[0025]
In the process of FIG. 3, HBr / Cl ₂ / O ₂ Resist layers 18a-18d and WSi by plasma etching using gas ₂ The poly-Si layer 14 is selectively etched using the layers 16a to 16d as a mask. This etching is performed using the etching apparatus of FIG. 4 as an example, and the etching conditions are as follows:
Pressure: 2mTorr
Microwave power: 1000W
High frequency power: 35W
Gas flow rate: HBr / Cl ₂ / O ₂ = 100/5 / 5sccm
It was. Other examples of etching conditions include Cl ₂ It is also possible to use a gas containing no chlorine-containing gas such as microwave power: 800 to 1500 W, gas flow rate: HBr / O ₂ = 100/5 sccm.
[0026]
As a result of the selective etching of the poly-Si layer 14, poly-Si layers 14a to 14d having patterns respectively corresponding to the resist layers 18a to 18d remain. During poly-Si etching, SiO _x , SiBr _x Reaction products such as WSi ₂ Since side etching of the layers 16a to 16d and the poly-Si layers 14a to 14d is suppressed, it is possible to give a favorable anisotropic shape to the stack of 16a / 14a, 16b / 14b, 16c / 14c, 16d / 14d, etc. . Poly-Si is WSi ₂ Compared to RIElag, it is easy to etch. After the poly-Si etching, the resist layers 18a to 18d are removed by a known ashing process. WSi such as 16a / 14a ₂ / Poly-Si stack is used as a gate electrode or wiring layer.
[0027]
The inventor ₂ / O ₂ Plasma etching using gas is WSi ₂ / WSi against poly-Si in poly-Si stack (W polycide layer) etching ₂ Focusing on the fact that the selection ratio can be set high, various experiments were conducted using the etching apparatus of FIG.
[0028]
In the apparatus of FIG. 4, the processing chamber 20 includes a plasma chamber 22a and a reaction chamber 22b. A sample stage (electrode) 24 is provided at the bottom of the reaction chamber 22 b, and a processing target wafer 26 is placed on the upper surface of the sample stage 24.
[0029]
A high frequency power source 28 is connected to the sample stage 24, and for example, high frequency power of 13.56 MHz is supplied. The reaction chamber 22b is connected to a gas supply source (not shown) and to the exhaust device VAC.
[0030]
A microwave MW of 2.45 GHz, for example, is supplied to the upper portion of the plasma chamber 22a from a microwave power source (not shown) through the microwave introduction window 30. The window 30 is usually made of quartz. A solenoid coil 32 is provided so as to surround the upper portion of the processing chamber 20.
[0031]
4 using the etching apparatus of FIG. ₂ / O ₂ WSi in gas plasma ₂ And poly-Si etching, WSi ₂ / Poly Si selectivity ratio O ₂ The result of examining the flow rate ratio dependency is shown in FIG. In the experiment, WSi was formed on a silicon substrate through a silicon oxide film. ₂ A first sample group including nine samples in which layers were deposited and a second sample group including nine samples in which a poly-Si layer was deposited on a silicon substrate via a silicon oxide film were used. The diameter of each silicon substrate was 200 mm. Each sample was inserted into the etching apparatus shown in FIG. 4 as a wafer to be processed 26 and etched. Etching conditions are
Pressure: 1mTorr
Microwave power: 1400W
High frequency power: 50W
Gas flow rate: Cl ₂ + O ₂ = 50sccm
It was.
[0032]
For 9 samples in the first sample group, O ₂ The flow rate ratio is changed to 0, 10, 20, 22, 24, 26, 28, 30, 40%, and WSi for each sample. ₂ The etching rate was determined. The result is indicated by a line P in FIG. Also, for the nine samples in the second sample group, O ₂ The flow rate ratio was changed as in the case of the first sample group, and the etching rate of poly-Si was obtained for each sample. The result is shown by line Q in FIG.
[0033]
WSi ₂ / Poly-Si selection ratio is O between the first sample group and the second sample group. ₂ WSi for each sample with the same flow rate ₂ It calculated by calculating | requiring the ratio of the etching rate of / poly Si etching rate. The result is indicated by a line R in FIG.
[0034]
According to the experimental results of FIG. ₂ If the flow rate ratio is 30% or more, it is almost WSi ₂ It can be seen that only the process conditions are etched. In the over-etching of FIG. ₂ Since the flow rate ratio is 40%, WSi such as 16e and 16f remaining in a narrow space ₂ The layer can be removed efficiently. As a result, WSi ₂ It is possible to cancel the pattern dependence of the etching rate based on the RIElag phenomenon.
[0035]
FIG. 6 shows HBr / Cl ₂ / O ₂ WSi in plasma etching using gas ₂ The result of having investigated the dependence of the side etching amount on the HBr flow rate ratio is shown. In the experiment, WSi was formed on a silicon substrate having a diameter of 200 mm via a silicon oxide film. ₂ / Four samples on which a poly-Si stack (W polycide layer) was formed were used. Each sample was provided with a large number of resist layers in parallel according to the pattern of line / space = 1.0 / 0.6 μm as shown in the dense pattern region B of FIG. Each sample provided with the resist layer in this manner was inserted into the etching apparatus of FIG. Etching conditions are
Pressure: 1mTorr
Microwave power: 1400W
High frequency power: 50W
Gas flow rate: Cl ₂ + HBr = 30 sccm, O ₂ = 20sccm
It was. Where O ₂ The flow rate ratio is WSi in FIG. ₂ / Poly-Si selection ratio is 40%, which is infinite.
[0036]
For 4 samples, Cl ₂ + HBr is changed to 0, 10, 20, 30%, and WSi for each sample. ₂ The side etching amount S (μm) of was determined. The side etching amount S is shown in FIG. ₂ As illustrated for the layer 16a, S = width Wtop measured at the top surface−width Wbot measured at the bottom surface. S <0 represents a forward taper shape, and S> 0 represents a side etch shape (reverse taper shape).
[0037]
According to the experimental results of FIG. 6, it can be seen that the side etching becomes zero at a HBr flow rate ratio of 17% and a vertical anisotropic etching shape is obtained. However, when the HBr flow rate ratio is 17%, a vertical shape is obtained in the line / space pattern, but a large amount of reaction products adhere to the side wall in the isolated line, resulting in a forward tapered shape.
[0038]
In the process of FIG. ₂ / O ₂ Since just etching is performed by plasma etching using gas, HBr / Cl ₂ / O ₂ It is possible to prevent the occurrence of a forward taper shape in an isolated line as occurred in the process. High O ₂ Flow rate of HBr / Cl ₂ / O ₂ WSi using gas plasma etching process ₂ Over-etching of WSi against poly-Si ₂ WSi remaining in a narrow space while maintaining a high selection ratio ₂ Only WSi can be removed by etching, and the effect of adding HBr can cause WSi ₂ Side etching can be prevented.
[0039]
8 to 10 show a wiring forming method according to another embodiment of the present invention.
[0040]
In the process of FIG. 8, a W layer 44 is formed by sputtering or the like on an insulating film 42 such as silicon oxide that covers the surface of a semiconductor substrate 40 such as silicon. Then, resist layers 46a and 46b are formed on the W layer 44 so as to approach each other according to a desired wiring pattern.
[0041]
In the process of FIG. 9, Cl ₂ / O ₂ The W layer 44 is just etched by plasma etching using gas so that the thickness becomes zero or a value in the vicinity thereof in a resist absence region wider than the distance between the resist layers 46a and 46b. The etching at this time can be performed under the same conditions as the just etching described in FIG. As a result of the just etching, W layers 44a and 44b respectively corresponding to the resist layers 46a and 46b are obtained, and a thin W layer 44c remains due to the RIElag phenomenon between the W layers 44a and 44b.
[0042]
In the process of FIG. ₂ / O ₂ HBr / Cl with HBr added to the gas ₂ / O ₂ Over-etching is performed by plasma etching using gas to remove the W layer 44c and leave the W layers 44a and 44b. The etching at this time can be performed under the same conditions as the over-etching described in FIG. After over-etching, the resist layers 46a and 46b are removed by ashing or the like. The W layers 44a and 44b are used as wiring layers.
[0043]
In the etching process of FIGS. ₂ / O ₂ Since the gas is used as the etching gas, the selectivity of W to the silicon oxide constituting the insulating film 42 is improved. Accordingly, it is possible to prevent the insulation film 42 from being reduced and the wiring level difference being increased. In addition, in the overetching of FIG. 10, the side etching of the W layers 44a and 44b is suppressed by adding HBr, so that the shape deterioration of the W layer (reverse taper shape or the like) can be prevented.
[0044]
The wiring formation method described above with reference to FIGS. ₂ You may implement using a layer and the same effect as mentioned above is acquired.
[0045]
The present invention is not limited to the above-described embodiment, and can be implemented in various modifications. For example, the following changes are possible.
[0046]
(1) As the W-based conductive material layer, W, WSi ₂ Not limited to this, a W alloy may be used. As tungsten silicide, WSi ₂ In addition to the stoichiometric ones, non-stoichiometric ones may be used, and in general, WSi _x Can be used.
[0047]
(2) The bromine-containing gas is not limited to HBr, but Br ₂ , BBr ₃ , CBr ₄ , SiBr ₄ Etc. may be used. Br ₂ The added amount of gas such as may be set so that the amount of Br atoms present in the plasma is equivalent to that of HBr shown in the above embodiment. Also, instead of bromine-containing gas, HI, I ₂ , BI ₃ , CI ₄ , SiI ₄ An iodine-containing gas such as may be used. Gas such as HBr or HI or O ₂ Regarding the gas, the optimum value of the addition amount depends on the film quality of the film to be etched (for example, depends on the film forming method, the processing conditions after the film forming, the film forming apparatus, etc.), and is adjusted for each film to be etched. Is desirable.
[0048]
(3) When the W-based conductive material layer is dry-etched, an antireflection film such as TiN or TiON may be provided on the W-based conductive material layer in advance. Further, a WN layer or the like may be interposed between the W-based conductive material layer and the poly-Si layer.
[0049]
【The invention's effect】
As described above, according to the present invention, after the W-based conductive material layer is just etched by dry etching using a mixed gas of chlorine-based gas and oxygen gas as an etching gas, a bromine-containing gas is added to the mixed gas. The Since the W-based conductive material is over-etched and then the poly-Si single layer is dry-etched, etching damage can be reduced while ensuring an anisotropic shape, and the yield is improved. An effect is obtained.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a substrate showing a resist layer forming step in a wiring forming method according to an embodiment of the present invention.
FIG. 2 shows WSi following the process of FIG. ₂ It is board | substrate sectional drawing which shows the just etching process and over-etching process of a layer.
3 is a cross-sectional view of a substrate showing a poly-Si layer etching step and a resist layer removing step following the step of FIG. 2. FIG.
FIG. 4 is a cross-sectional view showing a plasma etching apparatus used in the practice of the present invention.
FIG. 5 Cl ₂ / O ₂ Selectivity in plasma etching using gas (WSi ₂ / Poly Si) O ₂ It is a graph which shows flow rate ratio dependence.
FIG. 6 HBr / Cl ₂ / O ₂ WSi in plasma etching using gas ₂ It is a graph which shows the HBr flow rate ratio dependence of the side etching amount.
FIG. 7 WSi ₂ / WSi in poly-Si stacked etching ₂ It is sectional drawing which shows the side etching condition of a layer.
FIG. 8 is a cross-sectional view of a substrate showing a resist layer forming step in a wiring forming method according to another embodiment of the present invention.
FIG. 9 is a cross-sectional view of the substrate showing a W layer just etching step following the step of FIG. 8;
10 is a substrate cross-sectional view showing an overetching process following the process of FIG. 9. FIG.
FIG. 11 is a substrate cross-sectional view showing a resist layer forming step in an example of a conventional wiring forming method.
FIG. 12 shows WSi following the process of FIG. ₂ FIG. 4 is a cross-sectional view of a substrate showing a just etching process of a / poly-Si stack.
13 is a substrate cross-sectional view showing an overetching step and a resist layer removing step following the step of FIG. 12. FIG.
FIG. 14 is a cross-sectional view of a substrate showing a resist layer forming step in another example of a conventional wiring forming method.
15 is a cross-sectional view of a substrate showing a W layer just etching step subsequent to the step of FIG. 14;
16 is a substrate cross-sectional view showing an overetching process following the process of FIG. 15;
[Explanation of symbols]
10, 40: Semiconductor substrate, 12, 42: Insulating film, 14, Poly-Si layer, 16: WSi ₂ Layer, 18a-18d, 46a, 46b: resist layer, 44: W layer.

Claims (2)

A first step of forming a laminate in which a tungsten-based conductive material layer is stacked on a polysilicon layer on an insulating film covering the substrate;
A second step of forming a plurality of resist layers on the tungsten-based conductive material layer so that a non-existing region of the resist layer in the sparse pattern region and a non-existing region of the resist layer in the dense pattern region are formed;
A region where the resist layer is absent in the sparse pattern region by dry etching using the first mixed gas of chlorine-containing gas and oxygen gas as an etching gas and using the plurality of resist layers as a mask. A third step of etching so that the value becomes zero or a value in the vicinity thereof in the absence of the resist layer in the dense pattern region and is larger than the thickness of the absence region of the resist layer in the sparse pattern region When,
Subsequent to the third step, the tungsten-based bromine-based compound is formed by dry etching using a second mixed gas of bromine-containing gas, chlorine-containing gas, and oxygen gas as an etching gas and the plurality of resist layers as a mask. A plurality of tungsten-based conductive material layers each having a pattern corresponding to each of the plurality of resist layers by removing the tungsten-based conductive material in the non-existing region of the resist layer in the dense pattern region while suppressing side etching of the conductive material layer And a fourth step of forming
The second mixed gas is a gas for etching the tungsten-based conductive material layer without etching the polysilicon layer. By increasing the etching selectivity of the tungsten-based conductive material to the polysilicon, the second mixed gas is used after the completion of the fourth step. Canceling the dependence of the etching rate of the tungsten-based conductive material in the non-existing region of the resist layer in the sparse pattern region on the sparse pattern on the etching rate of the tungsten-based conductive material in the non-existing region of the resist layer in the dense pattern region A dry etching method characterized by the above. 2. The dry etching method according to claim 1, wherein a ratio of a chlorine-containing gas flow rate of the first mixed gas is larger than a ratio of a chlorine-containing gas flow rate of the second mixed gas.

Images