JP4641708B2 - Data processing apparatus and processor unit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a data processing device such as an LSI and a processor incorporated therein.
[0002]
[Prior art]
A large-scale system LSI is possible, and it is becoming possible to construct the entire system on a single semiconductor chip. Along with this, a processor (processor unit) that is indispensable for configuring a system and a function that has been developed as a dedicated LSI in order to maximize the performance according to the purpose are integrated on a single semiconductor chip. Development of a system LSI integrated into a single system is underway. The processor developed for this large-scale system LSI is called an embedded processor (embedded processor).
[0003]
[Problems to be solved by the invention]
An embedded processor is fundamentally different from a conventional single-chip CPU, but currently provided embedded processors are single-chip CPU processors. On the other hand, it is hard to say that it is clearly recognized as an embedded application.
[0004]
The major difference between the embedded processors is that the optional functions need to be rich. That is, in the case of a conventional CPU (or a finished product CPU) configured with a single chip, a function that will be required is fully mounted in advance in order to meet the needs of a wide range of users. On the other hand, the embedded processor incorporated in the system LSI requires only the necessary functions each time. Therefore, the function conventionally provided as one processor is also converted into an optional module. A processor unit and a modularized function are mounted on one system LSI, and a processor having a desired function is a system LSI. Will be built inside.
[0005]
Against this background, a debug module (debug function), which is generally built in the case of a conventional CPU, is also a separate unit that can be incorporated into a system LSI as an option in an embedded processor unit. It is desirable to be provided as The debug unit sets instruction pointer data or instruction code data as a target for causing the processor to break (pause) from a personal computer or the like, and the instruction pointer data or instruction code that is a break condition while the processor is executing a program. This is hardware that temporarily stops the processing of the processor unit when data is found. Then, debugging is performed by observing the contents of the internal register of the processor or injecting a specific value into the internal register.
[0006]
When the debug unit is provided as an optional module, it is desirable that the debug unit is also controlled separately from the embedded processor. This also improves debugging reliability. For example, debugger software for operating the debug unit can be run on a personal computer. In the case of a conventional finished product CPU, software is created on the premise that there is a debugger, whereas in an embedded processor, whether or not a debugger is provided is a user specification, and it is assumed that there is a debugger. Software development can be wasteful and redundant. In addition, running software on the premise that there is a debugger in a system without a debugger may cause a system error, and reliability may be reduced.
[0007]
On the other hand, when trying to operate the debugger unit independently of the processor unit, in order to break the processor unit according to the contents of the instruction bus (instruction pointer and instruction code) which is a break condition, the instruction pointer and instruction code are set. It is necessary to provide the fetch and decode functions to be generated in the debugger unit as well as the processor unit. For this reason, if the system LSI is to have a debugging function, it is necessary to mount a debugging unit having a complicated configuration and a relatively large circuit scale. When viewed as the entire system LSI, the hardware for fetching and decoding is doubled. In particular, when a processor unit corresponding to an instruction set having an indefinite length (or variable length) such as one or two instructions is mounted, the following functions are required for fetching and decoding. The scale of hardware that is heavily owned will also increase.
[0008]
That is, if the bus width of the data bus from which the instruction code is output does not match the instruction length, it is not clear where the next instruction code data is in the data, and the next instruction code straddles the fetched data. Data may exist. Therefore, in order to determine whether the instruction pointer data to be broken matches the instruction pointer used to fetch the data including the instruction code, the position of the next instruction pointer is determined by monitoring the length of each instruction. The function to do is needed. Also, if the data bus width does not match the instruction length, the branch destination address does not always match the fetch address when a branch occurs, so adjust it to determine the position of the next instruction pointer. The function to do is needed. Further, if the data bus width does not match the instruction length, as described above, the next instruction code data is selected from the fetched data and arranged, or the next instruction code data straddling the preceding and succeeding data is changed. A function to align is required.
[0009]
In addition to such functions, the following functions are also required in order for the debug unit to appropriately determine the next instruction code to be executed next in the execution unit of the processor. If the instruction code includes a multi-cycle instruction code that requires a plurality of execution cycles for execution, the timing at which the next instruction code is executed in the execution unit becomes unclear. Therefore, a function for detecting the timing from the instruction fetch until the instruction is executed is required. If the multi-cycle instruction processing can be supported, the hardware becomes very large.
[0010]
Further, when a branch occurs, an instruction code that has not been executed by the execution unit even if the instruction code has been fetched before that is an instruction code that is not actually executed and does not become the next instruction code. Since it is meaningless to output a break signal for debugging an instruction code that is not executed, a function for determining whether or not a branch occurs is also required.
[0011]
Since the hardware that covers these functions becomes large-scale, it is hardware that should be omitted considering the miniaturization and cost reduction of the system LSI. Moreover, these functions are basically functions supported by the processor unit hardware as the fetch function of the processor unit, and the hardware is duplicated.
[0012]
On the other hand, developing both an embedded processor with a debugging function and an embedded processor without a debugging function is a big investment in the overlap. In addition, when changing or improving the function of a processor, it is a heavy load to upgrade both those with a debugging function and those without a debugging function at the same time, which is a large duplication investment. In addition, an investment is required to double develop and maintain software for a processor with a debugging function and software for a processor without a debugging function. Therefore, in comparison with these disadvantages, it is possible to determine that the overlapping hardware to the extent that the debug unit and the processor unit are provided with somewhat overlapping hardware should be acceptable.
[0013]
However, an object of the present invention is to provide a system in which hardware that overlaps with a processor unit can be omitted from a debug unit in a system LSI that can be equipped with a debug unit as an option. Accordingly, it is an object of the present invention to prevent double investment in design / development or maintenance of hardware and software and to provide a compact and low-cost system LSI.
[0014]
[Means for Solving the Problems]
The present invention provides a processor unit having an interface for outputting next instruction pointer data and next instruction code data to the outside of the processor unit as an embedded processor unit. With this processor unit, when incorporated into the system LSI together with the debug unit, the debug unit can determine the break condition from the next instruction pointer data and / or the next instruction code data provided from the processor unit. Duplicate hardware can be eliminated. On the other hand, the processor unit only outputs the next instruction pointer data and the next instruction code data regardless of the presence or absence of the debug unit, so that both hardware and software can be developed and designed regardless of the presence or absence of the debug unit. Maintenance can be performed.
[0015]
  That is, in the present invention, a processor having a fetch unit that outputs a fetch address based on instruction pointer data, can generate instruction code data from the obtained data, and an execution unit that can execute processing based on the instruction code data The fetch unit provides a processor including a data alignment unit that decodes obtained data to generate variable-length instruction code data. The processor further includes instruction code data decoded by the fetch unit,Of the current instruction code data in the execution unitNext, first output means for outputting next instruction pointer data of next instruction code data to be executed by the execution unit to the outside from the processor unit, and second output for outputting the next instruction code data to the outside from the processor unit Means. If it is this processor unit, it is a debug unit having a break signal output means for supplying a break signal for requesting a pause to the processor unit when a break condition is satisfied, and is a target instruction pointer set as a break condition First input means for receiving next instruction pointer data to be compared with data from outside the debug unit, and next instruction code data to be compared with target instruction code data set as a break condition from outside the debug unit The debug unit can be operated in combination with the debug unit having the second input means.
[0016]
  How to control the debug unitA break request step for supplying a break signal for requesting a pause to the processor unit when a break condition is satisfied, and a next instruction pointer to be compared with target instruction pointer data set as a break condition Receiving from the outside of the debug unit at least one of data and next instruction code data to be compared with target instruction code data set as a break condition. Therefore, the debug unit does not require hardware corresponding to the fetch unit of the processor unit.
[0017]
Therefore, the data processing apparatus having the processor unit and the debug unit according to the present invention can be equipped with a debug function without duplicating hardware corresponding to the fetch unit. Since the debug unit is an optional unit, a data processing device, that is, a system LSI can be formed by using the processor unit of the present invention as an embedded processor without mounting the debug unit.
[0018]
When the program includes a multi-cycle instruction code, it is necessary to determine the execution time of the next instruction code data. Further, in order to prevent the generation of a useless break signal accompanying the occurrence of a branch, it is desirable to determine whether or not a break signal is necessary immediately before execution of the next instruction code data. Therefore, it is further preferable to provide a processor unit having third output means for outputting the timing for starting processing based on the next instruction code data from the processor unit to the outside. The timing for starting the processing based on the next instruction code data is the timing at which the processing based on the current instruction code data in the execution unit is completed, and this timing may be output from the processor unit to the outside. Correspondingly, the debug unit also includes third input means for accepting the timing at which the next instruction code data starts to be executed from the outside of the debug unit. The break signal output means includes at least target instruction pointer data and Any one of the target instruction code data and the next instruction pointer data and the next instruction code data coincide with each other, and a break signal may be output when the next instruction code data is started to be executed. In the control method of the debug unit, a step of accepting the timing at which the next instruction code data starts to be executed is provided from the outside of the debug unit. In the break request process, at least one of the target instruction pointer data and the target instruction code data is set. When the next instruction code data coincides with the next instruction code data and the next instruction code data starts to be executed, a break signal is output.
[0019]
The applicant of the present application has a dedicated processing unit having a dedicated circuit suitable for dedicated processing, and the fetch unit of the processor unit supplies general-purpose instruction code data defining processing in the processor unit as instruction code data to the execution unit. However, a data processing apparatus that supplies dedicated instruction code data defining processing in the dedicated processing unit to the dedicated processing unit, that is, a system LSI has been proposed. The processor unit of the present invention is used as an embedded processor of the system LSI. This makes it possible to add a debug unit at a low cost.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described in more detail with reference to the drawings. FIG. 1 schematically shows a data processing apparatus having a processor unit according to the present invention, that is, a system board 1 on which a system LSI 2 is mounted. The system LSI 2 mounted on the system board 1 is an LSI (hereinafter referred to as VUPU) proposed by the applicant of the present application called VUPU, and is referred to as a processor unit or general-purpose data processing unit (hereinafter PU) 5. A dedicated data processing unit (hereinafter referred to as VU) 6 specialized for specific processing is mounted. Further, the VUPU 2 of this example includes a debug unit (hereinafter referred to as DU) 7 for debugging the PU 5 and a user interface 9 for inputting / outputting signals to / from the DU 7. As the user interface 9, a JTAG boundary scan test interface or the like can be adopted, and the DU 7 can be controlled by the debugger software 10 operating on the personal computer 4 via the debug interface 3 provided on the system board 1.
[0021]
FIG. 2 is a block diagram showing an outline of VUPU2. VUPU2 is an LSI that uses PU5 as an embedded processor and controls VU6 by a program via PU5. The PU 5 is a general-purpose processor unit, and includes a code RAM 11 containing an execution format program code (microprogram code) 11a, an instruction fetched from the code RAM 11, and an execution unit (EU) 13 of the PU 5 and the VU 6 And a fetch unit (FU) 12 for providing a decoded control signal. Further, the PU 5 includes a highly versatile execution unit 13 composed of a general-purpose register, a flag register, an arithmetic unit (ALU), and the like, and performs general-purpose processing while inputting / outputting data using the data RAM 14 as a temporary recording area. Execute.
[0022]
The fetch unit 12 calculates and outputs a fetch address from a previous instruction or an instruction pointer determined by the state of the state register 15 and an interrupt signal, and fetches data including an instruction code from a predetermined address in the code RAM 11. Further, the fetched data is decoded to generate a dedicated instruction (VU instruction) or general-purpose instruction (general instruction, PU instruction) from the data obtained from the code RAM 11, and the dedicated instruction is controlled by a control signal (decoded control signal: The decoded general-purpose instruction is supplied to the execution unit 13 as a control signal (Decoded Control Signal) φp. The execution unit 13 returns a status signal (Exec unit Status Signal) φs indicating the execution state, and the execution results of the execution unit 13 and the VU 6 are reflected in the state register (state register) 15. For example, when the execution unit 13 satisfies the branch condition, the fetch unit 12 fetches the branch destination instruction code accordingly.
[0023]
In this VUPU2, with respect to the fetch unit 12, the execution unit 13 of PU2 and the VU6 are processing units of the same hierarchy. Therefore, it can be considered that the fetch unit 12 is an instruction issue unit common to the execution unit 13 and the VU 6, and the execution unit 13 is a PU that is compared with the VU 6.
[0024]
The VU 6 that executes the VU instruction φv includes a unit 21 that selects and decodes the VU instruction φv addressed to its own unit, and a sequencer (FSM (Finite) that outputs a control signal in advance so as to perform specific data processing. And a data path unit 23 designed to perform specific data processing in accordance with a control signal from the sequencer 22. The VU 6 includes a register 24 that can be accessed from the PU 5, and the data necessary for processing of the data path unit 23 is controlled by the PU 5 via the interface register 24, and the internal state of the VU 6 is controlled via the register 24. It can be referred to by PU5. Further, the result processed in the data path unit 23 is supplied to the PU 5, and the PU 5 performs processing using the result.
[0025]
The code RAM 11 stores a program 11a including a general-purpose instruction (PU instruction) and a dedicated instruction (VU instruction). The fetch unit 12 causes the VU 6 to receive a control signal φv including a VU instruction for starting itself. Then, the VU instruction decoder 21 selects it and operates. On the other hand, only the control signal φp obtained by decoding the PU instruction is supplied to the execution unit 13. The control signal φv obtained by decoding the VU instruction is not issued to the execution unit 13, but instead, a control signal indicating a nop instruction not accompanied by execution is issued, and the execution unit 13 skips the processing. Therefore, a VU instruction that cannot be interpreted by the execution unit 13 is not provided to the execution unit 13, and a program 11a including new or various VU instructions can be executed by the VUPU 2 without changing the configuration of the PU 5. In some descriptions of the present specification, the PU instruction and the control signal φp obtained by decoding the PU instruction are used in the same meaning, and the VU instruction and the control signal φv obtained by decoding the PU instruction are used in the same meaning. .
[0026]
Therefore, in VUPU2, VU6 is changed by an application or the like, and a dedicated instruction (VU instruction) for giving an instruction to VU6 often changes depending on the application. On the other hand, the PU 5 need only have a function that can interpret and execute a PU instruction that is a basic instruction or a general-purpose instruction without having to deal with an instruction specialized for VU by outputting a nop instruction. Therefore, the PU 5 is a general-purpose embedded processor and provides a function as a versatile platform on which the VU 6 operates. Then, by combining the versatile PU 5 and the VU 6 provided with a dedicated circuit, the VU 6 can also be controlled by a program via the PU 5. Therefore, the VUPU architecture can provide a system LSI that can shorten the design and development period without sacrificing real-time responsiveness, and can flexibly cope with subsequent changes and modifications.
[0027]
Therefore, it is important for the VUPU 2 that many optional functions can be mounted while maintaining the versatility of the PU 5, and the debug unit (DU) 7 is mounted as an optional unit in the VUPU 2 of this example. FIG. 3 shows signals exchanged between PU5 and DU7. The PU 5 in this example includes a wiring or connection point (second output means) 32 for externally outputting the next instruction code data φc fetched and decoded by the fetch unit 12 and then supplied to the execution unit 13, and the next instruction. A wiring or connection point (first output means) 31 for externally outputting next instruction pointer data φa indicating code data φc is provided. Further, the PU 5 includes a wiring or connection point (third output means) 33 for externally outputting a signal φt indicating the timing at which the execution unit 13 starts executing the processing based on the next instruction code data φc. The signal φt indicating the timing for starting execution of the next instruction is a signal indicating the timing at which the next instruction is latched upon completion of the instruction in the execution unit 13.
[0028]
Further, the PU 5 is provided with a wiring or connection point 34 for receiving the break signal φb from the DU 7. When receiving the break signal φb from the DU 7, the PU 5 stops processing based on the instruction code data in the execution unit 13.
[0029]
Corresponding to the debugging interface 8 provided with the connection points 31, 32, 33 and 34, the DU 7 has a connection point (first input means) 61 for receiving the next instruction point data φa, and the next instruction code data φc. Is provided with a connection point (second input means) 62 for receiving the signal, a connection point (third input means) 63 for receiving the execution start timing signal φt, and a connection point 64 for outputting the break signal φb. 60 is provided. The break condition coincidence detection function 50 of the DU 7 matches the next instruction point data φa received by the target instruction pointer data φta set via the user interface 9, and the next instruction received by the set target instruction code data φtc. When it coincides with the instruction code data φc and when the next instruction code data φc starts to be executed from the timing signal φt, the break signal φb is output.
[0030]
FIG. 4 shows a more detailed configuration of PU5 and DU7 related to these signals. The fetch unit 12 of the PU 5 includes a next instruction pointer generation unit 35 that generates a fetch address for obtaining a next instruction code based on the fetched and decoded instruction and the status signal φs from the execution unit 13. The next instruction pointer generator 35 updates the instruction pointer data and calculates the fetch address from the instruction pointer data. When the fetched and decoded instruction is a branch instruction, the branch condition is satisfied from the result of the execution unit 13. In this case, the instruction pointer data is transferred to the branch destination pointer. The fetch address generated by the generator 35 is stored in the register 36 and supplied to the code RAM 11 via the address bus 71. Data corresponding to the fetch address is obtained as fetch data φd via the data bus 72. Since the data bus 72 has a bus width of 2 words, the obtained data is always 2 words long. Therefore, if the instruction code is not only two-word length but indefinite or variable length such as one word length or three-word length, the instruction code data φc at an appropriate position is cut out from the fetch data φd, or a plurality of fetches It is necessary to generate instruction code data φc straddling data φd. Therefore, the data alignment unit 37 performs an operation of decoding the fetch data φd to generate instruction code data φc. When the timing for generating the instruction code data φc is reached, the read timing signal φr is output, and the next instruction code data to be supplied to the execution unit 13 is latched in the register 39. At the same time, the next instruction pointer data φa output from the generator 35 for fetching the next instruction code data φc is latched in the register 38.
[0031]
These next instruction pointer data φa and next instruction code data φc are supplied to the execution unit 13. In the execution unit 13, when the processing associated with the current instruction being executed internally ends and the next instruction execution start timing signal φt is output, the next instruction pointer data φa is latched in the register 41 of the current instruction pointer, and the next instruction Code data φc is latched in register 42 of the current instruction code. As a result, processing based on the next instruction code φc is started in the execution unit 13. The execution unit 13 has a function 44 for interpreting the break signal φb as a debugging function, and outputs a timing signal φdt for debugging when the break signal φb is received. The selector 43 selects the normal timing signal φt and the debugging timing signal φdt, and when debugging is started, the next instruction pointer φa and the next instruction code φc are latched by the debugging timing signal φdt, and the debugging is performed. The execution unit 13 can be controlled at the timing.
[0032]
In the PU 5 of this example, connection points 31 and 32 for outputting the next instruction pointer data φa and the next instruction code data φc latched in the registers 38 and 39 to the outside are provided in advance. Further, a connection point 33 for outputting a normal next instruction execution timing signal φt to the outside is provided in advance. These external outputs 31, 32 and 33 merely output data φa, φc and φt. Even if these data are not used externally, the control of the PU 5 itself is possible. It has a configuration that does not affect. However, in the VUPU 2 shown in FIG. 4, since the break signal φb is fed back from the DU 7 based on these data φa, φc and φt, it is possible to shift to the debug mode. In other words, in this example, the PU 5 and the DU 7 cooperate in function so that the hardware for fetching and decoding can be duplicated, and the debugging can be performed without the trouble of monitoring the timing and the hardware. Yes.
[0033]
The DU 7 includes a condition setting unit 51 that can set a break condition from the personal computer 4 through the user interface 9 and a break detection unit 55 that compares the condition and data obtained from the PU 5 and outputs a break signal φb. I have. The condition setting unit 51 includes a register 52 in which a break address condition φta serving as a break target is set, and a register 53 in which a break data condition φtc is set. The break detection unit 55 is obtained via the comparator 56 that compares the break address condition φta with the next instruction pointer data φa of the PU 5 obtained via the connection point 61, the break data condition φtc, and the connection point 62. The comparator 57 that compares the next instruction code data φc of the PU 5 and the AND gate 58 that calculates the logical sum of these output results and the timing data φt obtained through the connection point 63 and outputs the break signal φb. And. The break signal φb is supplied to the PU 5 via the register 59.
[0034]
As described above, the DU 7 of this example includes the register group 51 that stores data serving as a break condition, and the detection unit 55 that compares the data and data obtained from the processor side and outputs the break signal φb. The break signal φb can be supplied to the PU 5 at a desired timing with an extremely simple configuration. On the other hand, it is not necessary for PU5 to perform control with particular attention to DU7, and when a desired break condition is satisfied, break signal φb is supplied from DU7 and the process shifts to debug mode.
[0035]
FIG. 5 shows the processing on the PU side and the processing on the DU side related to debugging using a flowchart. First, the PU 5 calculates a fetch address for fetching data in order to acquire the next instruction code (next instruction code data) at the fetch stage executed by the fetch unit 12 in step 81, and the code RAM 11. The data is read out for. At this time, in the variable-length instruction of 1 word or 2 words length, reading is performed at the head address of the data of 2 word length width corresponding to the data bus of 2 word length width. As a result, in step 82, data including the desired next instruction code data is read from the code RAM 11. Further, in step 83, the desired next instruction code data φc is decoded from the fetched data φd at the decode stage executed by the fetch unit 12, and the next instruction code data φc and the next instruction pointer data φa are stored in the register 39. And 38. In the PU 5 of this example, the next instruction code data φc and the next instruction pointer data φa generated in this step 83 are automatically supplied to the DU 7.
[0036]
Next, at the execution stage of the execution unit 13, when the process based on the current instruction is completed at step 84, the next instruction code data φc and the next instruction pointer data φa prepared by the fetch unit 12 are taken into the execution unit 13. At this time, the PU 5 of this example automatically supplies the timing signal φt, which is a signal for capturing these data φa and φc, to the DU 7. When the processing based on the next instruction code data φc is executed in step 85, when the break signal φb is supplied from the DU 7, the processing is temporarily interrupted and the debugging mode is entered. Therefore, as long as the break signal φb is not supplied, the PU 5 obtains the next instruction code data φc in order as usual regardless of the presence or absence of the DU 7, and performs processing according thereto.
[0037]
In step 91, the DU 7 reads in advance the break address φta and the break data φtc, which are break conditions, from the external host 4 as external designation conditions. When the program to be debugged is executed in the PU 5 and the next instruction pointer data φa and the next instruction code data φc are supplied, the next instruction pointer data φa and the next instruction code data φc are obtained in step 92 and a break occurs. Address φta and break data φtc are respectively compared. If they match in step 93, the break request signal φb is output to the PU 5 when the timing signal φt is supplied in step 94. As a result, the PU 5 receives the break request signal φb in step 85 and pauses.
[0038]
In the timing chart shown in FIG. 6, when the address A3 is set as the break data φta and the instruction C3 is set as the break data φtc, the next instruction pointer data φa becomes the address A3 at the time t1, and the next instruction code data When φc becomes the code C3, a match is established at DU7. When the next instruction execution timing signal φt is input at time t2, a break signal φb is generated. At time t3, which is the timing of the next clock at which the next instruction code data φc is executed by the execution unit 13, the break signal φb is generated. Is supplied to PU5. As a result, PU5 pauses at the stage of executing instruction C3.
[0039]
Thus, in the PU 5 of this example, the interface 8 having the output terminal 31 of the next instruction pointer data φa, the output terminal 32 of the next instruction code data φc, and the output terminal 33 of the next instruction execution start timing signal φt is prepared. Therefore, the DU 7 can generate the break signal φb by using these signals φa, φc and φt supplied from the PU 5 and supply them to the PU 5. Therefore, the DU 7 does not need hardware for generating the next instruction pointer data φa, the next instruction code data φc, and the next instruction execution start timing signal φt, and redundant hardware is mounted in one LSI 2. Can be prevented.
[0040]
As described above, the hardware that outputs the next instruction pointer data φa and the next instruction code data φc becomes large when the instruction code has a variable length or the instruction code length does not match the data bus width. However, in the LSI 2 combining the PU 5 and DU 7 of this example, the instruction code data decoded on the processor 5 side can be used by the DU 7, so that the DU 7 having the same configuration is used regardless of whether the instruction code has a variable length or not. Debugging function can be added. That is, by adding the function of outputting data φa, φc and φt to PU5, the DU7 detects the address match for the next instruction pointer data φa, so that it is not necessary to monitor the instruction length. By performing code coincidence detection on the data φc, a decoding process for aligning bus data in accordance with addresses becomes unnecessary. Further, since the instruction code resulting from the branch control performed on the PU 5 side is obtained, the control is also unnecessary. Since the instruction completion timing of the execution stage is known from the timing signal φt from the execution unit 13, it is not necessary to analyze whether or not the instruction code is multi-cycle.
[0041]
Further, the DU 7 does not require hardware that is aware of the instruction code that is discarded because the branch condition is satisfied. In PU5, since an instruction that is not executed is not passed to the execution stage, the next instruction code data φc and the next instruction execution start timing signal φt for latching it in the execution stage are combined in the execution stage in DU7. This is because it is possible to reliably monitor the instruction code data passed to.
[0042]
On the other hand, the PU 5 is simply provided with points 31 to 33 for outputting these data φa, φc and φt in advance, so that software, hardware can be designed, developed and maintained without causing any problem of the debugging function. can do. The hardware configuration of these connection points 31 to 33 is not limited to the above, and it is sufficient that a signal or data can be transmitted to an option unit such as a debug unit in the boundary of PU5 of LSI2. . In the debug unit of the above example, both the next instruction pointer data φa and the next instruction code data φc are received and the respective data φa and φc are compared with the break address φta and the break data φc. A break signal may be output by comparing at least one of the instruction pointer data φa and the next instruction code data φc with a target value.
[0043]
  Furthermore, the option unit is not limited to the debug unit, but the user unit that can utilize these signals most effectively is the debug unit. With such a processor, it is only necessary to design, develop and maintain a single-spec processor for a processor for embedding a system LSI, but can save extra investment. Therefore, according to the present invention, it is possible to provide a processor with abundant optional functions suitable for an embedded processor, and it is possible to provide a PU 5 further suitable for a VUPU architecture. Further, by providing the present invention not only to the VUPU architecture but also to other types of embedded processors, it is possible to provide a processor with more rich optional functions.A typical debug unit is a debug unit having a break signal output means for supplying a break signal for requesting a pause to the processor unit when a break condition is satisfied, and a target instruction set as the break condition First input means for receiving next instruction pointer data to be compared with pointer data from the outside of the debug unit, and next instruction code data to be compared with target instruction code data set as the break condition outside the debug unit Second input means for accepting from. The debug unit has third input means for accepting the timing at which execution of the next instruction code data starts from the outside of the debug unit, and the break signal output means includes at least the instruction pointer data of the target and the target Preferably, any one of the instruction code data, the next instruction pointer data, and the next instruction code data coincide with each other, and the break signal is output when execution of the next instruction code data is started. A typical debug unit control method includes a next instruction pointer data to be compared with target instruction pointer data set as a break condition, and a next instruction code to be compared with target instruction code data set as the break condition. A step of accepting at least one of data from the outside of the debug unit, and a break requesting step of supplying a break signal for requesting the processor unit to pause when the break condition is satisfied. The control method includes a step of accepting a timing at which the next instruction code data starts to be executed from the outside of the debug unit. In the break request step, at least one of the instruction pointer data of the target and the instruction code data of the target Preferably, the break signal is output when the next instruction code data coincides with the next instruction code data and the next instruction code data is started to be executed.
[0044]
【The invention's effect】
As described above, in the present invention, the processor unit is provided with an interface for outputting the next instruction pointer data and the next instruction code data to the outside, so that it is effective between the embedded processor and the optional debug unit. It is possible to install a state transmission signal line. Therefore, the functions of the processor body and the debug unit can be coordinated, and the hardware load on the debugger can be reduced. Further, when a system LSI is constructed, it is possible to prevent duplication of hardware and easily mount optional functions such as a debug function. For this reason, a compact and low-cost multifunctional system LSI can be provided.
[Brief description of the drawings]
FIG. 1 is a diagram showing an outline of an LSI mounting system board on which a data processing apparatus according to the present invention is mounted.
FIG. 2 is a block diagram showing an outline of a data processing apparatus according to the present invention.
FIG. 3 is a diagram for explaining signals exchanged between a PU and a DU in this example;
FIG. 4 is a diagram showing details of PUs and DUs in this example.
FIG. 5 is a flowchart showing debug processing performed between a PU and a DU in this example.
FIG. 6 is a timing chart for explaining processing in which processing in an execution unit of a PU is stopped when a break condition is established in DU.
[Explanation of symbols]
1 System board with LSI
2 Data processing device (system LSI)
5 Processor unit (PU)
6 Dedicated data processing unit (VU)
7 Debug unit (DU)
8, 10 interface
11 Code RAM
12 Fetch unit (FU)
13 execution units
31, 32, 33, 34 Connection point
55 Break detector
61, 62, 62, 64 connection point

Claims (8)

Data processing having a processor unit that includes a fetch unit that outputs a fetch address based on instruction pointer data, can generate instruction code data from the obtained data, and an execution unit that can execute processing based on the instruction code data A device,
The fetch unit includes a data alignment unit that decodes the obtained data to generate variable-length instruction code data,
The processor unit further includes instruction code data decoded by the fetch unit, the next instruction pointer data of the next instruction code data to be executed by the execution unit next to the current instruction code data in the execution unit. First output means for outputting to the outside from the processor unit;
And a second output means for outputting the next instruction code data from the processor unit to the outside. In claim 1, further comprising a debug unit having a break signal output means for supplying a break signal for requesting a pause to the processor unit when a break condition is satisfied,
The debug unit further includes first input means for receiving the next instruction pointer data to be compared with target instruction pointer data set as the break condition;
And a second input means for receiving the next instruction code data to be compared with the target instruction code data set as the break condition. In Claim 2, the processor unit further comprises a third output means for outputting a start timing for starting processing based on the next instruction code data from the processor unit to the outside.
The debug unit further includes third input means for receiving the start timing, and the break signal output means includes at least one of the target instruction pointer data and the target instruction code data, and A data processing apparatus that outputs the break signal when either the next instruction pointer data matches the next instruction code data and the next instruction code data starts execution. The processor unit according to claim 2, further comprising third output means for outputting, from the processor unit, a completion timing at which the processing based on the current instruction code data in the execution unit is completed,
The debug unit further includes third input means for accepting the completion timing, and the break signal output means includes at least one of the instruction pointer data of the target and the instruction code data of the target, A data processing apparatus that outputs the break signal when either the next instruction pointer data matches the next instruction code data and the next instruction code data starts execution. In any one of Claims 1 thru | or 4, it has a dedicated processing unit provided with the dedicated circuit suitable for dedicated processing further,
The fetch unit of the processor unit supplies, as the instruction code data, general-purpose instruction code data that defines the processing in the processor unit to the execution unit, and the dedicated instruction code data that defines the processing in the dedicated processing unit. Data processing device that supplies the unit. A fetch unit that outputs a fetch address based on the instruction pointer data and generates instruction code data from the obtained data;
A processor unit having an execution unit capable of executing processing based on the instruction code data,
The fetch unit includes a data alignment unit that decodes the obtained data to generate variable-length instruction code data,
The processor unit further includes instruction code data decoded by the fetch unit, the next instruction pointer data of the next instruction code data to be executed by the execution unit next to the current instruction code data in the execution unit. First output means for outputting to the outside from the processor unit;
And a second output means for outputting the next instruction code data from the processor unit to the outside.   7. The processor unit according to claim 6, further comprising third output means for outputting a timing for starting processing based on the next instruction code data from the processor unit to the outside.   7. The processor unit according to claim 6, further comprising third output means for outputting the timing at which the processing based on the current instruction code data in the execution unit is completed to the outside from the processor unit.

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