JP4645642B2 - Solid-state imaging device - Google Patents

Description

The present invention relates to a solid-state imaging device including a dynamic operation comparator capable of reducing power consumption and size of a circuit.

As this type of comparator, one disclosed in US Pat. No. 6,369,737 B1, “Figure 10” (hereinafter referred to as a document) is known.
FIG. 5 is a circuit diagram showing a circuit disclosed in this document.
This circuit is an example of a comparator provided in a readout circuit of a solid-state imaging device, and analog signals read out from photodiodes D0 to D3 constituting four pixels through MOS transistors M1 to M8 are comparators (M9 to M9). M17, M21) 102 and latch circuit (M18 to M20) 104 are converted into digital signals by A / D converter 100.

That is, in this circuit, the signal charges generated by the photodiodes D0 to D3 are read out by the operations of the gate transistors M1 to M4 and accumulated in the transistors M5 to M8 as capacitors.
The comparator 102 compares the pixel signal level read to the transistors M5 to M8 by the transistor pair M10 and M11 with the level of the ramp (RAMP) signal having a predetermined time constant, and the ramp signal level is set to the pixel signal level. When it exceeds, the divided voltage output by the transistors M14 to M17 is inverted.
The latch circuit (1-bit latch circuit) 104 latches the value of BITX when the comparator output is inverted. By reading this value later, data corresponding to the pixel signal level is obtained.

However, since the comparator configured as described above uses a constant current source (M9), a voltage dividing circuit (M14 to M17), a current mirror (M13, M14), etc., a steady bias current is required. There is a problem that power consumption is large.
Further, a total of nine transistors (M9 to M17) are required, and there is a disadvantage that the circuit scale becomes large.

Accordingly, an object of the present invention is to provide a solid-state imaging device that can be driven without flowing a steady current, can be configured with a small number of transistors, and can reduce power consumption and circuit size.

In order to solve the above-mentioned problems and achieve the object of the present invention, a solid-state imaging device of the present invention comprises a pixel array unit comprising a plurality of pixels and photoelectrically converting an optical signal from each pixel to generate an image signal; This is a solid-state imaging device including a comparator and a latch circuit for A / D converting an image signal from the pixel array unit.
In the comparator as the central configuration of the solid-state imaging device, the first voltage input terminal is connected to the carrier control terminal, and the second voltage input terminal is connected to one of the carrier supply terminal and the carrier reception terminal. A first field effect transistor is provided. In addition, the first reset pulse is supplied to the first capacitor connected to the other of the carrier supply terminal or the carrier reception terminal of the first field effect transistor and the carrier control terminal, and the power supply voltage is charged to the first capacitor. And a second field effect transistor for resetting the output voltage of the first capacitor. Furthermore, a carrier control terminal is connected to the first capacitor, and a third field effect transistor is provided in which one of the carrier supply terminal and the carrier reception terminal is connected to the power supply voltage.
The fourth field effect is connected to the other of the carrier carrier supply terminal and the carrier reception terminal of the third field effect transistor, and the carrier control terminal is supplied with the second reset pulse or the output from the first capacitor. A transistor, and a second capacitor connected to a connection point of the third field effect transistor and the fourth field effect transistor.
Then, after the second field effect transistor resets the first capacitor, the two voltages input to the first voltage input terminal and the second voltage input terminal are compared by the threshold voltage of the first field effect transistor. As a result of this comparison, a signal flowing from the second voltage input terminal to the output terminal via the first field effect transistor is accumulated in the first capacitor. Furthermore, after the fourth field effect transistor resets the second capacitor, the output voltage of the first capacitor is stored in the second capacitor via the third field effect transistor, and the second capacitor The output voltage is supplied to the latch circuit .

According to the solid-state imaging device of the present invention , the comparator has a first input terminal provided on the carrier control terminal of one field effect transistor and a second input terminal provided on either the carrier supply terminal or the carrier receiving terminal. Since the two signals to be compared are input and the two signals are compared according to the current state at the output terminal provided on either the carrier supply terminal or the carrier reception terminal of the field effect transistor, a steady current is used. Therefore, a comparator can be configured with a small number of transistors, and a small solid-state imaging device with low power consumption can be realized.

Embodiments of the solid-state imaging device according to the present invention will be described below.
1A and 1B are diagrams showing a basic form of a comparator according to a first embodiment of the present invention. FIG. 1A is a circuit diagram and FIG. 1B is a timing chart.
The comparator of this example compares two input signals by a dynamic operation using a MOS transistor and a capacitor instead of a static operation using a steady current. The comparator of the MOS transistor (N channel MOS transistor in this example) Of the gate (carrier control terminal), source (carrier supply terminal), and drain (carrier reception terminal), the gate (first input terminal) and the source (second input terminal) are compared with the two By supplying the input signal and storing the current flowing in the drain (output terminal) in the capacitor, and outputting the voltage output as a comparison result signal, it has an ultra-low power consumption that does not require a steady current and an ultra-simple structure A comparator is realized.

Hereinafter, a specific description will be given with reference to FIG.
First, in the MOS transistor (first field effect transistor) Tr1, the first input voltage V1 is input to the gate, the second input voltage V2 is input to the source, and the capacitor (first capacitor) C1 is the drain. To the ground (GND).
The connection point between the MOS transistor Tr1 and the capacitor C1 is an output terminal (node A), and the output voltage Vout is connected to a high impedance node such as the gate of an output transistor (not shown).
Note that the capacitor C1 may be individually formed, or the parasitic capacitance of the node A may be used.

A P-channel MOS transistor (first reset means = second field effect transistor) Tr2 is connected to the output terminal (node A) of the MOS transistor Tr1.
The reset pulse Rp is input to the gate of the MOS transistor Tr2, the drive voltage (first reference potential) Vdd is input to the source, the drain is connected to the output terminal (node A), and the MOS transistor Tr2 Is turned on by a reset pulse Rp to reset the potential of the output terminal (node A) of the MOS transistor Tr1 to Vdd.

Next, the operation of such a comparator will be described.
First, in a reset period in which the MOS transistor Tr2 is turned on, the node A is at a high level.
After that, if V2> V1-Vth, the voltage of the node A is held at the high level. Vth is the threshold voltage of the MOS transistor Tr1.
If V2 <V1-Vth, electrons are injected into the node A from the V2 side, resulting in a voltage equal to V2.
As a result, the magnitudes of V2 and V1-Vth are distinguished and output as the output voltage Vout.
Therefore, if the design is such that V1-Vth falls within the low level range, the magnitude of V2 and V1-Vth can be determined.

When an analog value (an intermediate value between Vdd and GND) is input to V2, the low level of Vout is also an analog value. When a digital value (Vdd or GND) is input, the output is also digital.
Since there is an offset by Vth, in the case of digital, it is possible to determine whether V1> V2 or V1 ≦ V2.
This circuit is a dynamic circuit. That is, before the capacitor C1 spontaneously discharges, the output voltage Vout is read, the output voltage Vout is latched, or the node A is refreshed.
In the case of V2 <V1-Vth, the current flows only at the time of resetting, and the steady current does not flow, so that the power consumption is low.

Furthermore, it is possible to prevent a current during reset from flowing.
In this method, (1) V2 is set to High at the time of resetting and then set to the voltage to be compared, or (2) A switch is provided between V2 and Vdd and turned off at the time of resetting. There is a way. The method (1) will be described with reference to the example of FIG. The method (2) will be described with reference to the example of FIG.

Next, a second embodiment of the present invention will be described.
2A and 2B are diagrams showing a modification of the comparator according to the second embodiment of the present invention. FIG. 2A is a circuit diagram and FIG. 2B is a timing chart.
In addition to the configuration shown in FIG. 1, the comparator of this example includes a P-channel MOS transistor (third field effect transistor) Tr3, an N-channel MOS transistor (second reset means = fourth field effect transistor) Tr4, And a capacitor (second capacitor) C2.
The gate of the MOS transistor Tr3 is connected to the anode A, the source is connected to the drive voltage Vdd, the drain is connected to the source of the MOS transistor Tr4 and the capacitor C2, and this source serves as an output terminal (output voltage Vout) in a subsequent stage (not shown). It is connected to a high impedance node (such as the gate of the next stage transistor).
Further, the reset pulse Rn of the node A is input to the gate of the MOS transistor Tr4, the drain is grounded (GND), and the voltage of the capacitor C2 is reset to the ground (second reference potential) according to the reset pulse Rn. To do.
Note that the capacitor C2 may be formed individually as in the case of the capacitor C1, or the parasitic capacitance of the output terminal may be used.

Next, the operation of such a comparator will be described.
First, in a reset period in which the MOS transistors Tr2 and Tr4 are turned on, the node A is at a high level and the MOS transistor Tr3 is turned off. Further, since the MOS transistor Tr4 is on, the output voltage Vout is at a low level.
After that, if V2> V1−Vth, the voltage of the node A remains at the high level, and Vout also remains at the low level.
Further, if V2 <V1-Vth, electrons are injected into the node A from the V2 side, the voltage becomes equal to V2, and the design is such that V1-Vth is in the low level range. The output voltage Vout becomes High level.

With such a configuration, even if V2 is an intermediate voltage, Vout fully swings with a width of Vdd and GND. Further, it is not necessary for V2 to drive the output terminal.
Although there is a possibility that a through current flows through the MOS transistors Tr3 and Tr4 at the beginning of the reset pulse, this can be prevented by slightly delaying the phase of the reset pulse Rn with respect to the reset pulse Rp.

Next, a third embodiment of the present invention will be described.
3A and 3B are diagrams showing a modification of the comparator according to the third embodiment of the present invention. FIG. 3A is a circuit diagram and FIG. 3B is a timing chart.
In addition to the configuration shown in FIG. 2, the comparator of this example is an N-channel MOS transistor that opens and closes between an input voltage V2 and the source of the MOS transistor Tr1 by a control signal CNT (input control means = fifth field effect transistor). Tr5 is newly added, and the gate of the MOS transistor Tr4 shown in FIG.

Next, the operation of such a comparator will be described.
First, normally, the control signal CNT is set to the Low level, and the input signal V2 is disconnected from the MOS transistor Tr1. In this state, in the reset period, the node A is at a high level, and the output voltage Vout is at a low level.
Thereafter, when the control signal CNT is set to the high level, if V2> V1-Vth, the voltage of the node A remains at the high level and the output voltage Vout also remains at the low level.
However, if V2 <V1-Vth, electrons are injected into the node A from the input voltage V2 side, the voltage becomes equal to V2, and the MOS transistor is designed so that V1-Vth is in the low level range. Tr3 is turned on and the output voltage Vout becomes High level.
At this time, it is preferable to increase the Vth of Tr4 or apply a substrate bias to Tr4 so that the MOS transistor Tr4 is turned off.

In such a configuration, unlike the example of FIGS. 1 and 2, since the output of the node A becomes the output of the CMOS inverter circuit by the MOS transistors Tr1 and Tr5, the output voltage Vout is connected to a terminal through which a non-high impedance current flows. Can do.
Also, unlike the example of FIGS. 1 and 2, since the switch (MOS transistor Tr5) is provided to cut the input signal V2, the voltage of the input signal V1 or the input signal V2 is changed after the control signal CNT is set to Low level. Even if the voltage is changed, the voltage level of the output voltage Vout can be maintained. However, since the circuit is a dynamic circuit, the holding time is limited.
Unlike the examples of FIGS. 1 and 2, since the MOS transistor Tr5 is turned off at the time of resetting, no current flows between V2 and Vdd at the time of resetting, resulting in ultra-low power consumption.

Next, a fourth embodiment of the present invention will be described.
In the example shown in FIGS. 1 to 3 described above, since all of the circuits are dynamic circuits, the holding time is limited. However, if a latch circuit is provided in the next stage, the limitation can be eliminated.
Although various circuit configurations are possible for realizing this, in the following description, an example used for a comparator for an A / D converter provided in a readout circuit of a solid-state imaging device will be described.

4A and 4B are diagrams showing an application example of the comparator according to the fourth embodiment of the present invention. FIG. 4A is a circuit diagram and FIG. 4B is a timing chart.
This corresponds to the circuit configuration of the conventional example shown in FIG. 5, and is an example of a circuit in which an A / D converter is provided in a pixel of a solid-state imaging device to convert an imaging signal into a digital signal and output it. .
First, the pixel array unit 10 includes photodiodes D0 to D3 as photoelectric conversion units and MOS transistors for reading signal charges from the photodiodes D0 to D3, in a plurality of pixels (four pixels are shown in the figure). M1 to M4 are provided. In FIG. 4, MOS transistors (M5 to M8 in FIG. 5) serving as capacitors for storing the signal charge of each pixel are combined into one capacitor C3.

The A / D converter performs A / D conversion of the pixel signal output from the pixel array unit 10 by the comparator 20 and the 1-bit latch circuit 30.
The portion of the broken line frame a is the comparator 20, and the MOS transistors Tr1, Tr2, Tr3, Tr4 and the capacitor C1 are common to those in FIG.
A capacitor C3 is provided at the node V1 between the pixel array unit 10 and the comparator 20, and a reset MOS transistor TrR is provided between the node V1 and the drain of the MOS transistor Tr1. ing. The MOS transistor TrR constitutes reset means for initializing the voltage of the gate (first input terminal) of the MOSTr1 when the MOS transistor TrR is turned on.

The latch circuit (1-bit latch circuit) 30 includes a MOS transistor Tr6 whose gate is connected to the output terminal of the comparator 20, MOS transistors Tr7 and Tr8 for taking out clock bits output from the MOS transistor Tr6, And a fourth capacitor C4 connected to the source of the MOS transistor Tr6.
A clock (BITX) is input to the drain of the MOS transistor Tr6, and BITX is supplied from the source of the MOS transistor Tr6 to the gate of the MOS transistor Tr7 and the capacitor C4 while the output voltage Vout of the comparator 20 is on. When the output voltage Vout of the comparator 20 is turned off, the value of BITX at that time is latched in the capacitor C4.

The timing signal WORD is supplied to the gate of the MOS transistor Tr8, and the WORD is turned on later to output the latched signal to the outside through the signal line (BIT).
The capacitor C4 is not explicitly shown in the conventional example of FIG. 5, but is clearly shown in FIG. 4 because it is necessary for holding the voltage.

Next, since the operating principle of such a solid-state imaging device is known per se, the operation of the comparator shown in FIG. 4 will be mainly described here.
First, in FIG. 4, nodes V <b> 1 and V <b> 2 are inputs to the comparator 20.
A photodiode signal is input to the node V1. A ramp (sweep) wave is input to V2, and the output (node B) of the comparator 20 is inverted at some level.
Here, for the sake of simplicity, a 3-bit (bit) A / D conversion operation will be described with reference to FIG. Here, the voltage level of the input voltage V2 at which the output of the comparator 20 is inverted when the voltage level of the photodiode signal is 0 is set to 0, and the input voltage V2 at which the output of the comparator 20 is inverted when the voltage level of the photodiode signal is maximum. The voltage level is 8.

Hereinafter, the state of each unit in the case where the pixel signal of the photodiode D0 is read out in accordance with the timings t0 to t26 illustrated in FIG.
First, at t0, it is a state before the operation of the comparator 20, and V2 is at a high level.
Next, at t1, when the gate pulse S0 of the photodiode D0 is set to High, the photodiode D0 is connected to the comparator 20 side.
Next, at t2, the comparator 20 is reset. At this time, since V2 is High, no current flows through V2. The node B, which is the comparator output, is set to Low and the MOS transistor Tr6 is turned on, so that the voltage value of BITX appears in the capacitor C4.

Next, at t4 to t8, when 1, 3, 5, 7, and Low levels are sequentially input to V2, the comparator output is inverted at some point. Therefore, when this inversion is performed, the transistor Tr6 is turned off, and the voltage of BITX at that time is held in the capacitor C4, which becomes the value of the lower bit (lower bit latch).
At t9, WORD is set to Low during this period, and the lower bits are output outside the pixel. At t11, the comparator is reset.
Next, from t13 to t15, levels 2, 6, and Low are sequentially input to V2, and the middle bit is latched. At t16, the middle bit is output. At t17, the comparator is reset.

Next, at t19 and t20, 4 and Low levels are sequentially input to V2, and the upper bit is latched. At t21, the upper bit is output.
At t22, the comparator is reset and the reset transistor TrR is turned on. As a result, the node A and the node V1 become Vdd. V2 is set to Vdd.
At t23 and t24, after reset pulses Rp and Rn are returned, V2 is set to 0 level. Then, electrons are injected from the node V2 to the node V1 until the level reaches the level V2 (until V2 = V1-Vth), and the photodiode D0 also has the voltage value. As a result, D0 is reset to the level of signal 0. Even if there is a Vth variation of the transistor Tr1, this operation cancels the Vth variation.

In the conventional example shown in FIG. 5, the output of the comparator is fed back to reset the photodiode D0, and the Vth variation is suppressed to 1 / gain using the comparator gain.
However, the comparator of this example uses a different principle as described above. In principle, Vth variation can be suppressed up to kTC noise regardless of the comparator gain. It is valid.
At t25 and t26, the reset pulse RESET and the gate pulse S0 are turned off in this order, and V2 is returned to High to complete the operation.
The above is the operation related to the photodiode D0, and the other photodiodes D1 to D3 are read by the same operation thereafter.

In the conventional example shown in FIG. 5, the number of transistors in the comparator section is nine. However, in the example to which the present invention is applied, only four transistors are required. In the conventional example, a steady bias current is required for the operation of the comparator, but in this example of the present invention, a steady bias current is not necessary.
As described above, the comparator of this example can be realized with a simple configuration using a small number of transistors without using a steady-state current, so that the circuit scale and power consumption can be reduced. However, this comparator compares the magnitudes of V1-Vth and V2, not the magnitudes of the two input signals V1 and V2, but is very effective when used under the appropriate conditions as described above. It becomes a means.
In the above example, a MOS transistor is used as a field effect transistor, but other field effect transistors can be used as long as they have similar functions.

As described above, in the solid-state imaging device of this example, the comparator has two terminals of one field-effect transistor as input terminals and one terminal as an output terminal, and two input terminals depending on the current state at the output terminal. Since the magnitude relations of the signals input to are compared, a comparator can be configured with a small number of transistors without using a steady current, and there is an effect that a small solid-state imaging device with low power consumption can be realized.

It is a figure which shows the comparator by the 1st Example of this invention, (A) is a circuit diagram, (B) is a timing chart. It is a figure which shows the comparator by the 2nd Example of this invention, (A) is a circuit diagram, (B) is a timing chart. It is a figure which shows the comparator by the 3rd Example of this invention, (A) is a circuit diagram, (B) is a timing chart. It is a figure which shows the comparator by the 4th Example of this invention, (A) is a circuit diagram, (B) is a timing chart. It is a circuit diagram which shows the structural example of the pixel circuit which provided the conventional comparator.

Explanation of symbols

  Tr1 to Tr8, TrR, M1 to M8... MOS transistors, C1 to C4... Capacitors, D0 to D3.

Claims (1)

It consists of a plurality of pixels, and consists of a pixel array unit that photoelectrically converts optical signals from each pixel to generate image signals, and a comparator and latch circuit for A / D conversion of image signals from the pixel array unit. A solid-state imaging device,
The comparator is
A first field effect transistor having a first voltage input terminal connected to the carrier control terminal and a second voltage input terminal connected to one of the carrier supply terminal or the carrier receiving terminal ;
A first capacitor connected to the other of the carrier supply terminal and the carrier reception terminal of the first field effect transistor;
A second field effect transistor that is supplied with a first reset pulse at a carrier control terminal, charges a power supply voltage to the first capacitor, and resets an output voltage of the first capacitor ;
A third field effect transistor having a carrier control terminal connected to the first capacitor and one of a carrier supply terminal or a carrier reception terminal connected to a power supply voltage ;
A fourth field effect transistor connected to the other of the carrier carrier supply terminal and the carrier reception terminal of the third field effect transistor, and supplied with the output from the second reset pulse or the first capacitor to the carrier control terminal ; ,
A second capacitor connected to a connection point of the third field effect transistor and the fourth field effect transistor ,
After the second field effect transistor resets the first capacitor, two voltages input to the first voltage input terminal and the second voltage input terminal according to a threshold voltage of the first field effect transistor As a result of comparing the above, a signal that flows from the second voltage input terminal to the output terminal via the first field effect transistor is accumulated in the first capacitor,
After the fourth field effect transistor resets the second capacitor, the output voltage of the first capacitor is stored in the second capacitor via the third field effect transistor, and the second capacitor Supplying the output voltage of two capacitors to the latch circuit ;
A solid-state imaging device.

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