JP4645840B2 - Integrated circuit device, microcomputer and electronic device - Google Patents

Description

  The present invention relates to an integrated circuit device, a microcomputer, and an electronic apparatus.

In CPUs and microcomputers, access to built-in SRAM, SDRAM, etc. frequently occurs with programs, data, and the like. In the integrated path device that accesses the built-in SRAM, SDRAM, or the like, the power consumption increases when a clock is always supplied to a bus master such as a CPU that is powered on.
JP-A-9-114539

  Therefore, in CPUs and microcomputers, even when the power is turned on, the bus master is in a wait state to stop the clock and save power.

  However, conventionally, since the CPU clock is stopped in the wait state, the clock cannot be shared with a functional module that does not want to stop the clock.

  However, for example, the serial I / F supplied to the bus master in the bus wait state communicates in synchronization with the clock, so the clock cannot be stopped during the serial communication. For this reason, the clock lines were divided and the design was complicated.

  In other words, if the clock is stopped in the wait state, it is necessary to separate the clock supply between the bus master and the peripheral circuit that is in trouble when the clock is stopped in the bus wait state, and the clock can be controlled by the same clock root buffer. Can not.

  Here, in the same clock route buffer, the tool automatically adjusts the skew. However, if the clock route is divided, it is necessary to provide a separate clock route buffer. Since the tool does not adjust the skew between the separate clock root buffers, the skew between the clock root buffers must be adjusted manually, and repeated manual adjustments (including delay cells, inverters, etc.) ) Is necessary, which increases the workload.

  The present invention has been made in view of the above problems, and in an integrated circuit device, an integrated circuit that can supply a clock to a circuit that wants to stop the clock and a circuit that does not want to stop the clock with a single clock root buffer. The purpose is to provide a circuit.

(1) The present invention is an integrated circuit device,
A bus master circuit including a Philip flop circuit with a write protection function;
A bus slave circuit that processes a request from the bus master circuit and returns a response to the bus master;
A peripheral circuit that receives clock supply via the same clock route buffer as the bus master circuit;
A clock supply control circuit that performs supply control of a clock supplied to the bus master circuit and the peripheral circuit via the same clock route buffer,
The bus slave circuit is
When a response cannot be returned within a predetermined period to the request from the bus master circuit, a wait signal is output,
The peripheral circuit is
It is configured to output a clock request signal for preventing a clock supply stop in a predetermined case,
The clock supply control circuit includes:
Based on the wait signal and the clock request signal, supply control of the clock supplied to the bus master circuit and the peripheral circuit is performed.
The write-proof Philip flop circuit is
It is characterized in that it is configured to prevent new data from being written to the Philip flop based on the wait signal.

  All the Philip Flock circuits included in the bus master circuit may be configured as Philip flop circuits with a write protection function.

  The clock supply control circuit may be configured to perform control to stop the supply of the clock when the wait signal is in a wait state and the clock request signal does not indicate prevention of clock supply stop. Even when the wait signal is in the wait state, the clock supply is not stopped if the clock request signal indicates prevention of clock supply stop.

  By doing so, it is possible to measure power saving by stopping the supply of the clock only when the supply of the clock to the peripheral circuit may be stopped in the wait state.

  The Philip flop circuit with a write protection function includes a lip flop with a synchronous input and a circuit for preventing writing to the Philip flop.

  In addition, the Philip flop circuit with a write prevention function may be configured to prevent new data from being written to the Philip flop when the wait signal is in the wait state. In this way, when the clock is supplied in the wait state (when the peripheral circuit outputs a clock request signal for preventing the clock supply from being stopped), new writing to the Philip flop is prohibited. Therefore, malfunction of the bus master circuit can be prevented.

  However, if the clock supplied to the bus master is stopped in the bus wait state, it is necessary to separate the clock supply between the bus master and the peripheral circuit that is in trouble if the clock stops in the bus wait state. Can not do.

  According to the present invention, only one clock route buffer needs to be provided for the bus master circuit and the peripheral circuit, so that the design load is small. Further, it is possible to prevent a malfunction that is configured to prevent new data from being written to the lip-flop of the bus master circuit in the wait state.

  As described above, according to the present invention, it is possible to provide an integrated circuit device having both a function of stopping the clock of the entire bus master when a wait is applied to the bus and a function of waiting without stopping the clock.

(2) The present invention is an integrated circuit device,
A first circuit comprising a Philip flop circuit with a write protection function;
A second circuit that processes a request from the first circuit and returns a response to the first circuit;
A third circuit that receives a clock through the same clock root buffer as the first circuit;
A clock supply control circuit that performs supply control of a clock supplied to the first circuit and the third circuit via the same clock route buffer;
The second circuit includes:
When a response cannot be returned within a predetermined period to the request from the first circuit, a wait signal is output,
The third circuit includes:
It is configured to output a clock request signal for preventing a clock supply stop in a predetermined case,
The clock supply control circuit includes:
Based on the wait signal and the clock request signal, supply control of the clock supplied to the first circuit and the third circuit is performed.
The write-proof Philip flop circuit is
It is characterized in that it is configured to prevent new data from being written to the Philip flop based on the wait signal.

(3) The integrated circuit device of the present invention
The Philip flop circuit with the lower write prevention function,
It is characterized in that new data is prevented from being written to the Philip flop by rewriting the data of the Philip flop on the Philip flop based on the wait signal.

  For example, one of the inputs is connected to the output of the Philip flop, the other input is connected to the Philip flop input signal, a selection circuit (MAX) for selecting the input signal based on the selection signal and outputting the selected input signal. In addition, the output of the selection circuit may be connected to the input of the Philip flop. Here, the selection signal may be generated based on the weight signal. For example, the selection circuit may be configured to output a Philip flop output when the wait signal indicates a wait state. It is within the scope of the present invention to perform control based on both the wait signal and the write enable signal for performing write control on each lip flop.

  In this way, in the wait state, the data of the Philip flop is again written to the Philip flop, and new data can be prevented from being written to the Philip flop.

(4) The integrated circuit device of the present invention is
The write-proof Philip flop circuit has
By masking the clock supplied to the Philip flop based on the wait signal, new data is prevented from being written to the Philip flop.

  For example, a clock mask circuit that masks the clock based on the wait signal may be provided so that the output clock of the clock mask circuit is used as the clock input of the Philip flop. It is also within the scope of the present invention to control the mask of the clock based on both the wait signal and the write enable signal for performing write control on each lip flop.

  In this way, in the wait state, the clock is masked and no clock is supplied to the Philip flop, so that new data can be prevented from being written to the Philip flop.

(5) The integrated circuit device of the present invention is
The bus master circuit is a CPU.

(6) The integrated circuit device of the present invention is
The peripheral circuit is a communication module that performs communication at a determined communication speed.

(7) The integrated circuit device of the present invention is
The first circuit is a CPU.

(8) The integrated circuit device of the present invention is
The third circuit is a communication module that performs communication at a determined communication speed.

(9) The present invention
A microcomputer including any one of the integrated circuit devices described above.

(10) The present invention
A microcomputer as described above;
Means for receiving input information;
Means for outputting a result processed by the information processing device based on input information;
It is an electronic device characterized by including.

  DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

1. In the following, a preferred embodiment of the present invention will be described in detail with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. Also, not all of the configurations described below are essential constituent requirements of the present invention.

  FIG. 1 is a functional block diagram for explaining the configuration of the integrated circuit device of the present embodiment. FIG. 2 is a diagram showing the states of the wait signal and the clock request signal and the control contents of the clock supply control circuit and the lip-flop circuit with a write prevention function.

  The integrated circuit device 10 of the present embodiment performs processing in response to a request from the bus master circuit 20 including the lip-flop circuits 80-1,. A bus slave circuit that returns a response to the bus master, a peripheral circuit 40 that is supplied with a clock via the same clock route buffer 60 as the bus master circuit 2, and the same clock root buffer for the bus master circuit 20 and the peripheral circuit 40 And a clock supply control circuit 50 that performs supply control of a clock supplied via 60.

  The bus master circuit 20 transmits an address 72 via the bus slave circuit 30 and the bus 70 to exchange data 74. The bus master circuit 20 may be, for example, a CPU, and the bus slave circuit 30 may be, for example, an SRAM or SDRAM with a built-in IC.

  The bus slave circuit 30 outputs a wait signal 32 when a response cannot be returned within a predetermined period to a request from the bus master circuit 20 (for example, a data read or write request). The wait signal 32 may be configured to be at a first level (for example, H level) when in a wait state, and to be at a second level (for example, L level) when not in a wait state.

  The peripheral circuit 40 is configured to output a clock request signal 42 for preventing a clock supply stop in a predetermined case. The clock request signal 42 is set to the first level (for example, H level) when the peripheral circuit 40 needs to be supplied with a clock, and is set to the second level (for example, L level) when the clock supply is not required. It may be configured.

The peripheral circuit 40 may be, for example, a communication module that performs communication at a determined communication speed. The clock supply control circuit 50 is supplied to the bus master circuit 20 and the peripheral circuit 40 based on the wait signal 32 and the clock request signal 42. The clock supply control is performed.

  The clock supply control circuit 50 is configured to perform control to stop the clock supply when the wait signal 32 is in the wait state and the clock request signal 42 does not indicate prevention of clock supply stop (310 in FIG. 2). reference). Even if the wait signal is in the wait state, the clock supply is not stopped if the clock request signal indicates that the clock supply is stopped (see 320 in FIG. 2).

  When the wait signal is in a non-wait state, a clock is supplied (see 330 in FIG. 2).

  The clock supply control circuit 50 can be configured to include, for example, a first AND circuit 52, a latching lip flop 56, and a second AND circuit 58. The first AND circuit 52 inputs an inverted signal of the clock request signal 42 and the wait signal 32 and takes an AND, and outputs the inverted signal as a clock enable signal 54. The latching lip flop 56 may be a D lip flop having the clock enable signal as a D input and the oscillation clock 110 as a clock input. The second AND circuit 58 is an AND circuit that receives the output of the latching lip flop and the transmission clock 110, and the output is input to the clock route buffer 60.

  By doing so, it is possible to measure power saving by stopping the supply of the clock only when the supply of the clock to the peripheral circuit may be stopped in the wait state.

  The write-proof function lip flop circuits 80-1,..., 80-n are configured to prevent new data from being written to the lip flop based on the wait signal 32. Here, the Philip flop may be a Philip flop having a synchronous input (D Philip flop, T Philip flop, RS Philip flop, JK Philip flop, etc.).

  All the Philip Flock circuits included in the bus master circuit may be configured as Philip flop circuits with a write protection function.

  The write-proof function lip flop circuits 80-1,..., 80-n are configured to prevent new data from being written to the lip flop when the wait signal 32 is in the wait state. (See 320 in FIG. 2). In this case, when the clock is supplied in the wait state (when the peripheral circuit 40 outputs the clock request signal 42 for preventing the clock supply from being stopped), new writing to the Philip flop is prohibited. Therefore, malfunction of the bus master circuit 20 can be prevented.

  When the clock request signal 42 is not output in the wait state, the supply of the clock to the bus master circuit 20 is stopped, so that the flip-flop circuits 80-1,. No clock is supplied and no new data is written to the Philip flop (see 310 in FIG. 2).

  According to the present embodiment, it is only necessary to provide one clock route buffer 60 for the bus master circuit 20 and the peripheral circuit 40, and the function and clock for stopping the clock of the entire bus master when a wait is applied to the bus. Therefore, it is possible to provide an integrated circuit device having a function capable of waiting without stopping.

  In addition, the integrated circuit device 10 includes various types such as BCU (Bus Control Unit), MMU (Memory Management Unit), DMAC (Direct Access Memory Controller), LCD (Liquid Crystal Display) driver or SIO (Serial Input Output). Peripheral circuitry can be included.

  FIG. 3 is a diagram for explaining an example of the configuration of the lip-flop circuit with a write prevention function of the present embodiment.

  For example, an example in which an 8-bit Philip flop (86-1,... 86-8) is configured as a Philip flop circuit with a write protection function will be described. In such a case, for each Philip flop (86-1,... 86-8) for each bit, one input is connected to the output 87 of the Philip flop and the other input is input data (Philip flop input signal). 89, a selection circuit (MAX) 84 that selects input signals 84 and 89 based on a write control signal (selection signal) 83 and outputs the selected input signal, and outputs an output 85 of the selection circuit 84 It may be connected to the input of the Philip flop 86-1.

  Here, the write control signal 83 can be generated based on both the wait signal 32 and the write enable signal 81 that permits writing to each lip flop. For example, an AND circuit 82 for inputting the inverted signal of the wait signal 32 and the write enable signal 81 may be provided, and the output 83 of the AND circuit 82 may be used as the selection signal (write control signal 83) of the selection circuit 84.

  In this way, in the wait state, the data of the Philip flop can be written again to the Philip flop 86-1, and new data can be prevented from being written to the Philip flop 86-1.

  4A is a timing chart when the peripheral circuit is in a clock non-request state, and FIG. 4B is a timing chart when the peripheral circuit is in a clock request state.

  The transmission clock 110 is a clock that is input to the clock supply control circuit. The wait signal 32 is a signal output from the bus slave circuit, and becomes H level in the wait state.

  The clock request signal 42 is a signal output from the peripheral circuit, and becomes H level when the peripheral circuit requests supply of a clock.

  The input clock 62 is a clock that is an output of the clock supply control circuit 50, and is a clock that is supplied to the bus master circuit and peripheral circuits via the same clock route buffer.

  The write control signal 83 is a signal that becomes a selection signal of the selection circuit of the lip flop circuit with a write prevention function, and is a signal that is generated based on a wait signal and a write enable signal that controls permission of writing to each lip flop. Here, a case where the write enable signal is in the write permission state will be described.

  In FIG. 4A, since the peripheral circuit is in a clock non-request state, the clock request signal is at L level. In this case, when the wait signal 32 changes from the non-wait state (L level) to the wait state (H level) (see 410), the input clock is masked accordingly (see 420), and the bus master circuit and peripheral circuits receive the clock signal. Supply stops.

  As the wait signal 32 changes from the non-wait state (L level) to the wait state (H level) (see 410), the write control signal of the lip-flop circuit with a write prevention function also becomes H level (selects and outputs the input data). ) To L level (the output of the Philip flop itself is selected output). However, in this case, since no clock is supplied to the bus master circuit, new data cannot be written to the Philip flop, and the power state is low.

  In FIG. 4B, since the peripheral circuit is in the clock request state, the clock request signal is at the H level. In this case, even if the wait signal 32 changes from the non-wait state (L level) to the wait state (H level) (see 460), the input clock is not masked (see 420), and the clock is supplied to the bus master circuit and peripheral circuits. Supplied.

  However, as the wait signal 32 changes from the non-wait state (L level) to the wait state (H level) (see 410), the write control signal of the lip-flop circuit with the write prevention function also becomes H level (selects and outputs the input data). ) To the L level (the output of the Philip flop itself is the selected output), so that new data cannot be written to the Philip flop. Therefore, although not in a low power state, the bus master circuit is in a write-inhibited state, and malfunctions in the wait state can be prevented.

  FIG. 5 is a diagram for explaining another example of the configuration of the lip-flop circuit with a write prevention function of the present embodiment.

  For example, an example in which an 8-bit Philip flop (188-1,... 188-8) is configured as a Philip flop circuit with a write protection function will be described. In this case, the clock input of the Philip flop (188-1,... 188-8) for each bit is connected to the local gate clock which is the output of the clock mask circuit 184.

  The clock mask circuit 184 can be configured to include a latching lip flop 185 and an AND circuit 186. The latching lip flop 185 may be a D lip flop having the write control signal as a D input and the input clock 62 as a clock input. The AND circuit 186 is an AND circuit that receives the output of the latching lip flop 185 and the input clock 62, and the local gate clock that is the output of the lip flop (188-1,... 188-8) for each bit. Input to the clock input.

  Here, the write control signal 183 can be generated based on both the wait signal 32 and the write enable signal 81 that permits writing to each lip flop. For example, an AND circuit 182 for inputting the inverted signal of the wait signal 32 and the write enable signal 81 may be provided, and the output 183 of the AND circuit 182 may be used as the D input of the latching lip flop.

  In this way, in the wait state, the clock input to the 8-bit Philip flop (188-1,... 188-8) is masked, so that the Philip flop (188-1,. It is possible to prevent new data from being written.

  FIG. 6 is a timing chart for explaining the operation of another example of a lip-flop circuit with a write protection function.

  The input clock 62 is a clock that is an output of the clock supply control circuit 50, and is a clock that is supplied to the bus master circuit and peripheral circuits via the same clock route buffer.

  The wait signal 32 is a signal output from the bus slave circuit, and becomes H level in the wait state.

  The clock request signal 42 is a signal output from the peripheral circuit, and becomes H level when the peripheral circuit requests supply of a clock.

  The write control signal 183 is a signal that becomes the D input of the latching lip flop of the clock mask circuit of the lip flop circuit with a write prevention function, and is generated based on the wait signal and a write enable signal that controls permission of writing to each lip flop. Here, the case where the write enable signal is in the write permission state will be described.

  The local gate clock 187 is a clock that becomes a clock input of a Philip flop circuit with a write prevention function.

  In FIG. 6, since the peripheral circuit is in the clock request state, the clock request signal is at the H level. In this case, even if the wait signal 32 changes from the non-wait state (L level) to the wait state (H level), the input clock is not masked and the input clock is supplied to the bus master circuit and the peripheral circuits.

  In another example, when the wait signal 32 changes from the non-wait state (L level) to the wait state (H level) (see 510), the write control signal changes from H level to L level (see 520). In response to this, the local gate clock 187 output is masked (see 420), and the Philip flop is in a write-inhibited state.

  Therefore, although the clock is supplied to the bus master circuit and not in a low power state, the bus master circuit is in a write-inhibited state, and malfunction in the wait state can be prevented.

  FIG. 7 is a functional block diagram for explaining another configuration of the integrated circuit device according to the present embodiment.

  The integrated circuit device 210 according to the second embodiment includes a first circuit 220 including a lip-flop circuit 280-1,... 280-n with a write protection function, and requests from the first circuit 220. A second circuit that performs a process on the first circuit and returns a response to the first circuit, a third circuit 240 that receives a clock via the same clock root buffer 260 as the first circuit 220, and the first circuit A clock supply control circuit 250 that controls supply of a clock supplied to the circuit 220 and the third circuit 240 via the same clock route buffer 260 is included.

  The first circuit 220 transmits an address 272 to the second circuit 230 to exchange data 274. Note that the first circuit 220 may be a CPU, for example, and the second circuit 230 may be, for example, an SRAM or SDRAM with a built-in IC.

  The second circuit 230 outputs a wait signal 232 when a response to the request from the first circuit 220 (for example, a data read or write request) cannot be returned within a predetermined period. The wait signal 232 may be configured to be at a first level (for example, H level) when in a wait state, and to be at a second level (for example, L level) when not in a wait state.

  The third circuit 240 is configured to output a clock request signal 242 for preventing a clock supply stop in a predetermined case. The clock request signal 242 becomes the first level (for example, H level) when the third circuit 240 needs to be supplied with a clock, and becomes the second level (for example, L level) when the clock supply is not necessary. It may be configured as follows.

Note that the third circuit 240 may be, for example, a communication module that performs communication at a determined communication speed. The clock supply control circuit 250 is based on the wait signal 232 and the clock request signal 242, and the first circuit 220 and the second circuit. Supply control of the clock supplied to 240 is performed.

  The clock supply control circuit 250 is configured to perform control to stop the clock supply when the wait signal 232 is in the wait state and the clock request signal 242 does not indicate prevention of clock supply stop. Even when the wait signal is in the wait state, the clock supply is not stopped if the clock request signal indicates prevention of clock supply stop.

  When the wait signal is in a non-wait state, a clock is supplied.

  The clock supply control circuit 250 can include, for example, a first AND circuit 252, a latching lip flop 256, and a second AND circuit 258. The first AND circuit 252 inputs an inverted signal of the clock request signal 242 and the wait signal 232 and takes an AND, and outputs the inverted signal as a clock enable signal 254. The latching lip flop 256 may be a D lip flop having the clock enable signal as the D input and the oscillation clock 110 as the clock input. The second AND circuit 258 is an AND circuit that receives the output of the latching lip flop and the transmission clock 110, and the output is input to the clock route buffer 260.

  By doing so, it is possible to measure power saving by stopping the supply of the clock only when the supply of the clock to the peripheral circuit may be stopped in the wait state.

  The lip-flop circuits 280-1,..., 280-n with a write prevention function are configured to prevent new data from being written to the lip-flop based on the wait signal 232. Here, the Philip flop may be a Philip flop having a synchronous input (D Philip flop, T Philip flop, RS Philip flop, JK Philip flop, etc.).

  All the Philip Flock circuits included in the bus master circuit may be configured as Philip flop circuits with a write protection function.

  The lip-flop circuits 280-1,..., 280-n with write prevention function are configured to prevent new data from being written to the lip-flop when the wait signal 232 is in the wait state. Also good. In this way, when the clock is supplied in the wait state (when the third circuit 240 outputs the clock request signal 242 for preventing the clock supply stop), a new write to the Philip flop is performed. Therefore, the malfunction of the first circuit 220 can be prevented.

  In the wait state, when the clock request signal 242 is not output, the supply of the clock to the first circuit 220 is stopped, so that the flip-flop circuits 280-1,. No clock is supplied to -n and no new data is written to the Philip flop.

  According to the present embodiment, it is only necessary to provide one clock route buffer 260 for the first circuit 220 and the third circuit 240. When the bus is waited, the clock of the entire bus master is stopped and the wait is performed. It is possible to provide an integrated circuit device having both a function to wait and a function to wait without stopping the clock.

  In addition, the integrated circuit device 10 includes various types such as BCU (Bus Control Unit), MMU (Memory Management Unit), DMAC (Direct Access Memory Controller), LCD (Liquid Crystal Display) driver or SIO (Serial Input Output). Peripheral circuitry can be included.

2. Microcomputer FIG. 8 is an example of a hardware block diagram of the microcomputer of this embodiment.

  The microcomputer 700 includes a CPU 510, a cache memory 520, an LCD controller 530, a reset circuit 540, a programmable timer 550, a real time clock (RTC) 560, a DRAM controller / bus I / F 570, an interrupt controller 580, a serial interface 590, and a bus controller 600. A / D converter 610, D / A converter 620, input port 630, output port 640, I / O port 650, clock generator 560, prescaler 570 and general-purpose bus 680 connecting them, dedicated bus 730, etc. A clock supply control circuit 740, various pins 690, and the like are included.

  The clock supply control circuit 740 has the configuration described with reference to FIGS.

  The CPU 510 functions as a bus master circuit, and the Philip flop having a synchronization input included in the CPU has a configuration of a Philip flop circuit with a write control function as described in FIG. 3 or FIG.

  The RAM 720 and the ROM 710 may function as a bus slave circuit, and the clock supply control circuit 740 and the Philip flop circuit with a write control function of the CPU 510 may be operated based on a wait signal output from the RAM 720 or the ROM 710.

  The serial interface RAM 7 may function as a bus slave circuit and supply a clock via the same machine lock route buffer as the CPU 510.

3. Electronic Device FIG. 9 shows an example of a block diagram of the electronic device of this embodiment. The electronic apparatus 800 includes a microcomputer (or ASIC) 810, an input unit 820, a memory 830, a power generation unit 840, an LCD 850, and a sound output unit 860.

  Here, the input unit 820 is for inputting various data. The microcomputer 810 performs various processes based on the data input by the input unit 820. The memory 830 serves as a work area for the microcomputer 810 and the like. The power generation unit 840 is for generating various power sources used in the electronic device 800. The LCD 850 is for outputting various images (characters, icons, graphics, etc.) displayed by the electronic device.

  The sound output unit 860 is for outputting various sounds (sound, game sound, etc.) output from the electronic device 800, and the function can be realized by hardware such as a speaker.

  FIG. 10A illustrates an example of an external view of a cellular phone 950 that is one of electronic devices. The cellular phone 950 includes a dial button 952 that functions as an input unit, an LCD 954 that displays a telephone number, a name, an icon, and the like, and a speaker 956 that functions as a sound output unit and outputs sound.

  FIG. 10B illustrates an example of an external view of a portable game device 960 that is one of electronic devices. The portable game device 960 includes an operation button 962 that functions as an input unit, a cross key 964, an LCD 966 that displays a game image, and a speaker 968 that functions as a sound output unit and outputs game sound.

  FIG. 10C illustrates an example of an external view of a personal computer 970 that is one of electronic devices. The personal computer 970 includes a keyboard 972 that functions as an input unit, an LCD 974 that displays characters, numbers, graphics, and the like, and a sound output unit 976.

  By incorporating the microcomputer of this embodiment into the electronic devices in FIGS. 10A to 10C, an electronic device with low power consumption and high cost performance can be provided.

  As electronic devices that can use this embodiment, in addition to those shown in FIGS. 10A, 10B, and 10C, portable information terminals, pagers, electronic desk calculators, devices equipped with touch panels, Various electronic devices using an LCD such as a projector, a word processor, a viewfinder type or a monitor direct view type video tape recorder, and a car navigation device can be considered.

  In addition, this invention is not limited to this embodiment, A various deformation | transformation implementation is possible within the range of the summary of this invention.

1 is a functional block diagram of an integrated circuit device according to an embodiment of the present invention. The figure which showed about the control content of the state of a wait signal and a clock request signal, a clock supply control circuit, and a lip-flop circuit with a write-protection function. An example of a configuration of a Philip flop circuit with a write prevention function. 4A is a timing chart when the peripheral circuit is in a clock non-request state, and FIG. 4B is a timing chart when the peripheral circuit is in a clock request state. Another example of the configuration of a Philip flop circuit with a write prevention function. The timing chart for demonstrating operation | movement of the Philip flop circuit with a write-inhibiting function of the other example. FIG. 10 is a functional block diagram for explaining another structure of the integrated circuit device of this embodiment. The hardware block diagram of the microcomputer of this Embodiment. An example of a block diagram of an electronic device including a microcomputer is shown. 10A, 10B, and 10C are examples of external views of various electronic devices.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Integrated circuit device, 20 Bus master circuit, 30 Bus slave circuit, 32 Wait signal, 40 Peripheral circuit, 42 Clock request signal, 50 Clock supply control circuit, 60 Clock route buffer, 70 Bus, 80 Philip flop circuit with write control function, 510 CPU, 530 LCD controller, 540 reset circuit, 550 programmable timer, 560 real-time clock (RTC), 570 DRAM controller / bus I / F, 580 interrupt controller, 590 serial interface, 600 bus controller, 610 A / D converter, 620 D / A converter, 630 input port, 640 output port, 650 I / O port, 660 clock generator (PLL), 670 prescaler, 680 General-purpose bus, 690 pins, 700 microcomputer, 710 ROM, 720 RAM, 730 MMU, 740 clock supply control circuit, 800 electronic device, 850 LCD

Claims (10)

An integrated circuit device comprising:
A bus master circuit including a Philip flop circuit with a write protection function;
A bus slave circuit that processes a request from the bus master circuit and returns a response to the bus master;
A peripheral circuit that receives clock supply via the same clock route buffer as the bus master circuit;
A clock supply control circuit that performs supply control of a clock supplied to the bus master circuit and the peripheral circuit via the same clock route buffer,
The bus slave circuit is
When a response cannot be returned within a predetermined period to the request from the bus master circuit, a wait signal is output,
The peripheral circuit is
It is configured to output a clock request signal for preventing a clock supply stop in a predetermined case,
The clock supply control circuit includes:
Based on the wait signal and the clock request signal, supply control of the clock supplied to the bus master circuit and the peripheral circuit is performed.
The write-proof Philip flop circuit is
An integrated circuit device configured to prevent new data from being written to a Philip flop based on a wait signal. An integrated circuit device comprising:
A first circuit comprising a Philip flop circuit with a write protection function;
A second circuit that processes a request from the first circuit and returns a response to the first circuit;
A third circuit that receives a clock through the same clock root buffer as the first circuit;
A clock supply control circuit that performs supply control of a clock supplied to the first circuit and the third circuit via the same clock route buffer;
The second circuit includes:
When a response cannot be returned within a predetermined period to the request from the first circuit, a wait signal is output,
The third circuit includes:
It is configured to output a clock request signal for preventing a clock supply stop in a predetermined case,
The clock supply control circuit includes:
Based on the wait signal and the clock request signal, supply control of the clock supplied to the first circuit and the third circuit is performed.
The write-proof Philip flop circuit is
An integrated circuit device configured to prevent new data from being written to a Philip flop based on a wait signal. In any one of Claims 1 thru | or 2.
The Philip flop circuit with the lower write prevention function is
An integrated circuit device configured to prevent new data from being written to the Philip flop by rewriting the data of the Philip flop on the Philip flop based on the wait signal. In any one of Claims 1 thru | or 2.
The write-proof Philip flop circuit is
An integrated circuit device configured to prevent new data from being written to a Philip flop by masking a clock supplied to the Philip flop based on a wait signal. In any one of claims 3 to 4 dependent on claim 1 or claim 1,
The integrated circuit device, wherein the bus master circuit is a CPU. In any one of claims 3 to 5 dependent on claim 1 or claim 1,
The integrated circuit device, wherein the peripheral circuit is a communication module that performs communication at a determined communication speed. In any one of claims 3 to 4 dependent on claim 2 or claim 2,
The integrated circuit device, wherein the first circuit is a CPU. In any one of claims 3 to 4, 7 depending on claim 2 or claim 2,
The integrated circuit device, wherein the third circuit is a communication module that performs communication at a determined communication speed.   A microcomputer comprising the integrated circuit device according to claim 1. A microcomputer according to claim 9;
Means for receiving input information;
Means for outputting a result processed by the information processing device based on input information;
An electronic device comprising:

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