JP4645843B2 - Data processing apparatus, data processing method and program - Google Patents

Description

  The present invention relates to a data processing apparatus for generating physical design data based on logical design data of an integrated circuit, a data processing method, and a program for causing a computer to execute the method.

  The integrated circuit includes a clock generation device (hereinafter referred to as a driver) that generates a clock signal that serves as a reference for the timing of circuit operation, and a plurality of elements (hereinafter referred to as receivers) that receive the clock signal. One or more drivers are provided. The driver and receiver are connected by a network called a clock distribution network. Cells such as buffers and inverters are provided at the connection between the clock distribution network and the receiver.

  A transmission delay until the clock signal transmitted from the driver serving as the clock source reaches the final stage buffer or the output terminal of the inverter is defined as a clock delay. When the wiring length from the driver to each receiver is the same, when the driver transmits a clock signal to a plurality of receivers via the clock distribution network, the timing at which each receiver receives the clock signal is the same. In this way, if the clock distribution network is ideally formed, the clock delays of the respective receivers match. On the other hand, when the wiring length from the driver to each receiver is different due to manufacturing variations, the clock delays of each receiver do not match. The difference between the clock delay when the manufacturing variation is not considered and the clock delay when the manufacturing variation is considered is defined as a clock transmission delay error (clock skew).

  If there is a clock skew in the clock distribution network, the upper limit of the operating frequency of the circuit must be lowered in consideration of the error in order to operate the circuit normally. In order to increase the upper limit of the operating frequency, a clock distribution network with a small clock skew is desirable. As a countermeasure, Patent Document 1 discloses a clock distribution structure having a symmetric structure such as an H-Tree structure. The clock distribution structure is the basis of the clock distribution network.

However, in recent integrated circuits that are becoming finer, even if the clock distribution structure is symmetric, clock skew is a problem due to variations in manufacturing. To solve this problem, a mesh structure, a spine structure, and a clock distribution structure combining a plurality of structures have been proposed. Although it cannot be avoided that variations occur during manufacturing, the clock skew generated due to manufacturing variations becomes smaller by using these structures.
Japanese Patent Laid-Open No. 11-317457 (page 8, FIG. 2)

  In general, the amount of wiring increases and the power consumption increases as the clock distribution structure has a smaller influence of manufacturing variations on clock skew. Conversely, as the amount of wiring decreases, the power consumption decreases, but the effect of clock skew increases. Therefore, there is a problem that a clock distribution structure suitable for a specific integrated circuit cannot be easily obtained from the relationship between the two. In addition, a method of estimating all the clock distribution structures and estimating the clock skew can be considered, but this involves a problem that it takes a large number of man-hours and calculation time.

  The present invention has been made to solve the above-described problems of the prior art, and presents information that allows the user to select an optimum structure from among a plurality of types of clock distribution structures. An object is to provide a data processing apparatus, a data processing method, and a program for causing a computer to execute the method.

In order to achieve the above object, a data processing apparatus of the present invention comprises:
A storage unit storing a plurality of types of information of a clock distribution structure, which is a basic structure of a wiring network for distributing a clock signal;
An output unit for outputting clock skew and power consumption information of a plurality of candidate clock distribution networks for integrated circuit data including information on the number of receivers that receive the clock signal;
Virtual clock network generation means for generating a plurality of virtual clock distribution networks for the integrated circuit data using a plurality of types of clock distribution structures stored in the storage unit when the integrated circuit data is input. Optimizing means for determining a parameter for minimizing clock skew for the clock distribution structure that is different for each clock distribution network, and analysis means for determining the clock skew and power consumption for each clock distribution network for which the parameter is determined A data processing unit including:
It is the structure which has.

On the other hand, a data processing method of the present invention for achieving the above object includes a storage unit for storing a plurality of types of clock distribution structures, which is a basic structure of a wiring network for distributing clock signals, and a clock signal in an integrated circuit. A data processing method by an information processing apparatus comprising a data processing unit for obtaining a clock distribution network for distribution to
When integrated circuit data including information on the number of receivers that receive the clock signal is input to the data processing unit, a virtual distribution for the integrated circuit data is performed using a plurality of types of clock distribution structures stored in the storage unit. Create multiple clock distribution networks,
The data processing unit determines a parameter that minimizes clock skew for the clock distribution structure that is different for each generated clock distribution network;
The data processing unit obtains clock skew and power consumption for each clock distribution network for which parameters are determined.

In addition, a program of the present invention for achieving the above object includes a storage unit for storing a plurality of types of clock distribution structures, which is a basic structure of a wiring network for distributing clock signals, and distributing clock signals in an integrated circuit. A program for causing a data processing unit of a computer provided with a data processing unit to obtain a clock distribution network to
When integrated circuit data including information on the number of receivers that receive the clock signal is input, a plurality of virtual clock distribution networks for the integrated circuit data are generated using a plurality of types of clock distribution structures stored in the storage unit. Generating step;
Determining a parameter that minimizes clock skew for the clock distribution structure that is different for each generated clock distribution network;
Determining clock skew and power consumption for each clock distribution network for which parameters have been determined;
The data processing unit of the computer is caused to execute a process including:

  According to the present invention, a plurality of candidate clock distribution networks and the analysis results of clock skew and power consumption of each clock distribution network are presented to the user, so that the user can select a clock suitable for the integrated circuit to be developed. The distribution network can be selected in a shorter time.

(First embodiment)
The configuration of the data processing apparatus of this embodiment will be described.

  FIG. 1 is a block diagram illustrating a configuration example of the data processing apparatus according to the present embodiment. As shown in FIG. 1, the data processing apparatus is an information processing apparatus having an input unit 1, a data processing unit 2, a storage unit 5, and an output unit 3. The data processing unit 2 includes a virtual clock network generation unit 21, an optimization unit 22, and an analysis unit 23.

  The input unit 1 includes a communication unit that transmits and receives data to and from an external device via a communication line, in addition to operation devices such as a keyboard and a mouse. When the integrated circuit data is input, the integrated circuit data is transferred to the data processing unit 2. The integrated circuit data includes at least receiver information. Receiver information is information including the number of receivers. The integrated circuit data of this embodiment includes information on the arrangement of each receiver, and the arrangement position (arrangement coordinates) of each receiver on the chip is determined.

  The storage unit 5 stores a plurality of types of information on a clock distribution structure, which is a basic structure of a wiring network for distributing clock signals. The H-Tree structure disclosed in Patent Document 1 is a kind of clock distribution structure. Further, the storage unit 5 stores the processing results of each means.

  The virtual clock network generation unit 21 applies various clock distribution structures stored in the storage unit 5 to the integrated circuit data received from the input unit 1 to generate a plurality of virtual clock distribution networks. Here, since the clock distribution network is generated ignoring physical design constraints, the generated clock distribution network is a virtual one that cannot be implemented as it is. However, even if it is virtual, since the distribution network model corresponding to the integrated circuit data is generated based on the existing clock distribution structure, the data can be executed to the extent that the optimization means and analysis means described later can be executed. Exists on.

  The optimization means 22 optimizes the parameters existing for each underlying clock distribution structure for the virtual clock distribution network. The purpose of this optimization is to minimize the occurrence of clock skew due to manufacturing variations from the driver to the receiver.

  The analysis means 23 analyzes the delay of the virtual clock distribution network. A static delay analysis function and a probabilistic static delay analysis function are provided, and a clock delay and a clock skew when the manufacturing variation is not taken into consideration and a clock skew when the manufacturing variation is taken into consideration are obtained. Further, the power consumption is obtained by calculation. In this way, information necessary for the user to determine the optimum clock distribution structure is obtained by analysis. In this embodiment, the clock skew analysis is performed both when the manufacturing variation is taken into consideration and when it is not taken into consideration.

  The data processing unit 2 includes a CPU (Central Processing Unit) that executes predetermined processing according to a program and a memory for storing the program. The virtual clock network generation unit 21, the optimization unit 22, and the analysis unit 23 are virtually configured in the data processing device when the CPU executes a program.

  The output unit 3 is a display device that outputs the analysis result obtained by the analysis unit 23 in a form visible to the user. It has a GUI (Graphical User Interface) function and displays a clock distribution network and a clock skew distribution on the screen. The power consumption information is displayed in text format. If the output unit 3 is a printer device, these results can be printed on paper.

  Next, the operation of the data processing apparatus of this embodiment will be described. FIG. 2 is a block diagram showing a configuration example of the data processing apparatus and a data flow, and FIG. 3 is a flowchart showing an operation procedure of the data processing unit.

  Integrated circuit data whose arrangement positions on all the receiver chips have been determined is prepared. When the integrated circuit data 41 prepared in advance by the user is input from the external device 4 to the data processing unit 2 via the input unit 1, the input unit 1 passes the integrated circuit data 41 to the data processing unit 2.

  When the virtual clock network generation unit 21 of the data processing unit 2 receives the integrated circuit data 41, the virtual clock network generation unit 21 reads the information of the plurality of clock distribution structures 51 stored in the storage unit 5. Each of the plurality of clock distribution structures 51 is applied to the integrated circuit data 41 to generate a plurality of clock distribution networks 52 that can be mounted on the chip plane (step 101). Subsequently, the information of the clock distribution network 52 is stored in the storage unit 5. The types of the clock distribution structure 51 include various structures such as an H-Tree structure, a Mesh structure, a Spine structure, and a combination of these. The virtual clock network generation unit 21 generates a wiring by arranging a clock source at the center of the chip as in the H-Tree structure shown in FIG. At this time, generation of wiring is performed ignoring realistic physical design constraints. That is, it may overlap with the existing power supply wiring, and even if a position where wiring is possible is determined, it is not considered. In this way, a virtual clock distribution network is generated at high speed.

  Subsequently, the optimization unit 22 reads the plurality of clock distribution networks 52 from the storage unit 5, and optimizes parameters for each data (step 102). Then, the optimized clock distribution network 53 is stored in the storage unit 5. There are two types of parameters. One is common regardless of the type of the clock distribution structure, such as the type of wiring layer to be used, the wiring width, the insertion position of the buffer and the inverter. The other is dependent on the type of clock distribution structure such as the number of stages of the H-Tree structure and the number of lattices of the Mesh structure. The optimization means 22 optimizes these parameters for the purpose of minimizing the clock skew considering the manufacturing variation. When calculating the clock delay, it is assumed that the buffer or inverter at the final stage is wired linearly from the receiver, and circuit constants such as capacitors and registers are determined.

  Subsequently, the analysis unit 23 reads the optimized clock distribution network 53 from the storage unit 5 and analyzes the power consumption for each of these data. The static delay analysis function analyzes the clock delay and clock skew when manufacturing variations are not included. Further, the clock skew when manufacturing variation is included is analyzed by the stochastic static delay analysis function (step 103). All these analysis results 54 are stored in the storage unit 5. The analysis result 54 includes clock skew distribution data and power consumption information corresponding to the clock distribution network.

  The output unit 3 presents the analysis result 54 to the user through the GUI according to the control signal from the data processing unit 2. As a result, the user can confirm the clock distribution network and the clock skew distribution on the GUI. Items that do not require a GUI, such as power consumption, can be confirmed in text.

In the present embodiment, as described above, a plurality of candidate clock distribution networks and analysis results of clock skew and power consumption of each clock distribution network are presented to the user. The user can determine a clock distribution network that seems to be the best from a plurality of candidate clock distribution networks in consideration of a trade-off between clock skew and power consumption. A clock distribution network suitable for the integrated circuit to be developed can be selected in a shorter time.
(Second Embodiment)
This embodiment is a case where the information of the position of the receiver in the integrated circuit data 41 is not completely determined. In the following, detailed description of the same configuration as that of the first embodiment will be omitted, and only differences from the first embodiment will be described in detail.

  The integrated circuit data does not include information about the arrangement coordinates of the receiver, but includes information of two types related to the arrangement of the receiver. The first form is a description of the position where the receiver can be arranged. Specifically, it can be defined by a DEF format GROUP, which is a kind of file format, but other formats may be used. The second form is a description of the total input terminal capacitance value of the receiver existing in each part surrounded by a grid by dividing the chip plane into a grid pattern in advance. Information including the first form and the second form related to the arrangement of the receiver is referred to as arrangement-related information. When integrated circuit data including arrangement related information is input via the input unit 1, the data processing unit 2 obtains the arrangement coordinates of the receiver based on the arrangement related information, and is the same integrated circuit as in the first embodiment. Generate data.

Next, the effect of this embodiment will be described. When modifying the design contents of an integrated circuit developed in the past in order to reduce the size and power consumption, information on the approximate arrangement position of the receiver of the integrated circuit may remain in the storage unit 5 in some cases. In this case, it is not necessary for the user to determine the arrangement position of the receiver, and it is sufficient to write at least the arrangement-related information in the integrated circuit data with reference to the receiver arrangement coordinates of the integrated circuit stored in the storage unit 5. . In this way, when the information of the integrated circuit developed in the past can be used, the clock distribution network can be generated prior to the determination of the arrangement position of the circuit element using the information. For this reason, it is necessary to determine the arrangement position of the circuit element, select the clock distribution network, generate the clock distribution network, and adjust the arrangement position of the circuit element. The development period can be shortened by changing the setup to determine the location.
(Third embodiment)
In the first embodiment, the optimization means operates depending on the clock distribution structure to which the integrated circuit data is applied. This embodiment is different from the first embodiment in that the optimization means operates without depending on the clock distribution structure. In the following, detailed description of the same configuration as that of the first embodiment will be omitted, and only differences from the first embodiment will be described in detail.

  Generally, a non-tree type clock distribution structure including a closed circuit has a symmetric shape, and therefore there is a wiring through which no current flows unless there is a manufacturing variation. If there are irregular parts, the calculation load for determining parameters such as the wiring width and buffer insertion position increases. On the other hand, the tree-type clock distribution structure can determine parameters such as the wiring width and buffer insertion position by a common method and is easy to optimize. This common method is called an optimization algorithm. Utilizing the above, the optimization unit of the present embodiment performs the following operation.

  The optimizing means deletes the wiring through which no current flows when there is no manufacturing variation for the non-tree type clock distribution structure. As a result, a tree-type clock distribution structure is obtained. Subsequently, parameters are determined by an optimization algorithm for the tree-type clock distribution structure. Thereafter, the deleted wiring is restored. In this way, optimization processing can be performed for any clock distribution structure.

Next, the effect of this embodiment will be described. Even if the user has come up with a new clock distribution structure, it is not always easy to come up with an optimization method for the clock distribution structure. However, according to the present embodiment, any clock structure can be quickly optimized as described above.
(Fourth embodiment)
This embodiment is different from the first embodiment in that the output unit outputs the optimization result by the optimization means in a simulator format such as SPICE. In the following, detailed description of the same configuration as that of the first embodiment will be omitted, and only differences from the first embodiment will be described in detail.

  FIG. 4 is a block diagram showing a configuration example of the data processing apparatus of this embodiment and a data flow. The external device 4 includes a SPICE simulator 43. As in the first embodiment, an optimized clock distribution network 42 is generated for the integrated circuit data 41 input from the input unit 1 via the virtual clock network generation means 21 and the optimization means 22. The The optimization means 22 converts the information of the optimized clock distribution network 42 into a format suitable for the SPICE circuit simulation grammar. Then, as shown in FIG. 4, the information of the optimized clock distribution network 42 is sent to the external device 4 via the output unit 3. The external device 4 performs SPICE simulation using the information of the optimized clock distribution network 42 received from the data processing device, and outputs the clock skew distribution and power consumption information of the candidate clock distribution network. To do.

  In the present embodiment, the external device 4 has a circuit simulation function. However, the analysis unit of the data processing device may have a circuit simulation function.

  Next, the effect of this embodiment will be described. The analysis unit 23 of the first embodiment performs a delay analysis by a technique called static delay analysis. In this embodiment, the analysis after optimization is performed by a simulator 43 such as SPICE. The simulator 43 is generally slower in execution speed than static delay analysis, but has high analysis accuracy. Therefore, when the analysis accuracy is further increased, the analysis can be performed using a simulator.

In this embodiment, SPICE is applied as the grammar of the circuit simulator, but other grammars may be used.
(Fifth embodiment)
This embodiment is different from the first embodiment in that when one of a plurality of candidate clock distribution networks is selected, a clock distribution network that complies with physical design constraints is generated based on the selection. In the following, detailed description of the same configuration as that of the first embodiment will be omitted, and only differences from the first embodiment will be described in detail.

  FIG. 5 is a block diagram showing a configuration example of the data processing apparatus of this embodiment and a data flow.

  In the present embodiment, an actual clock network generation unit 24 is provided in the data processing unit 2. Further, the output unit 3 is provided with an information output unit 31 and a data output unit 32.

  The information output means 31 has a function similar to that of the output unit 3 in the first embodiment. The user can select an optimal clock distribution network by looking at the analysis result presented by the information output means 31.

  When the user's selection 42 instruction is input from the external device 4, the real clock network generation unit 24 physically designs cells such as drivers, buffers, and inverters on the clock distribution network for the selected clock distribution network. Arrange them according to the restrictions. Since these cells are more important than other cells, other cells are moved when they overlap with other cells. An important cell is a cell placed at the end of a clock signal source or wiring. In addition, wiring is generated in accordance with physical design constraints. Hereinafter, the clock distribution network generated by the actual clock network generation unit 24 is referred to as an actual clock distribution network. The real clock network generation means 24 is virtually configured in the data processing apparatus when the CPU executes a program. Further, in FIG. 5, for the purpose of explanation, a signal for user selection 42 is input from the external device 4 to the output unit 3, but is input via the input unit 1.

  The data output means 32 outputs the real clock distribution network 43 generated by the real clock network generation means 24 based on a general integrated circuit data format.

  In the present embodiment, the real clock distribution network 43 is generated by the real clock network generation means 24, and it is possible to quickly move to the subsequent physical design stage.

  A plurality of embodiments may be combined from the second to fifth embodiments and applied to the first embodiment. Further, the present invention can be applied to the design of an integrated circuit in which the clock distribution network is not embedded in advance. Furthermore, you may apply to the program for making a computer perform the data processing method of this invention.

It is a block diagram which shows the example of 1 structure of the data processor in 1st Embodiment. It is a block diagram which shows the structural example of the data processor of 1st Embodiment, and the flow of data. It is a flowchart which shows the operation | movement procedure of the data processing part of 1st Embodiment. It is a block diagram which shows the structural example of the data processing apparatus of 4th Embodiment, and the flow of data. It is a block diagram which shows the structural example of the data processor of 5th Embodiment, and the flow of data.

Explanation of symbols

2 Data processing unit 21 Virtual clock network generation unit 22 Optimization unit 23 Analysis unit 3 Output unit

Claims (11)

A storage unit storing a plurality of types of information of a clock distribution structure, which is a basic structure of a wiring network for distributing a clock signal;
An output unit for outputting clock skew and power consumption information of a plurality of candidate clock distribution networks for integrated circuit data including information on the number of receivers that receive the clock signal;
Virtual clock network generation means for generating a plurality of virtual clock distribution networks for the integrated circuit data using a plurality of types of clock distribution structures stored in the storage unit when the integrated circuit data is input. Optimizing means for determining a parameter for minimizing clock skew for the clock distribution structure that is different for each clock distribution network, and analysis means for determining the clock skew and power consumption for each clock distribution network for which the parameter is determined A data processing unit including:
A data processing apparatus.   The data processing apparatus according to claim 1, wherein the integrated circuit data includes information on arrangement coordinates on the chip of the receiver. The integrated circuit data includes arrangement-related information including information on a position where the receiver can be arranged, and information on a total value of the input terminal capacity of the receiver that exists for each part surrounded by a lattice in which the chip plane is divided by a lattice. Have
The data processing unit obtains the arrangement coordinates of the receiver based on the arrangement-related information when the integrated circuit data does not contain arrangement coordinate information on the receiver, and includes the arrangement coordinate information. The data processing apparatus according to claim 1, wherein data is transferred to the virtual clock network generation unit. The virtual clock network generation means includes
4. The data processing apparatus according to claim 1, wherein the clock distribution network in which the clock distribution structure is arranged on a chip plane is generated for each clock distribution structure ignoring physical design constraints. 5.   5. The parameter according to claim 1, wherein the parameter includes a type and insertion position of a cell provided at a connection portion between the clock distribution network and the receiver, and a wiring width and a wiring layer type of the clock distribution network. The data processing apparatus described. The analysis means includes
The data processing apparatus according to claim 1, wherein at least a case where manufacturing variation is not considered or a case where manufacturing variation is considered is calculated as the clock skew. The optimization means includes
For a non-tree type clock distribution structure, a part of wiring is deleted to form a tree type structure, and a predetermined optimization algorithm is applied to the tree type structure to determine the parameters, and then deleted. The data processing device according to claim 1, wherein the wiring is restored. The analyzing means has a circuit simulation function;
The optimization means includes
8. The data processing apparatus according to claim 1, wherein the clock distribution network with the parameters determined is sent to the analysis means in a format suitable for the grammar of the circuit simulation.   When a selection instruction for determining the clock distribution network is input, an actual clock network generation unit that performs cell placement and wiring generation related to the selected clock distribution network in compliance with physical design constraints is the data processing. The data processing apparatus according to claim 1, which is provided in the section. A storage unit for storing a plurality of types of clock distribution structures, which is a basic structure of a wiring network for distributing clock signals, and a data processing unit for obtaining a clock distribution network for distributing clock signals in an integrated circuit are provided. A data processing method by an information processing apparatus,
When integrated circuit data including information on the number of receivers that receive the clock signal is input to the data processing unit, a virtual distribution for the integrated circuit data is performed using a plurality of types of clock distribution structures stored in the storage unit. Create multiple clock distribution networks,
The data processing unit determines a parameter that minimizes clock skew for the clock distribution structure that is different for each generated clock distribution network;
A data processing method, wherein the data processing unit obtains a clock skew and power consumption for each clock distribution network for which parameters are determined. A storage unit for storing a plurality of types of clock distribution structures, which is a basic structure of a wiring network for distributing clock signals, and a data processing unit for obtaining a clock distribution network for distributing clock signals in an integrated circuit are provided. A program for causing the data processing unit of a computer to execute the program,
When integrated circuit data including information on the number of receivers that receive the clock signal is input, a plurality of virtual clock distribution networks for the integrated circuit data are generated using a plurality of types of clock distribution structures stored in the storage unit. Generating step;
Determining a parameter that minimizes clock skew for the clock distribution structure that is different for each generated clock distribution network;
Determining clock skew and power consumption for each clock distribution network for which parameters have been determined;
A program for causing the data processing unit of the computer to execute a process including:

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