JP4647484B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a technical field of a semiconductor device having a metal wiring structure in which a slit is formed.

  In recent years, with the high integration and miniaturization of semiconductor devices, trenches are formed in dielectrics in which a silicon oxide film or a part of the silicon oxide film is replaced with a chemical group containing fluorine, hydrogen, or carbon. A wiring structure formed by a so-called damascene method in which a metal wiring is formed by embedding a metal by phase growth or plating and then removing excess metal by a method such as chemical mechanical polishing has been put into practical use. By the metal wiring formation method using the damascene method, it becomes possible to form a wiring structure of a semiconductor integrated circuit mainly composed of copper or copper, and this technique can reduce wiring resistance and improve electromigration resistance. It is like that.

  However, the wiring formation method by the damascene method includes a flattening process in the formation process, so that when the wiring width to be formed is more than about several micrometers, it is inevitably generally referred to as “dishing”. The phenomenon called will occur. This dishing becomes particularly noticeable as the wiring width increases.

  Usually, in the metal wiring flattening process in the damascene wiring forming process, by optimizing the rotational speed and pressure of the abrasive and polishing pad, the selection ratio at the time of polishing is made so that the metal is more easily scraped than the insulating film. It is adjusted. That is, in the planarization step, the insulator other than the metal that serves as the wiring functions as a stopper for planarization.

  However, when the width of the metal wiring is wide as described above, there is a wide area where there is no insulating film functioning as a stopper, and the entire area of the metal wiring is flattened so that the metal wiring is desired. As a result, the wiring height becomes thinner than a desired film thickness, resulting in a problem that the wiring resistance becomes higher than a desired value.

  In general, when a high-frequency current flows through adjacent metal wires, a non-uniform current density distribution is generated inside each metal wire. This is a phenomenon explained by electromagnetics, and is generally referred to as a proximity effect. As a simple example, assuming that two adjacent metal wirings exist, it is assumed that an in-phase AC current flows through both metal wirings. When a current flows through these metal wirings, a magnetic field is generated around the metal wiring. When the flowing current is an alternating current, an alternating magnetic field is naturally generated. Since the magnetic lines of force due to this alternating magnetic field pass through the wirings adjacent to each other, an induced current is generated in both wirings in directions that prevent the magnetic flux. Therefore, the current is amplified when the current originally flowing in the metal wiring is in the same direction as the induced current, and the current is decreased when the current originally flowing in the metal wiring is in the opposite direction to the induced current.

  Therefore, when currents in phase with each other flow in adjacent wirings, the currents concentrate on the outside. This is the proximity effect. In particular, in a frequency band higher than the gigahertz band, the influence of the resistance increase due to the proximity effect becomes large, and the effective resistance of the metal wiring is increased.

  In order to solve these problems, there is an invention described in Patent Document 1, for example. This invention discloses a technique for suppressing dishing by forming a slit in a wide wiring and suppressing an increase in wiring resistance. By using the method described in Patent Document 1, it is possible to suppress a decrease in the wiring film thickness due to dishing during the planarization of the metal wiring, and thus to suppress an increase in resistance of the wide wiring.

  Further, in the invention described in Patent Document 2, the spiral inductor wiring formed by the wide wiring is connected in parallel with a plurality of wirings, thereby blocking the path of the induced current excited inside the metal wiring. A technique for reducing the above and improving the performance of the inductor is disclosed.

  That is, when the invention described in Patent Document 2 is partially shown, it is as shown in FIGS. As shown in FIGS. 19 and 20, slits 3 and 4 are formed in the metal wirings 1 and 2 in parallel with the extending direction. These slits 3 and 4 are formed symmetrically with respect to the extending direction of the metal wirings 1 and 2 when viewed from the upper surface of the metal wirings 1 and 2, so that the respective center dividing lines 5 and 6 are formed in the slit 3. , 4 in the center in the width direction. And by forming the slits 3 and 4, the metal wiring is divided into parts 1a and 1b and metal wiring parts 12a and 12b.

  Furthermore, in the invention described in Patent Document 3, the upper portion of the spiral inductor wiring formed by the wide wiring is connected in parallel with a plurality of wirings, thereby increasing the surface area of the metal wiring and improving the Q value of the inductor. Technology is disclosed.

The invention described in Patent Document 4 includes a technique for reducing loss by reducing the series resistance of a part where current concentration occurs by making the current concentration part of the inductor wiring parallel connection of a plurality of level wirings. It is disclosed.
Japanese Patent No. 3481812 JP-A-11-261008 JP 2003-209183 A JP 2004-214377 A

  However, in the invention described in Patent Document 1, although the effect of ensuring the flattening of the wiring material can be obtained by forming the slit, the current flows unevenly inside the formed wiring. If the slits are evenly laid out in the metal wiring, it is effective during operation in the high-frequency band where the influence of the proximity effect becomes large due to the presence of the slits at locations where current concentrates due to circuit characteristics. There is a problem that the wiring resistance increases.

  By the way, in order to reduce the leakage magnetic flux to the outside, the metal wiring layout used in the semiconductor device is often laid out so that currents of opposite phases flow in a plurality of adjacent wirings. In this case, currents concentrate on the inner sides of the wirings adjacent to each other. Therefore, there is a problem that substantial wiring resistance increases when slits are formed in the inner portions of the adjacent wiring structures.

  Therefore, when the metal wiring and the slit are formed by the method described in Patent Document 1, the slit is also formed inside the adjacent metal wiring through which currents of opposite phases flow. There was a problem that the substantial resistance of the would increase.

  On the other hand, when an element such as an inductor is formed in a circuit configuration used in a semiconductor device, currents having the same phase flow through a plurality of adjacent wirings. In this case, current concentrates on the outside of the wirings adjacent to each other. Accordingly, if the slits are formed in the outer portions of the adjacent wiring structures, the substantial wiring resistance increases. Therefore, when the metal wiring and the slit are formed by the method described in Patent Document 1, the slit is also formed outside the adjacent metal wiring through which currents in the same phase flow. There was a problem that the substantial resistance increased.

  Further, in the invention described in Patent Document 2, for the spiral inductor on the semiconductor substrate, by providing slits 3 and 4 in the extending direction of the metal wirings 1 and 2 constituting the spiral inductor, the metal wiring 1 2 discloses a technique for improving the performance of a spiral inductor by blocking the path of an induced current excited in the coil 2.

  However, in the slit shape disclosed in the invention described in Patent Document 2, no particular attention is paid to the current concentration generated in the metal wirings 1 and 2, and the resistance increase due to the current concentration is not paid attention. No measures have been taken. Therefore, the method of the invention described in Patent Document 2 has a problem that a large performance improvement of the spiral inductor cannot be expected because the increase in resistance due to current concentration cannot be sufficiently suppressed.

  Furthermore, in the invention described in Patent Document 3, a spiral inductor on a semiconductor substrate is provided with a slit in the extending direction of the metal wiring only in the upper part of the metal wiring constituting the spiral inductor, thereby providing a skin effect. A technique for suppressing an effective increase in resistance is disclosed.

  However, in the slit shape disclosed in the invention described in Patent Document 3, as in the invention described in Patent Document 2, no particular attention has been paid to the current concentration generated in the metal wiring. No measures are taken against the resistance increase due to current concentration. Therefore, the method of the invention described in Patent Document 3 has a problem that a significant improvement in the performance of the spiral inductor cannot be expected because a rise in resistance due to current concentration cannot be sufficiently suppressed.

  In the invention described in Patent Document 4, for the spiral inductor on the semiconductor substrate, the metal that constitutes the spiral inductor on the inner side of the innermost wiring of the spiral turn where current concentration occurs and on the outer side of the outermost outer wiring, respectively. A technique is disclosed in which wiring resistance is reduced by using parallel connection wiring using a plurality of wiring level layers.

  However, when the metal wiring is formed by the method of the invention described in Patent Document 4, the use of multiple levels of wiring layers increases the parasitic capacitance between the lower level wiring and the substrate. There's a problem. In fact, referring to the experimental data disclosed in the invention described in Patent Document 4, by using the invention, the invention is applied rather than the Q value of the spiral inductor when a single wiring layer is used. It is shown that the Q value of the inductor improved, but the self-resonant frequency of the spiral inductor is lower than that of a known spiral inductor formed by a single wiring layer. This means that the parasitic capacitance of the spiral inductor formed according to the present invention is larger than that of a spiral inductor formed using a known single layer wiring, and this increase in parasitic capacitance is used. Depending on the application of the integrated circuit, this is not preferable.

  The present invention has been made in view of the above points, suppresses dishing in the manufacturing process, suppresses an undesirable decrease in the thickness of the metal wiring, and does not normally cause an increase in parasitic capacitance, It is an object of the present invention to provide a semiconductor device that suppresses an increase in effective metal wiring resistance due to the proximity effect, which is particularly noticeable at high frequencies in the gigahertz band.

  The present inventors have solved the above dishing problem with respect to the above problem that the wiring resistance increases when a slit as described in the background art is formed at a location where current concentration occurs due to the proximity effect described above. It has been found that an effective increase in resistance can be suppressed by devising the arrangement of slits formed for suppression.

  That is, in claim 1 of the present invention, a plurality of metal wirings are arranged adjacent to each other, and slits are formed in each of these metal wirings, and the slits in at least one or more metal wirings among the plurality of metal wirings Is formed asymmetrically with respect to the extending direction of the metal wiring as viewed from the top surface of the metal wiring.

  According to the present invention, the slits in the metal wiring are formed asymmetrically with respect to the extending direction of the metal wiring as viewed from the top surface of the metal wiring, thereby suppressing dishing and preventing a reduction in the wiring film thickness, and An increase in resistance of the metal wiring during high frequency operation can be suppressed. Thereby, low power consumption and low noise of the semiconductor device can be realized.

  Moreover, since the slits in the metal wiring are formed asymmetrically with respect to the extending direction of the metal wiring when viewed from the top surface of the metal wiring, it is possible to suppress an increase in resistance of the metal wiring, thereby reducing wiring delay. As a result, the speed of the semiconductor device can be increased.

  Furthermore, since the slits in the metal wiring are formed asymmetrically with respect to the extending direction of the metal wiring as viewed from the upper surface of the metal wiring, current concentration in the metal wiring can be reduced, so that A semiconductor device with improved migration resistance and high reliability can be realized.

  And, by forming the slits in the metal wiring asymmetrically with respect to the extending direction of the metal wiring when viewed from the top surface of the metal wiring, the rise in resistance of the metal wiring during high-frequency operation is suppressed, thereby improving the performance. A circuit constituting a signal processing device, for example, a circuit such as a voltage controlled oscillator or a low noise amplifier constituting a communication semiconductor device can be realized, and a low-loss, high-performance wireless communication semiconductor device can be realized. .

  Hereinafter, the best embodiment of the present invention will be described in detail with reference to the drawings. In addition, all the following structural drawings show each embodiment of this invention typically, and the dimension of the structure by this invention is not prescribed | regulated by the ratio on drawing of a component.

  In the following embodiments, when metal wirings adjacent to each other on a semiconductor device are formed of copper or an alloy containing copper as a main component, they are formed by a so-called damascene method. When wiring is formed of copper or an alloy containing copper as a main component formed by this damascene method, in many cases, in order to prevent diffusion of wiring material into the insulating film, the bottom and side walls of the metal wiring are formed. Although a layer generally referred to as a barrier metal is formed, which is formed of a refractory metal such as titanium or tantalum and the nitride thereof, or a laminated structure thereof, these have a great influence on the present invention. Since it is not a thing, it does not illustrate in particular.

  Further, in each of the following embodiments, the elements constituting the metal wiring are not particularly limited, and a typical metal wiring material is copper or an alloy containing copper as a main component, but aluminum, gold, or silver Such an element or an alloy containing them as a main component may be used, and the effect obtained by the present invention is not particularly limited by the wiring material.

  That is, in each of the following embodiments, since the electromagnetic phenomenon around and inside the metal wiring is used, the metal wiring material, the presence or absence of the surrounding substance in the metal wiring, or the material constant is not particularly limited. In addition, the effect can be obtained by the wiring structure disclosed by the present invention. Each of the following embodiments relates to a semiconductor device, but a semiconductor substrate is not particularly shown.

(First embodiment)
[Constitution]
FIG. 1 is a plan view showing a first embodiment of the semiconductor device according to the present invention, and FIG. 2 is a sectional view showing the first embodiment of the semiconductor device according to the present invention.

  As shown in FIGS. 1 and 2, a plurality of metal wirings 11 and 12 having substantially the same wiring width are disposed adjacent to each other on the semiconductor device. By arranging these metal wirings 11 and 12 adjacent to each other, a plurality of parallel wirings are formed. In addition, slits 13 and 14 are formed in the metal wirings 11 and 12 in parallel with the extending direction, respectively. The slits 13 and 14 are formed asymmetrically with respect to the extending direction of the metal wirings 11 and 12 when viewed from the upper surface of the metal wirings 11 and 12.

  As described in the background art, this is formed in order to suppress dishing in the planarization process when the metal wiring is formed by the planarization process. As a result, a decrease in the wiring film thickness due to dishing is suppressed, and an increase in the series resistance of the wiring is suppressed. In particular, in the case of a wide wiring having a wiring width of several micrometers or more, it is common to form a slit inside the wiring.

  Further, since the slits 13 and 14 are formed, the metal wiring parts 11a and 11b and the metal wiring parts 12a and 12b divided into a plurality of wirings are at least at the end thereof or at the upper layer or lower layer of the metal wiring. Another metal wiring located is connected to each other as a connecting portion. This is because the position and shape of the slit formed for the purpose of suppressing dishing is changed according to the degree of current concentration with respect to the metal wiring that should be originally formed as one wiring in this embodiment. But it is clear.

  FIG. 1 shows a state in which parts 11a and 11b and 12a and 12b of the metal wiring are connected at the terminal ends. The metal wiring having a slit in the following description has the connecting portion described above without particular notice.

  The metal wirings 11 and 12 are mounted on, for example, a semiconductor substrate having a transistor and used for power supply lines and ground lines.

  Next, the operation of this embodiment will be described.

  In the present embodiment, as indicated by reference numerals 15 and 16 in FIGS. 1 and 2, currents in opposite phases flow through the metal wirings 11 and 12. This reversed phase generally indicates a state where the phase is completely reversed, that is, a case where the phase difference is 180 degrees, but it is not necessary to be strictly reversed, and it may be substantially reversed. That is, in the present embodiment, it is assumed that the current directions are opposite to each other when the phase difference is 90 degrees to 270 degrees.

  As shown in FIGS. 1 and 2, the density of the slits 13 and 14 formed in parallel with the extending direction of the adjacent metal wirings 1 and 2 is equal to the inner portion in the region outside the metal wirings 11 and 12. It is formed higher than. More strictly speaking, when the center dividing lines 17 and 18 are drawn on the metal wirings 11 and 12, as shown in FIGS. 1 and 2, in the respective metal wirings 11 and 12, on the left and right sides of the center dividing lines 17 and 18, respectively. The density of the slits 13 and 14 in the metal wirings 11 and 12 is different. As in this embodiment, a wiring arrangement configuration in which a reverse-phase current flows in adjacent wiring pairs is widely used in designing a semiconductor device for the purpose of reducing leakage magnetic flux to the outside. . In this case, due to the proximity effect, currents flowing through the metal wires 11 and 12 are concentrated inside the metal wires 11 and 12. According to the present embodiment, since the slits 13 and 14 are disposed outside the metal wirings 11 and 12 adjacent to each other, an effective resistance increase due to current concentration generated inside each metal wiring is achieved. Can be suppressed. In particular, an increase in resistance due to the proximity effect can be suppressed in a high-frequency band higher than the gigahertz band.

  In the present embodiment, among the metal wirings divided into a plurality by the slits 13 and 14, the wiring width of the wiring having the narrowest line width is defined by the operating frequency and wiring material using the metal wiring. It is preferably about twice or more the skin depth. Here, if the wiring width is smaller than about twice the skin depth, the cross-sectional area of the metal wiring that contributes to conduction decreases, and as a result, the resistance of the metal wiring increases.

  As described above, in the present embodiment, in a plurality of metal wirings 11 and 12 adjacent to each other, a location where current concentration occurs is predicted from the positional relationship between adjacent metal wirings 11 and 12 and the operation characteristics of the circuit, and each current concentration is estimated. The slits 13 and 14 are formed avoiding the location where current concentration occurs according to the location and the degree thereof.

  Therefore, in the present embodiment, for example, in the metal wirings 11 and 12 adjacent to each other that are laid out so that currents of opposite phases flow, the slits 13 and 14 are formed outside the metal wirings 11 and 12 adjacent to each other. Thus, it is possible to prevent a decrease in the wiring film thickness due to dishing in the flattening process in the metal wiring forming process, and to suppress an increase in resistance due to the slits 13 and 14 where current concentration occurs in the metal wirings 11 and 12. Yes.

  Thus, according to the present embodiment, dishing can be suppressed to prevent a reduction in the wiring film thickness, and an increase in resistance of the metal wirings 11 and 12 during high-frequency operation can be suppressed as compared with the conventional technique. Thereby, low power consumption and low noise of the semiconductor device can be realized. In addition, since an increase in resistance of the metal wirings 11 and 12 can be suppressed, wiring delay can be reduced, and as a result, speeding up of the semiconductor device can be realized.

  Furthermore, according to the present embodiment, since current concentration in the metal wirings 11 and 12 can be relaxed, the electromigration resistance in the metal wirings 11 and 12 is improved, and as a result, a semiconductor device having high reliability is realized. be able to.

  According to the present embodiment, since only the slits 13 and 14 are formed to suppress the resistance rise, a semiconductor substrate is used because a plurality of levels of wiring layers are not used as in the method described in Patent Document 3, for example. And the parasitic capacitance between the metal wirings 11 and 12 does not increase. Electromagnetically, the formation of the slits 13 and 14 causes a parasitic capacitance between the metal wirings 11 and 12 that are connected in parallel to each other, but this is a metal that increases by using a multilayer level wiring. Compared to the parasitic capacitance between the wiring and the semiconductor substrate, the size is negligible, and does not cause the performance deterioration of the metal wirings 11 and 12.

  In addition, according to the present embodiment, it is possible to suppress an increase in resistance of the metal wirings 11 and 12 during high-frequency operation. Circuits such as an oscillator and a low noise amplifier can be realized, and a high-performance wireless communication semiconductor device with low loss can be realized.

  Next, a modification of the semiconductor device of this embodiment will be described.

  FIG. 3 is a plan view showing a first modification of the semiconductor device of this embodiment, and FIG. 4 is a cross-sectional view showing a first modification of the semiconductor device of this embodiment. In addition, the same code | symbol is attached | subjected and demonstrated to the part which is the same as that of the said 1st Embodiment, or respond | corresponds. The same applies to the following embodiments and modifications.

  As shown in FIGS. 3 and 4, in this modification, the slits 13 and 14 formed in the respective metal wirings 11 and 12 have a certain length with respect to the extending direction of the metal wirings 11 and 12. Are divided into multiple parts.

  Thus, according to this modification, the same effect as that of the first embodiment can be obtained. Other configurations and operations are the same as those in the first embodiment, and thus description thereof is omitted.

  FIG. 5 is a plan view showing a second modification of the semiconductor device of this embodiment, and FIG. 6 is a cross-sectional view showing a second modification of the semiconductor device of this embodiment.

  As shown in FIGS. 5 and 6, in this modification, a plurality of slits 13a, 13b, 14a, 14b are arranged substantially in parallel with the metal wires 11, 12 in parallel with the extending direction of the metal wires 11, 12. Is formed. Therefore, by forming the plurality of slits 13a, 13b, 14a, 14b, in addition to the first embodiment, a part 11c of the metal wiring and a part 12c of the metal wiring are formed.

  Thus, according to this modification, the same effect as that of the first embodiment can be obtained. Other configurations and operations are the same as those in the first embodiment, and thus description thereof is omitted.

  FIG. 7 is a plan view showing a third modification of the semiconductor device of this embodiment, and FIG. 8 is a cross-sectional view showing a third modification of the semiconductor device of this embodiment.

  As shown in FIGS. 7 and 8, in this modification, the slits 13 and 14 formed in a plurality are divided into a plurality in the extending direction of the metal wirings 11 and 12. In this case, it is preferable that the adjacent slits 13 and 14 are arranged so as to be adjacent to each other obliquely.

  As described above, according to the present modification, the slits 13 and 14 are formed by being divided into a plurality of portions in the extending direction of the metal wirings 11 and 12, thereby suppressing dishing more effectively. .

[Production method]
Next, the manufacturing method of this embodiment is demonstrated with reference to FIG.

  9 shows a so-called single damascene in which the metal wirings 11 and 12 are formed after forming the lower level wiring 20 of the metal wiring to be formed and the via 21 for electrically connecting the lower level wiring 20 and the metal wiring. It is explanatory drawing which shows the manufacturing method about a method. However, the present embodiment can be similarly applied to the case where the metal wiring and the via are formed by the so-called dual damascene method in which the via 21 positioned below the metal wiring and the metal wiring are simultaneously formed.

  As shown in FIG. 9A, the lower level wiring 20 of the metal wiring to be formed and the via 21 are formed to form the lower level wiring 20 and the metal wirings 11 and 12. An insulating film 22 is formed thereon as much as possible as a wiring interlayer insulating film.

  The insulating film 22 is an insulating film containing an element such as silicon, oxygen, hydrogen, fluorine, carbon, or nitrogen. However, in this embodiment, the material of the insulating film is not particularly limited. The insulating film 22 is deposited by a known insulating film forming method such as chemical vapor deposition or coating. Further, depending on the processing method of the insulating film 22, the insulating film 22 may use a laminated structure of two or more insulating films having different compositions, but the illustration is omitted here.

  Next, as shown in FIG. 9B, wiring grooves 23a, 23b, 24a, and 24b are formed by using a pattern forming method typified by a photolithography method and a processing technique typified by a reactive etching method. Here, in this embodiment, a slit is formed between the wiring groove 23a and the wiring groove 24a, which are later formed as the metal wiring 11, and between the wiring groove 23b and the wiring groove 24b, which are formed later as the metal wiring 12, respectively. A predetermined wiring pattern is formed to form 13 and 14.

  Further, in the present embodiment, the positions of the slits 13 and 14 are adjusted according to the positional relationship between the metal wirings 11 and 12 to be formed later. That is, in the present embodiment, currents in opposite phases flow through the metal wirings 11 and 12, so that the slits 13 and 14 are formed outside the metal wirings 11 and 12.

  Next, in FIG. 9C, a metal material 25 for forming a metal wiring is embedded in the wiring groove by a method such as sputtering, chemical vapor deposition, or plating. For example, copper or an alloy containing copper as a main component is used as the metal material 25, but the present invention is not limited by the type of the metal material. Also, in many cases, before the metal wiring material 25 is deposited, in order to prevent the metal wiring material 25 from diffusing into the insulating film 22, a laminated structure of a thin refractory metal generally called a barrier metal and its compound is used. Although it is often deposited, the illustration is omitted here.

  Next, in FIG. 9D, in order to form the metal wirings 11 and 12, the metal wiring material 25 is flattened by, for example, a chemical mechanical polishing method to obtain the metal wirings 11 and 12. Since the slits 13 and 14 are formed by the insulating film 22 at the time of the planarization, excessive polishing of the metal wiring material 25 is suppressed by dishing accompanying the planarization. As a result, the metal wirings 11a, 11b and 12a, 12b constituting the metal wirings 11 and 12, respectively, have a desired film thickness, and an increase in wiring resistance can be suppressed.

  By the above manufacturing method, metal wirings 11 and 12 which are adjacent to each other and in which slits 13 and 14 are formed are obtained. Since the metal wirings 11 and 12 thus obtained have slits 13 and 14 formed therein, it is possible to prevent a reduction in wiring film thickness due to dishing. Therefore, an increase in resistance can be suppressed, currents in opposite phases flow, and the slits 13 and 14 are formed outside the metal wirings 11 and 12 adjacent to each other. Can be suppressed.

[Comparative example]
Next, from the viewpoint of the rate of increase in wiring resistance, the conventional method and the wiring structure and manufacturing method according to this embodiment are compared, and the superiority of this embodiment is described.

  After a silicon oxide film is deposited on a silicon substrate by about 4 micrometers, two metal wirings 11 and 12 having a wiring length of 100 micrometers, a wiring width of 5 micrometers, and a film thickness of about 1 micrometer are parallel to each other by the damascene method. Formed at intervals of 2.5 micrometers. Slits 13 and 14 according to the prior art and the present embodiment were formed in these two metal wirings, respectively, and currents of opposite phases were passed to examine the respective resistance values.

  As a conventional slit forming method, as shown in FIGS. 19 and 20, slits 5 and 6 having a width of 0.5 μm are provided at positions corresponding to the center dividing lines 5 and 6 of the respective metal wirings 1 and 2, respectively. Formed. The effective wiring resistance value at 20 GHz of the metal wirings 1 and 2 thus formed was 3.16 ohms.

  Next, slits 13 and 14 according to the present embodiment were formed in the metal wiring. That is, in this embodiment, since currents flow in two phases opposite to each other in the metal wirings 11 and 12, the slits 13 and 14 are formed in portions outside the metal wirings 11 and 12. The effective wiring resistance value at 20 GHz of the metal wirings 11 and 12 thus formed was 2.99 ohms.

  As described above, the effective resistance value in the high-frequency band can be reduced by about 5% by using the slit arrangement according to the present embodiment as compared with the conventional technique, thereby demonstrating the superiority of the present embodiment. .

  The present embodiment is applicable to a transistor and a multilayer metal wiring that are formed of copper or an alloy containing copper as a main component. The present embodiment can also be applied to a multilayer wiring structure having a plurality of metal wiring layers of at least two layers. In this case, some metal wirings in the metal wiring of at least one layer are slit. have.

(Second Embodiment)
A second embodiment of the present invention will be described with reference to FIGS. FIG. 10 is a plan view showing a second embodiment of the semiconductor device according to the present invention, and FIG. 11 is a cross-sectional view showing the second embodiment of the semiconductor device according to the present invention. In addition, the same code | symbol is demonstrated to the part which is the same as that of the said 1st Embodiment, or respond | corresponds. The same applies to the following embodiments and modifications.

  Unlike the first embodiment, the present embodiment is applied when currents having the same phase flow as shown by reference numerals 15 and 16 in the metal wirings 11 and 12 adjacent to each other, and the effect can be obtained. Here, the above-mentioned in-phase generally indicates a state in which the phases are completely coincident, that is, a case where the phase difference is 0 degree, but it is not necessary to exactly coincide with each other, and may be substantially in-phase. That is, in this embodiment, when the phase difference is −90 degrees to 90 degrees, the current directions are in phase.

  As shown in FIGS. 10 and 11, by arranging the metal wirings 11 and 12 adjacent to each other, a plurality of parallel wirings are formed. In addition, slits 13 and 14 are formed in the metal wirings 11 and 12 in parallel with the extending direction, respectively. By forming these slits 13 and 14, the metal wiring parts 11a and 11b and the metal wiring parts 12a and 12b divided into a plurality of wirings are at least at the ends thereof or at the upper layer or lower layer of the metal wiring. Another metal wiring located is connected to each other as a connecting portion.

  As described in the background art, this is formed in order to suppress dishing in the planarization process when the metal wiring is formed by the planarization process. As a result, a decrease in the wiring film thickness due to dishing is suppressed, and an increase in the series resistance of the wiring is suppressed. In particular, in the case of a wide wiring having a wiring width of several micrometers or more, it is common to form a slit inside the wiring.

  As described above, in this embodiment, as indicated by reference numerals 15 and 16 in FIGS. 10 and 11, currents in the same phase flow through the metal wirings 11 and 12, respectively. 10 and 11, the slits 13 and 14 formed in parallel with the extending direction of the adjacent metal wirings 11 and 12 are inside the center dividing lines 17 and 18 of the respective metal wirings 11 and 12. Is formed. In this case, due to the proximity effect, currents flowing through the respective wirings are concentrated outside the respective metal wirings 11 and 12, but in the present embodiment, the slits 13 and 14 are formed by the respective metal wirings 11 and 12 as described above. Since they are arranged inside the 12 center dividing lines 17 and 18, it is possible to suppress a substantial increase in resistance due to current concentration generated outside the respective metal wirings 11 and 12. In particular, an increase in resistance due to the proximity effect can be suppressed in a high-frequency band higher than the gigahertz band.

  In the present embodiment, among the metal wirings divided into a plurality by the slits 13 and 14, the wiring width of the wiring having the narrowest line width is defined by the operating frequency and wiring material using the metal wiring. It is preferably about twice or more the skin depth. Here, if the wiring width is smaller than about twice the skin depth, the cross-sectional area of the metal wiring that contributes to conduction decreases, and as a result, the resistance of the metal wiring increases.

  As described above, according to this embodiment, the present invention can be easily applied to adjacent wiring in which a common-mode current always flows, such as an inductor on a semiconductor substrate formed of metal wiring. For example, although an inductor can be cited as an electronic circuit element necessary for a circuit that handles a signal in the gigahertz band, a known spiral inductor formed of a metal wiring on a semiconductor substrate has the highest current concentration among the configurations. The locations are inside the innermost wiring of the spiral and outside the outermost wiring, and this phenomenon can be predicted using a method such as electromagnetic field simulation. In the present embodiment, any of these is avoided to form the slits 13 and 14. However, in this embodiment, when applied to the spiral inductor, the slits 13 and 14 are arranged so as to be biased to the left or right with respect to the center dividing lines 17 and 18 of the extending metal wirings 11 and 12. As a result, the effect of this embodiment is impaired in either the innermost wiring or the outermost wiring, but in this case, each case is predicted and compared by a method such as electromagnetic field simulation. The slit position may be determined so that the resistance increase suppressing effect can be obtained more.

  Next, a modification of the semiconductor device of this embodiment will be described.

  FIG. 12 is a plan view showing a first modification of the semiconductor device of this embodiment, and FIG. 13 is a cross-sectional view showing a first modification of the semiconductor device of this embodiment.

  As shown in FIGS. 12 and 13, in this modification, the slits 13 and 14 formed in the respective metal wirings 11 and 12 have a certain length with respect to the extending direction of the metal wirings 11 and 12. Are divided into multiple parts.

  Further, in the present embodiment, although not shown, a plurality of slits are formed in the respective metal wirings 11 and 12 in parallel with the extending direction of the metal wirings 11 and 12, as in the second modification of the first embodiment. 13a, 13b, 14a, 14b may be formed. Further, although not shown, as in the third modification of the first embodiment, the plurality of formed slits 13a, 13b, 14a, 14b are further provided in a plurality in the extending direction of the metal wirings 11, 12. It may be divided. In this case, it is preferable that the adjacent slits 13 and 14 are arranged so as to be obliquely adjacent to each other. By arranging the slits 13 and 14 as described above, it is possible to more effectively suppress dishing.

[Production method]
The manufacturing method of this embodiment differs from the manufacturing method of the first embodiment only in the positions of the slits 13 and 14 formed in the metal wirings 11 and 12. Therefore, as the manufacturing method of the present embodiment, the same manufacturing method as that of the first embodiment is used, and only the positions where the slits 13 and 14 are formed need be changed. Therefore, a detailed description of the manufacturing method of this embodiment is omitted.

(Third embodiment)
A third embodiment of the present invention will be described based on FIG.

  FIG. 14 is a plan view showing a third embodiment of the semiconductor device according to the present invention. In the third embodiment, the present invention is applied to a spiral wiring pattern formed on a semiconductor substrate, that is, a spiral inductor formed by laying out metal wiring in a known spiral turn shape.

  As shown in FIG. 14, in the present embodiment, a metal wiring 30 spirally formed on a semiconductor substrate to form a spiral inductor, a lead line 31, and a via (not shown) connecting them. Consists of In this embodiment, slits 32 are formed in the metal wiring 30 that forms the spiral inductor.

  As described above, according to the present embodiment, when currents of the same phase flow through the metal wirings adjacent to each other by the slit 32 as in the second embodiment, an increase in resistance due to the proximity effect at high frequency is suppressed, and a high-performance spiral is achieved. An inductor can be obtained.

  In the present embodiment, a slit may be similarly formed in the metal wiring that becomes the lead line 31. In addition, a structure using a multi-level wiring layer for the spiral inductor, for example, a structure in which spiral inductors formed in multi-level wirings are connected in series with each other, or a structure in which spiral inductors formed in multi-level wiring layers are connected in parallel to each other Even if the slit 32 according to the present embodiment is formed, the same effect can be obtained.

  Further, in the present embodiment, the wiring width of the thinnest wiring among the metal wirings divided into a plurality by the slit 32 is the skin depth defined by the operating frequency and wiring material using the metal wiring. It is preferable that it is about twice or more. Here, if the wiring width is smaller than about twice the skin depth, the cross-sectional area of the metal wiring that contributes to conduction decreases, and as a result, the resistance of the metal wiring increases.

[Comparative example]
Next, from the viewpoint of improving the performance of the inductor formed of metal wiring, the conventional method and the wiring structure and manufacturing method according to the present embodiment are compared, and the superiority of the present embodiment is described with reference to FIGS. To do.

  FIG. 15 shows the frequency dependence of the inductance value of an inductor formed by metal wiring having different wiring shapes. As the wiring structure, (1): a structure without slits, (2): a structure in which a slit is formed at the center of the wiring as shown in FIGS. 19 and 20 by the conventional method described in Patent Document 2, and (3) : As shown in FIG. 14, there are three types of structures according to the present embodiment in which the slit 32 is formed only inside the metal wiring 30. The inductance value of each structure is calculated from the measured S parameter.

  Comparing the inductance values of each structure, in the structure of Patent Document 2, the induced current loss is reduced by blocking the induced current path, and as a result, the inductance value is increased. Is invited. Further, the cause of the increase in the inductance value may be that the inductance value is improved by mutual inductance because the configuration of the inductor is a parallel connection of a plurality of wires.

  On the other hand, although the inductance value of the structure of the present embodiment of (3) is higher than that of the structure without slits of (1) as in Patent Document 2 of (2), the resonance frequency does not decrease. This is due to the fact that the increase in inductance is smaller than that of the prior art and that the equivalent resistance is smaller than that of the structure described in Patent Document 2 of (2), so that the influence of parasitic capacitance is less visible. Can be interpreted.

  On the other hand, in the figure which shows the resistance value of each structure shown in FIG. 16, since the equivalent resistance in the structure of patent document 2 of (2) is the highest, this is because the slits 3 and 4 were formed in the center of the wiring. This is because the resistance is increased under the influence of current concentration. On the other hand, the resistance value of the structure of the present embodiment (3) is lower than that of the prior art, indicating the superiority of the present embodiment.

  Finally, FIG. 17 shows the frequency dependence of the Q value of the inductance formed by the metal wiring. As shown in FIG. 17, it can be seen that the Q value of the inductor formed by the method described in Patent Document 2 in (2) is improved as compared with the structure without slits in (1). It can be seen that the structure of this embodiment shows the highest Q value. In the method described in Patent Document 2 of (2), the resonance frequency is lowered, which is understood from the frequency dependence of the equivalent resistance value and inductance value of each structure of FIGS. 15 and 16 described above. The

  As described above, according to the spiral inductor according to the third embodiment, the Q value of the spiral inductor can be improved without increasing an undesirable parasitic capacitance, thereby demonstrating the superiority of the present embodiment.

[Production method]
The manufacturing method of this embodiment differs from the manufacturing method of the first embodiment only in the positions of the wiring pattern and slit 32 formed in the metal wiring 30. Therefore, as the manufacturing method of the present embodiment, the same manufacturing method as that of the first embodiment is used, and only the formation pattern of the wiring groove and the position where the slit 32 is formed need be changed. Therefore, a detailed description of the manufacturing method of the present embodiment is omitted.

  In the present embodiment, it is more preferable to predict a location where current concentration occurs in advance according to the wiring layout of the spiral inductor and to form a slit pattern to avoid the current concentration location.

(Fourth embodiment)
A fourth embodiment of the present invention will be described based on FIG.

  FIG. 18 is a plan view showing a fourth embodiment of the semiconductor device according to the present invention. In the fourth embodiment, the present invention is applied to a structure in which a part of metal wiring adjacent to each other is bent.

  As shown in FIG. 18, in this embodiment, the bent portions are formed in the metal wirings 41 and 42 having substantially the same wiring width, and therefore, the relationship such as the in-phase or the reverse phase in the current direction with the adjacent metal wiring. Are different layouts in the same metal wiring. In order to apply such a structure, the position of the slit in the same wiring with respect to the metal wiring and the metal wiring having the bent portion is reversed on the left and right with respect to the extending direction of the metal wiring. Need arises.

  Therefore, in the present embodiment, regions 43 and 44 having slits 53 and 54 arranged at equal intervals in a part of the metal wirings 40 and 41 by a known method, and regions not having the slits (not shown). And the regions 43 and 44 having the slits 53 and 54 arranged at equal intervals or the region having no slits as a boundary, on the left and right sides with respect to the extending direction of the metal wirings 40 and 41. Slits 49, 50, 51, 52 are formed to reverse the position of the slit.

  In addition, the metal wiring 41 has slits 51 and 52 and a bent portion. The metal wiring 41 has slits 51 and 52 in addition to the bent portion, and the position of the slit in the metal wiring 41 with the bent portion as a boundary. It is reversed left and right with respect to the extending direction. The metal wiring 41 has slits 51 and 52 and a bent portion, and has slits 53 arranged at equal intervals in the bent portion, and the position of the slit in the metal wiring 41 with the bent portion as a boundary. The metal wiring 41 is reversed left and right with respect to the extending direction.

  Further, with respect to the metal wiring 42, the relationship between the current direction 47 flowing through the metal wiring 42 and the currents 45 and 46 flowing through the metal wirings 40 and 41 adjacent to the metal wiring 42 is always in phase. What is necessary is just to form the slit 48 by a form.

  As described above, according to the present embodiment, the resistance due to the proximity effect in the high frequency band in the metal wiring in which the relationship such as the in-phase or the reverse phase in the current direction with the adjacent metal wirings 40 and 41 is different in the same metal wiring. The rise can be suppressed.

  In the present embodiment, among the metal wirings divided into a plurality by the slits, the wiring width of the wiring having the smallest line width is the skin frequency defined by the operating frequency and wiring material using the metal wiring. It is preferably approximately twice or more. Here, if the wiring width is smaller than about twice the skin depth, the cross-sectional area of the metal wiring that contributes to conduction decreases, and as a result, the resistance of the metal wiring increases.

[Production method]
The manufacturing method of this embodiment differs from the manufacturing methods of the first and second embodiments only in the positions of slits formed in the metal wiring. Therefore, as the manufacturing method of the present embodiment, the same manufacturing method as that of the first embodiment is used, and only the position where the slit is formed needs to be changed. Therefore, a detailed description of the manufacturing method of this embodiment is omitted.

  As an application example of the present invention, application to a multilayer wiring of a semiconductor device having a transistor and a multilayer wiring is mentioned. As the performance of semiconductor devices improves, the operating frequency is expected to increase in the future. Moreover, it is thought that the use in the high frequency band used for radio | wireless communication will expand further.

1 is a plan view showing a first embodiment of a semiconductor device according to the present invention. 1 is a cross-sectional view showing a first embodiment of a semiconductor device according to the present invention. It is a top view which shows the 1st modification of 1st Embodiment of the semiconductor device which concerns on this invention. It is sectional drawing which shows the 1st modification of 1st Embodiment of the semiconductor device which concerns on this invention. It is a top view which shows the 2nd modification of 1st Embodiment of the semiconductor device which concerns on this invention. FIG. 6 is a cross-sectional view showing a second modification of the first embodiment of the semiconductor device according to the present invention. It is a top view which shows the 3rd modification of 1st Embodiment of the semiconductor device which concerns on this invention. FIG. 6 is a cross-sectional view showing a third modification of the first embodiment of the semiconductor device according to the present invention. 1 is a cross-sectional view showing a manufacturing method of a first embodiment of a semiconductor device according to the present invention. It is a top view which shows 2nd Embodiment of the semiconductor device which concerns on this invention. It is sectional drawing which shows 2nd Embodiment of the semiconductor device which concerns on this invention. It is a top view which shows the modification of 2nd Embodiment of the semiconductor device which concerns on this invention. It is sectional drawing which shows the modification of 2nd Embodiment of the semiconductor device which concerns on this invention. It is a top view which shows 3rd Embodiment of the semiconductor device which concerns on this invention. It is explanatory drawing which shows the characteristic of the inductor by 3rd Embodiment of the semiconductor device which concerns on this invention. It is explanatory drawing which shows the characteristic of the inductor by 3rd Embodiment of the semiconductor device which concerns on this invention. It is explanatory drawing which shows the characteristic of the inductor by 3rd Embodiment of the semiconductor device which concerns on this invention. It is a top view which shows 4th Embodiment of the semiconductor device which concerns on this invention. It is a top view which shows the conventional semiconductor device (patent document 2). It is sectional drawing which shows the conventional semiconductor device (patent document 2).

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 Metal wiring 12 Metal wiring 13 Slit 14 Slit 15 Current direction 16 Current direction 17 Center dividing line 18 Center dividing line 20 Lower level wiring 21 Via 22 Insulating film 23a, 23b Wiring groove 24a, 24b Wiring groove 25 Wiring material 30 Metal wiring 31 Lead line 32 Slit 40 Metal wiring 41 Metal wiring with bent portion 42 Metal wiring with bent portion 43 Region with equally spaced slits 44 Region with equally spaced slits 45 Current direction 46 Current direction 47 Current direction 48 slits 49 slits 50 slits 51 slits 52 slits 53 slits arranged at regular intervals 54 slits arranged at regular intervals

Claims (18)

Adjacent metal wirings through which alternating currents of substantially opposite phases flow are arranged, slits are formed in these metal wirings, respectively, and the slits in each of the adjacent metal wirings are viewed from the top surface of the metal wiring. It forms asymmetrically with respect to the extending direction of the wiring, and the density of the slits formed on the outside of each of the adjacent metal wirings is higher than the density of the slits formed on the inside of each of the adjacent metal wirings. A semiconductor device characterized by being formed so as to be higher . Adjacent metal wirings through which alternating currents having substantially the same phase with each other are arranged, slits are formed in these metal wirings, and the slits in each of the adjacent metal wirings are viewed from the top surface of the metal wiring. And the density of the slits formed inside each of the adjacent metal wirings is higher than the density of the slits formed outside each of the adjacent metal wirings. A semiconductor device formed so as to be higher. The slit is a semiconductor device according to claim 1 or 2, characterized in that it is formed in a plurality with respect to the extending direction of the metal wiring. 3. The semiconductor device according to claim 1, wherein a plurality of the slits are formed in parallel and substantially in parallel with the extending direction of the metal wiring. The slit A semiconductor device according to claim 4, characterized in that it is formed in a plurality with respect to the extending direction of the metal wiring. The semiconductor device according to claim 5 , wherein the plurality of divided slits are arranged so as to be obliquely adjacent to each other. The metal wiring semiconductor device according to any one of claims 1 to 6, characterized in that it is mounted on a semiconductor substrate having a transistor. The semiconductor device according to claim 2 , wherein an induction element is formed by a metal wiring having the slit. A metal wiring having a slit, a semiconductor device according to any one of claims 1 to 7, characterized in that it is used to power line. The metal wiring having the slit is used as a grounding wire.
The semiconductor device as described in any one of thru | or 7 . The wiring width of the narrowest wiring among the metal wiring divided into a plurality by the slit is larger than about twice the skin depth defined by the operating frequency and the metal wiring material. Item 11. The semiconductor device according to any one of Items 1 to 10 . Has a transistor and a multilayer metal wiring, the semiconductor device according to any one of claims 1 to 11 metal wiring of the multilayer is characterized in that it is formed of an alloy containing the copper or copper . In the multilayer interconnection structure having at least two layers of a plurality of metal wiring layers, part of the metal wiring in at least one layer of metal wires, any one of claims 1 to 12 and having the slit one The semiconductor device according to item. The metal wiring has a slit and a bent portion, and has a slit in addition to the bent portion, and the position of the slit in the metal wiring is left and right with respect to the extending direction of the metal wiring with the bent portion as a boundary. the semiconductor device according to any one of claims 1 to 13, characterized in that it is reversed. The metal wiring has a slit and a bent portion, and has slits arranged at equal intervals in the bent portion, and the position of the slit inside the metal wiring with the bent portion as a boundary is the extension of the metal wiring. the semiconductor device according to any one of claims 1 to 13, characterized in that it is inverted right and left relative to the running direction. The metal wiring having the slit does not have a slit in a part, and the position of the slit in the metal wiring is reversed left and right with respect to the extending direction of the metal wiring, with the portion having no slit as a boundary. the semiconductor device according to any one of claims 1 to 13, characterized in that there. The metal wiring having the slits has slits arranged at equal intervals in part, and the positions of the slits in the metal wiring with respect to the part having the equally spaced slits as the extending direction of the metal wiring the semiconductor device according to any one of claims 1 to 13, characterized in that it is left-right reversed with respect. Wherein the plurality of metal wires, the semiconductor device according to any one of claims 1 to 17, characterized in that it has a substantially equal line width.

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