JP4650928B2 - Scan flip-flop circuit, scan test circuit and test design method using the same - Google Patents

Description

  The present invention relates to a scan test circuit and a semiconductor integrated circuit device including the same, and more particularly to a scan test circuit that facilitates testing.

    In recent years, scan design is often used as a design for testability accompanying high integration of LSI. This is a method in which a sequential circuit in a logic circuit is controlled through a test mode path (scan path) to operate as one shift register. FIG. 9 shows a scan flip-flop 200 that is generally used. This is a circuit having a selector inside the scan flip-flop 200, and selectively inputs one of data (DataIn terminal signal) and shift data from the combinational circuit according to ScanEnable. By replacing the flip-flop associated with the path to be tested with the scan flip-flop 200 and connecting them in a daisy chain via the shift data, this shift register (scan path) is used by configuring as a serial shift register. Thus, a value can be directly written to or read from the flip-flop to be tested.

On the other hand, among the demands for high reliability, not only the detection of stuck-at faults whose logic value is fixed to '0' or '1', but also subtle delay faults that become a problem in actual operation as the operation speed increases. There is a need for an appropriate and easy test technique (delay test) for detection.
A delay test method will be described with reference to FIG. FIG. 11 shows one of the typical delay test methods called the broadside method. As a stage before starting the delay test, a value before transition is set in each scan flip-flop connected in a shift register form in a shift cycle (scan-in). After that, the clock (TestClock) is input twice (A, B) while the scan enable signal (ScanEnable) is inactive, that is, with the shift cycle released.

  The signal Y propagated through the logic circuit in the previous stage is set in the scan flip-flop corresponding to the start point of the path to be tested at the first clock (A), and the scan flip-flop corresponding to the end point of the path to be tested is scanned in. A signal X ′ in which the influence of the value X set in the start point scan flip-flop is propagated to the logic circuit is input and set.

  In the second clock (B), the influence of Y, which is the value input and set in the start flip-flop at the first clock (A) to the scan flip-flop corresponding to the end point through the path to be tested, is a logic circuit. The signal Y ′ propagated to is input and set. Thereafter, the scan enable signal is activated to scan out the value of each scan flip-flop, and it can be determined whether or not the value set in each scan flip-flop is correct. At this time, if the time from A to B is the same as the actual operation, a delay test (at speed test) of the actual operation speed can be performed. However, if X and Y are the same value, it cannot be determined whether or not it is operating correctly. Therefore, in the delay fault test, the logical value of the starting point is changed (X → Y is changed from “0” to “1”, or “1”. It is necessary to observe whether the transition is correctly transmitted to the end point at the actual operation speed.

  In the case of scan test design using the scan flip-flop 200, the value X before transition can be easily set by scan-in, but the setting of the value Y after transition is the forward combination circuit configuration of the scan flip-flop corresponding to the start point of the test target path It is difficult to make a value that transitions reliably because it depends on. In order to easily execute an appropriate test using an actual operating frequency, Patent Document 1 uses a scan flip-flop that inverts an output bit in a cycle immediately before data acquisition from a test target circuit. The transition of logical values is facilitated. Patent Document 1 discloses that static timing verification is performed, and a scan flip-flop that inverts an output bit is replaced only for a flip-flop that is a starting point of a path having no timing margin.

  FIG. 10 shows an example of an easy-to-invert scan flip-flop 201 circuit that transitions logical values in the clock cycle disclosed in Patent Document 1, and includes a general scan flip-flop 200 and a selection signal (DelayTestMode terminal) that controls the selection. A selector that selects and outputs an inverted output (QB terminal signal) of the scan flip-flop 200 or data (DataIn terminal signal) from the combinational circuit according to the signal). The invertible scan flip-flop 201 selects an inverted output (QB terminal signal) as an input when the DelayTestMode signal is at a high level (H) in the selector, and inverts at the rising edge of the clock signal (TestClocK signal) input to CLK. An output (QB terminal signal) is set and output. When the DelayTestMode signal is at a low level (L), data from the combinational circuit (DataIn terminal signal) is selected and output in the same manner. That is, if the inversion-type scan flip-flop 201 is used, the logic value can be easily changed during the delay test without depending on the preceding combinational circuit.

JP 2001-4710 A (page 5-7, FIG. 5)

However, in a path that has been detected by the above-described static timing verification and has no timing margin, the number of flip-flops at the start point relative to the flip-flop at the end point is not necessarily 1, and depending on the logic value of the flip-flop at the other start point In some cases, the transition of the logic value in the scan flip-flop (invertible scan flip-flop 201) that inverts the output bit that has been replaced does not propagate to the observation point, and the delay fault test may not be possible.

  7 and 8 are examples showing the above events. Common constituent elements are denoted by common reference characters / numbers and used in the description.

  At the stage of scan design, the flip-flops (FF) 1, 2, 3, 4, 5, 6, 7, 8, and 9 use the scan flip-flop 200 shown in FIG. There is a combinational circuit between the scan flops 1, 2, 3, 4 and the scan flip-flops 6, 7, 8, 9. 102 is a NAND circuit, 103 is an OR circuit, 104 is an AND circuit, 105 is a NOR circuit, 106 is an OR circuit, and 107 is an AND circuit. Each scan flip-flop is connected in the form of a shift register via shift data C1, C2, C3, C4, and C5. A path passing through the signal lines S1, S2, S3, and S4 is a target path for the delay fault test. As disclosed in Patent Document 1, it is assumed that the target path is extracted as a data propagation path between flip-flops with no timing margin based on the static timing check result, and in order to perform a transition reliably during the test cycle, As disclosed in Patent Document 1, only the flip-flop 1 serving as the start point of a path with no margin in timing is replaced with a scan flip-flop (invertible easy-type scan flip-flop 201) that inverts output bits.

  In the shift cycle (scan-in), the scan flip-flop 1 replaced from the normal scan flip-flop 200 to the invertible scan flip-flop 201 is changed from the logical value “0” to “1” in the test cycle. Is propagated to the target path. However, when the logical value of the signal line S5 is “0”, the signal line S2 is logically “1” regardless of the logic of the signal line S1, and the output bit after the replacement is changed. Inverted scan flip-flop transitions do not propagate. Therefore, the logical value of the signal line S5 must be “1”. Similarly, the signal line S6 must have a logical value “0”, and the signal line S7 must have a logical value “1”. In order to create this logic, the scan flip-flops 2, 3, and 4 are respectively “1”, “0”, and “1” while the logic value of the scan flip-flop 1 is changed from “0” to “1”. A logical value must be output.

  However, there are cases where this logic cannot be created due to the circuit configuration.

  The inversion and holding of the logical value of the scan flip-flop is performed by data input or scan input in a clock cycle. That is, in order to hold the output value of the scan flip-flop 2 at “1” during the test cycle in the circuit configuration of FIG. 7, the scan flip-flop 2 is set to “1” immediately before the test cycle, In the first clock (A), it is necessary to input either “1” by the shift data C3 or input “1” by the data input S9.

  In the former case, in order to input “1” by the shift data C3, the scan flip-flop 3 must be “1” immediately before the test cycle. On the other hand, in order to propagate the transition of the target path, the scan flip-flop 3 must be scanned. Since the flip-flop 3 must be fixed to “0”, the value set immediately before the test cycle must also be “0”, and S5 and S6 are simultaneously held at values that do not affect the target path. You can't keep it.

  In the latter case, for example, in the case of the circuit as shown in FIG. 8, the logical values of the signal lines S9 and S11 are set to “1” so as to keep the holding conditions of the scan flip-flop 2 and the scan flip-flop 4. , 9, the signal lines S8, S10 to the scan flip-flops 1, 3 cannot be set to '1' and '0', respectively. In such a case, if the circuit disclosed in Patent Document 1 is used, the scan flip-flop 1 can create a transition regardless of the shift data C4 logic value or the signal line S8 logic value. However, the value of the scan flip-flop 3 cannot be fixed to “0”.

  In other words, in the known technique, the transition of the logic value in the invertible scan flip-flop 201 that inverts the output bit that has been replaced for the detection of the delay fault in the test target circuit is the other end of the test target circuit. Depending on the logic value of the flip-flop that is the starting point of the path, it does not propagate and the delay fault test may not be possible. Therefore, it is a problem to set the other paths to appropriate values that do not affect the delay test.

Prepare a scan flip-flop that has a mode to hold the output value regardless of the input value, and select the flip-flops that are not on the target path among all the flip-flops related to the end-point of the test target path. Regardless of the path, the scan flip-flop having a mode for holding the output value replaces the path other than the target path at the time of delay fault detection of the target path, and inversion that is the starting point of the target path The signal transition in the easy scan flip-flop is reliably propagated to the circuit under test. The test design method of the present invention includes a scan chain configured by a series connection circuit of a plurality of flip-flops for testing an internal circuit of an LSI including a logic circuit, and operates as a shift register. Scan test data and a clock are input, logical operation is performed by the internal circuit, and a scan path test for confirming that the internal circuit is operating normally based on scan-out result data that is an output of the operation result, In a test design in which a timing test of actual operation speed is performed in two cycles of an input clock, a first step of extracting a signal propagation path to be tested and a first step provided at an end point of the test target signal propagation path The effect of propagation within one cycle of the clock input to the flip-flop A second step of replacing the second flip-flop with a holding / inverting mixed scan flip-flop, and the second flip-flop having an effect of propagation within one period of the clock input to the first flip-flop. Determines a first value to be output in the first cycle of the two cycles and a second value to be output in the second cycle of the two cycles, the first value and the second value The second flip-flop is used for the fourth step for determining whether the values are equal to the first mode when the determination results of the fourth step are equal, and for the second mode if they are different. A fifth step of setting a mode, wherein the holding and inverting mixed scan flip-flop has a previous cycle regardless of an input value from an input terminal in the first mode. The value output from the output terminal is held and output, and in the second mode, the value output from the output terminal is inverted and output in the previous cycle regardless of the input value from the input terminal. In this mode, the input value from the input terminal is output.

  By the above means, it becomes possible to test the delay failure detection (delay test) of the target path which could not be tested by the conventional scan chain configuration or the data input configuration.

  Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings.

  FIG. 1 is a circuit diagram of an easy-to-hold scan flip-flop 202 according to the present invention, which retains a logical value even when the clock cycle transitions. The easy-to-hold scan flip-flop 202 has an output (Q terminal signal) of the scan flip-flop 200 according to a general scan flip-flop 200 (scan flip-flop body) and a selection signal (DelayTestMode terminal signal) for controlling selection. Or a selector 302 that selects and outputs data (DataIn terminal signal) from the combinational circuit. The easy-to-hold scan flip-flop 202 selects the output (Q terminal signal) as an input when the DelayTestMode signal is at a high level (H) in the selector, and outputs it at the rising edge of the clock signal (TestClocK signal) input to CLK. The value of (Q terminal signal) is output for one TestClocK period until the next rising edge of the clock signal (TestClocK signal) is input to CLK. When the DelayTestMode signal is at a low level (L), data from the combinational circuit (DataIn terminal signal) is selected and output in the same manner.

  FIG. 2 shows a scan flip-flop 1 that affects propagation within one cycle with respect to the scan flip-flop 5 corresponding to the end point of the target path when performing a delay test using the paths passing through S1, S2, S3, and S4 as target paths. 2, 3, and 4, the scan flip-flop 1 determines that the logical configuration value is difficult to invert, and the scan flip-flop 3 determines that the logical configuration value is difficult to hold. In this example, the flip-flop 201 is replaced, and the scan flip-flop 3 is replaced with the holding facilitating circuit 202. Here, one DelayTestMode signal is commonly connected to the scan flip-flops 1 and 3, but this is not restrictive. The ScanEnable signal is omitted. It is assumed that the scan flip-flop 2 and the scan flip-flop 4 can easily generate necessary values by a logical configuration.

  In FIG. 2, the timing of the signal S1 connected to the output of the scan flip-flop 1 replaced with the easy-inversion scan flip-flop 201 and the easy-to-hold scan flip-flop 202, and the signal S6 connected to the output of the scan flip-flop 3, respectively. A chart is shown in FIG. 3 to explain the operation.

  In the last cycle T0 of the shift cycle (scan-in), the logical value of the scan flip-flop is set. In FIG. 3, “0” is set in the scan flip-flop 1 and the scan flip-flop 3. Thereafter, before the first clock timing (A) is generated in the test cycle, the scan enable signal is made inactive to stop the scan-in, and the value of each flip-flop immediately before the test cycle is determined. Next, by activating the DelayTestMode signal, the replaced scan flip-flops 1 and 3 have “1” which is an inverted value of the signal S1 connected to the respective outputs and a hold value “0” of the signal S6. Are input, the scan flip-flops 1 and 3 output “1” and “0”, respectively, at the first clock timing (A). As a result, “0” is propagated to the signal S4 connected to the input of the scan flip-flop 5 at the first clock timing (A) of the test cycle, and “1” is propagated at the second clock timing (B). Can be verified when the target path transitions from '0' to '1'. That is, the replaced scan flip-flop can not only invert the output but also hold the output irrespective of the DataIn input or the ScanIn input value, and can create an arbitrary test pattern.

  FIG. 4 shows an example of a series of flow of this replacement operation on the assumption that a broadside delay test is performed.

  In FIG. 4, first, a net list of a circuit to be tested is read using a computer or the like, and a critical path or the like is analyzed using a static analysis tool or the like (L11). Next, a path to be subjected to a delay test is selected from the analysis result (L12). For example, only the path with the most critical timing is selected, or all possible paths are selected.

  Next, when the logical value that is the set value of the flip-flop that becomes the start point of the selected target path transitions from the first value to the second value, the transition propagates to the input of the flip-flop that becomes the end point of the target path A uniquely determined condition for setting is set for a net related to the flip-flop serving as the end point of the target path, and it is determined whether or not each condition has a collision or contradiction (L13). If there is a contradiction or collision, it means that the delay test pattern cannot be generated, and the delay test pattern for the target path cannot be generated (L20).

  If there is no contradiction or collision in L13, then the net value combination related to the flip-flop that is the end point of the target path is comprehensively determined, and the set value is determined so that there is no contradiction or collision with each other. It is determined whether or not it is possible (L14). When determining the setting value, it is not necessary to consider whether it can be generated logically. At this time, an arbitrary value may be determined. Also, if the settings cannot be made so that there is no contradiction or collision with each other, it is impossible to generate a delay test (L20).

  When the set value of the net related to the target path can be determined without contradiction or collision in L14, the value of the flip-flop corresponding to the start point of the net is also determined automatically. If the flip-flop is on the target path, the first and second values to be transitioned should be determined as values to be set, and the first value that is the same value for the flip-flops on the other paths And the second value should be the same value.

  Next, it is determined whether or not the determined setting value can be set for each scan flop flop (L15). In the broadside delay test, the first value can be set by scan-in in the scan cycle, so whether or not the second value can actually be set in the operation mode when the scan cycle is canceled. It becomes the judgment of. Specifically, in the circuit as shown in FIG. 7, for example, the scan flip-flops 6, 7 that affect the scan flip-flops 1, 2, 3, 4 whose values are to be set when creating the test pattern within one cycle. , 8 and 9 are scanned in and set to predetermined values, the scan mode is canceled, the clock is input once, the side scan mode is set, and the values of the scan flip-flops 1, 2, 3, and 4 are set. By observing after scanning out, it can be determined whether or not a predetermined value can be easily set in the scan flip-flops 1, 2, 3, and 4. If it is determined in L14 that an arbitrary value should be set, it is determined in this determination (L15) that setting is possible.

  Next, when the second value for generating the test pattern cannot be set in the target flip-flop, the flip-flop is an easily invertible or easy-to-hold scan flip-flop for performing another test. It is determined whether or not (L16). For example, if it is desired to set a hold value that does not change the first and second values, but the circuit has already been replaced with an easy-to-transition scan flip-flop to perform another test, the circuit Since it cannot be replaced, it is considered that the test pattern in the target path cannot be generated (L20).

  If the pattern has not yet been replaced in L16, then the test pattern composed of the first and second values is the holding pattern (the first and second values are the same value) or the transition pattern (first and second values). 2 is a different value) (L17), and in the case of the holding pattern, the flip-flop to be processed is replaced with the easy-to-hold scan flip-flop 202 (L19), and the transition pattern For example, the flip-flop to be processed is replaced with the easy inversion type scan flip-flop 201 (L18).

  Since the test pattern can be created by repeating the operations from L13 to L19 for all flip-flops related to the target path (L21), the scan flip-flop replaced with the created test pattern is used as part of the delay test information. Register (L22).

  If there are other paths to be tested, the same flow is repeated (L23). The test pattern of the delay test is completed by the above flow.

Next, a second embodiment of the present invention will be described. FIG. 5 is a circuit diagram of a holding / inverting mixed scan flip-flop 203, which is a modification of the present invention. The holding inversion mixed type scan flip-flop 203 is configured to output a general flip-flop 200 (scan flip-flop body) and an output (Q terminal signal) of the flip-flop 200 according to a selection signal (DelayTestMode terminal signal) for controlling selection. Or a selector 303 that selects and outputs either the data from the combinational circuit (DataIn terminal signal) or the inverted output (QB terminal signal) of the flip-flop 200, and can be easily inverted as shown in FIG. 1 is provided with both the function of the type scan flip-flop 201 and the function of the holding facilitation circuit 202 as shown in FIG. By using this circuit, the scan flip-flop can be configured to be easily held or inverted. The TestDelayMode signal may have a multi-bit configuration or a configuration that propagates information in a time division manner.

  FIG. 6 shows an example in which the scan flip-flops 1, 2, 3, 4 are all configured by the holding / inverting mixed scan flip-flop shown in FIG. In this case, the delay test controller 110 controls DelayTestMode1, DelayTestMode2, DelayTestMode3, and DelayTestMode4, which are 2-bit selection signals corresponding to the scan flip-flops 1, 2, 3, and 4, respectively. Note that the DataIn signals of the scan flip-flops 1, 2, 3, and 4 are omitted. Here, for example, when the delay test controller 110 is controlled so that the scan flip-flop 1 is set to the inversion easy configuration mode and the scan flip-flops 2, 3, 4 are set to the hold easy configuration mode, the target paths S1, S2, S3, S4 are changed. The delay test is possible, and the target paths S6, S3, and S4 can be subjected to the delay test by setting the scan flip-flop 3 in the easy inversion configuration mode and the scan flip-flops 1, 2, 3, and 4 in the easy maintenance configuration mode. Similarly, delay tests can be performed on the S5, S2, S3, S4 path, S7, S4 path, and the like.

  As described above, by selectively using the single hold / invert mixed scan flip-flop 203 in the easy hold circuit configuration mode or the easy reverse circuit configuration mode, selective replacement by static timing verification after layout ( L16) in FIG. 4 is not necessary, and even when there is a conflict with another test, the configuration is switched according to the target path to be tested, thereby detecting a delay fault of a plurality of paths (delay test) in the same circuit. ) Can be possible.

FIG. 3 is an easy-to-hold scan flip-flop circuit diagram of the present invention. It is an example of using the scan flip-flop of the present invention in a delay test. 3 is a timing chart of the delay test of FIG. It is a scan flip-flop replacement flowchart in the first embodiment. FIG. 7 is a circuit diagram of a holding and inverting mixed type scan flip-flop used in the second embodiment of the present invention. It is an example of a delay test using the holding inversion mixed type circuit of the second embodiment of the present invention. This is an example of a circuit that requires an appropriate logical value in a conventional delay test. This is an example of a circuit that cannot be tested in a conventional delay test. This is a general scan flip-flop. It is an example of an easy inversion type scan flip-flop used in the present invention. It is a timing chart which shows a general delay test. It is a scan flip-flop configuration setting flowchart in the second embodiment.

Explanation of symbols

1, 2, 3, 4, 5 Scan flip-flop 200 General scan flip-flop circuit 201 Invertible scan flip-flop circuit 202 Easy-to-hold scan flip-flop circuit 203 Invert-hold mixed scan flip-flop circuit

Claims (2)

A scan chain configured by a series connection circuit of a plurality of flip-flops for testing an internal circuit of an LSI composed of a logic circuit and operating as a shift register, inputs test scan test data and a clock in a test mode, This is a scan path test in which a logical operation is performed by an internal circuit and the internal circuit is confirmed to operate normally based on scanout result data that is the output of the operation result. In test design that performs the timing test of
A first step of extracting a signal propagation path to be tested;
A second flip-flop that influences propagation within one cycle of the clock input to the first flip-flop provided at the end point of the signal propagation path to be tested is replaced with a holding inversion mixed scan flip-flop. And the steps
A first value output by the second flip-flop that influences propagation within one cycle of the clock input to the first flip-flop, and two cycles of the two cycles. A third step of determining a second value to be output to the eye;
A fourth step of determining whether the first value and the second value are equal;
A fifth step of setting a mode in which the second flip-flop is used for the first mode when the determination results of the fourth step are equal, and for the second mode when they are different from each other ,
The holding inversion mixed scan flip-flop is
In the first mode, the value output from the output terminal is held and output in the previous cycle regardless of the input value from the input terminal, and in the second mode, the value input from the input terminal is related. A test design method characterized in that the value output from the output terminal is inverted and output in the previous cycle, and the input value from the input terminal is output in the third mode . The holding inversion mixed scan flip-flop is
The scan flip-flop body,
An input terminal, an output terminal connected to the output of the scan flip-flop body, and a selector;
The selector is
The normal output of the scan flip-flop body in the first mode is
In the second mode, the inverted output of the scan flip-flop body is
In the third mode, input from the input terminal
Select and output to each scan flip-flop body
The test design method according to claim 1, wherein a scan flip-flop is used.

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