JP4657678B2 - Phase-locked oscillator - Google Patents

Description

  The present invention relates to a phase-locked oscillator (PLL circuit), and particularly to a stable pull-in even in a configuration using a phase comparator that does not have a frequency comparison function for high-frequency operation, such as a local oscillator of a wireless transmission device. The present invention relates to a phase-locked oscillator capable of realizing characteristics.

  Among phase comparators used in phase-locked oscillators (PLL circuits), a phase comparator that does not have a frequency comparison function can perform phase comparison at high speed. And since direct phase comparison is performed, a phase difference between input and output can be suppressed, and a circuit used in a phase-locked oscillator used as a local oscillator of a radio transmission device of a high frequency band exceeding 10 GHz such as a microwave and a millimeter wave band. It is a configuration.

  FIG. 1 is a diagram illustrating a conventional configuration example of a phase-locked oscillator using a phase comparator that does not have a frequency comparison function. Since the phase comparator 1 that does not have a frequency comparison function operates at high speed, a circuit can be configured by direct phase comparison, and there is no phase delay factor such as frequency division. Can be suppressed. The output signal of the voltage controlled oscillator (VCO) 3 is phase-compared with the reference signal by the phase comparator 1. The error voltage generated there is fed back to the voltage controlled oscillator 3 via the loop filter circuit (LPF) 2.

  In the phase-locked oscillator shown in FIG. 1, since the phase comparator 1 does not have a frequency comparison function, a sweep circuit 4 is provided in order to realize frequency pulling, and the loop characteristic of the loop filter 2 is widened. The control voltage Vf of the voltage-controlled oscillator 3 is window-compared by the window comparator 5 to determine whether the control voltage Vf is within a predetermined voltage range (locked) (lock detect), and locked / unlocked state. Accordingly, the sweep circuit 4 is controlled.

Further, in Patent Document 1 below, in order to reduce the noise band and enable high-speed pull-in, a first PLL loop is formed using a PLL main body circuit at the time of frequency pull-in to an external input signal, and phase pull-in and steady-state A state in which a second PLL loop is formed using the PLL main circuit, and the control signal to the local oscillator obtained by the frequency pull-in is stored and held, and the effective free-running frequency of the local oscillator during the second PLL loop operation is set. A PLL circuit having a control circuit is disclosed.
JP-A-8-139598

  However, the phase-locked oscillator configured as shown in FIG. 1 has the following problems. First, in order to secure a frequency pull-in range, it is necessary to realize a wide band loop characteristic. However, the widening of the loop characteristic is limited to about several MHz. When the oscillation frequency becomes a high frequency (for example, 10 GHz or more), there is a problem that the frequency variable width of the voltage controlled oscillator (VCO) cannot be dealt with by widening the loop characteristics.

  Second, as a lock detect, the control voltage of the voltage controlled oscillator (VCO) is window-compared, and if it is within a certain range, it is determined that it is locked. In this way, when the frequency stability is low, the window range must be relatively wide, the entire window cannot be drawn, and the lock is released even if the control voltage is within the window. There is a problem that there exists a deadlock zone in the window where the phenomenon can occur.

  Third, for the frequency pull-in, the loop filter (LPF) sweeps the offset voltage to assist the pull-in. However, in order to operate the sweep circuit by the window comparator, the deadlock zone exists as described above. The problem of not locking occurs.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a phase-locked oscillator that can reliably pull in a frequency and can reliably detect a loss of lock when a phase comparator that does not have a frequency comparison function is used. .

In order to achieve the above object, a phase-locked oscillator according to the present invention includes a voltage-controlled oscillator that outputs a first frequency signal corresponding to a first control signal, and a phase difference between the first frequency signal and an external input signal. A first PLL circuit having a first phase comparator that outputs the first control signal based on the above, a fixed-frequency oscillator using a vibrator that outputs a predetermined frequency, and the voltage-controlled oscillator A second frequency comparison function that outputs a second control signal based on a frequency difference between a signal obtained by dividing the output first frequency signal and a second frequency signal from the fixed-frequency oscillator; and a phase comparator, said the second control signal, wherein the voltage controlled oscillator to output a second frequency signal, a second PLL circuit operating selectively with said first PLL circuit, unique Vibrator with frequency A voltage-controlled vibrator oscillator that uses and outputs a third frequency signal in accordance with the third control signal; a signal obtained by dividing the third frequency signal and the first frequency signal from the voltage-controlled oscillator; A third PLL circuit having a third phase comparator having a frequency comparison function for outputting a third control signal based on a frequency difference between the first control signal and a voltage corresponding to the third control signal within a predetermined range. In some cases, the first PLL circuit is operated by the first control signal, and the control circuit that operates the second PLL circuit by the second control signal when the predetermined range is exceeded. It is characterized by providing.

A preferred phase-locked oscillator according to the present invention includes a voltage-controlled oscillator that outputs a first frequency signal corresponding to an input control voltage, and a first that corresponds to a phase difference between the first frequency signal and an external input signal . A first PLL circuit including a first phase comparator that does not have a frequency comparison function that outputs a control signal, and a first filter that outputs a control voltage corresponding to the first control signal; A frequency difference between a fixed frequency oscillator using a vibrator that outputs a frequency, a signal obtained by dividing the first frequency signal from the voltage controlled oscillator, and a second frequency signal from the fixed frequency oscillator; a second phase comparator having a frequency comparison function of outputting a second control signal corresponding, a second PLL circuit and a second filter for outputting a control voltage in accordance with the second control signal , With natural frequency A voltage controlled oscillator oscillator for outputting a third frequency signal corresponding to the control voltage and the input using Doko, the third frequency signal and the first frequency signal division from the voltage controlled oscillator A third phase comparator having a frequency comparison function for outputting a third control signal corresponding to the frequency difference from the detected signal, and a third filter for outputting a control voltage corresponding to the third control signal. When the control voltage of the third PLL circuit provided and the third filter is within a predetermined range, the control voltage of the first filter is input to the voltage controlled oscillator, and when the voltage exceeds the predetermined range, And a control circuit for inputting the control voltage of the second filter to the voltage controlled oscillator.

  In the above configuration, for example, the fixed-frequency oscillator of the second PLL circuit includes a reference voltage generator that generates a predetermined reference voltage and the voltage-controlled oscillator oscillator of the third PLL circuit. When a voltage is supplied to the voltage controlled oscillator of the third PLL circuit, a frequency signal from the voltage controlled oscillator is input to the second phase comparator, and the control circuit Depending on the three control voltages, either the reference voltage or the control voltage of the third filter is switched and input to the voltage controlled oscillator oscillator.

  In the above configuration, for example, the second phase comparator of the second PLL circuit and the third phase comparator of the third PLL circuit are configured as the same shared phase comparator and controlled. The circuit switches and inputs the control signal from the shared phase comparator to either the second filter or the third filter in accordance with the control voltage of the third filter.

  In the above configuration, for example, the second phase comparator of the second PLL circuit and the third phase comparator of the third PLL circuit are configured as the same shared phase comparator, The second filter of the second PLL circuit and the third filter of the third PLL circuit are configured as the same shared filter, and the control circuit uses the control voltage of the third filter. In response, the control voltage from the shared filter is switched and input to either the voltage-controlled oscillator or the voltage-controlled oscillator.

  In the above configuration, the loop constant of the first filter may be switched, and the control circuit may switch the loop constant according to the control voltage of the third filter.

In the above configuration, it is preferable that the control circuit does not respond to an input change to the control circuit for a predetermined time after switching the control voltage input to the voltage controlled oscillator .

  According to the phase-locked oscillator of the present invention, when the input signal is a high-frequency signal (for example, a frequency exceeding 10 GHz) and the phase comparator to which the high-frequency signal is input does not have a frequency comparison function, reliable frequency pull-in is achieved. Is possible. In addition, the unlocked state (unlocked) can be reliably detected.

  Embodiments of the present invention will be described below with reference to the drawings. However, such an embodiment does not limit the technical scope of the present invention.

  FIG. 2 is a diagram illustrating a first configuration example of the phase-locked oscillator according to the embodiment of the present invention. In FIG. 2, the phase-locked oscillator includes a main PLL circuit 10, a starter PLL circuit 20, a qualify PLL circuit 30, and a control circuit 40. The main PLL circuit 10 includes a phase comparator 11 to which an external input signal is input, a loop filter (LPF) 12, and a voltage controlled oscillator (VCO) 16, and shares a voltage controlled oscillator with the starter PLL circuit 20. In addition, a switch (SW) 14 and a switching buffer circuit 15 are inserted between the loop filter 12 and the voltage controlled oscillator 16. The phase comparator 11 does not have a frequency comparison function. In the present specification, a component having a function of comparing both the phase and the frequency may be simply referred to as a phase comparator. The loop filter (LPF) 12 includes a loop constant switching circuit 13 that controls the loop constant.

  The starter PLL circuit 20 is a PLL circuit for locking when the main PLL circuit 10 is unlocked, and includes a fixed frequency oscillator (XO) 21 using a crystal resonator having a high-accuracy natural frequency, a frequency A frequency phase comparator 22 having a comparison function, a loop filter (LPF) 23, and a voltage controlled oscillator (VCO) 16 are included. As described above, the switch (SW) 24 is provided between the loop filter 23 and the voltage controlled oscillator 16 in order to share the voltage controlled oscillator 16 with the main PLL circuit 10. The switching buffer circuit 15 is also shared. Not only the crystal resonator but also a resonator having another natural frequency with high accuracy such as a ceramic resonator may be used.

  When the control circuit 40 selectively switches the switch 14 and the switch 24, either the main PLL circuit 10 or the starter PLL circuit 20 is selected, and the control voltage supplied to the voltage controlled oscillator 16 is switched.

  During operation of the starter PLL circuit 20, the output signal from the voltage controlled oscillator 16 is divided by the frequency divider 25 and input to the frequency phase comparator 22. The frequency phase comparator 22 is supplied with a stable and highly accurate frequency from a fixed-frequency oscillator 21 using a crystal resonator. Therefore, the voltage-controlled oscillator 16 is connected to the fixed-frequency oscillator 21 using a crystal resonator. Can be synchronized.

  The qualify PLL circuit 30 is a PLL circuit for monitoring whether the main PLL circuit 10 is locked, and is a voltage control using a frequency phase comparator 31 having a frequency comparison function, a loop filter 32, and a crystal resonator. A crystal oscillator (VCXO) 33, a frequency divider 34, and a window comparator 35 are included. The voltage-controlled crystal oscillator 33 using a crystal resonator has a more stable oscillation frequency than that of a voltage-controlled oscillator using, for example, a microwave band stripline resonator or a dielectric resonator, and the control voltage is applied to the window comparator. In this case, a highly accurate frequency difference on the order of ppm can be detected. Not only a crystal resonator, but also a voltage-controlled resonator oscillator using a resonator having another natural frequency with high accuracy, such as a ceramic resonator.

  The frequency phase comparator 31 of the qualify PLL circuit 30 compares the frequency of the output signal from the voltage controlled oscillator 16 during operation of the main PLL circuit 10 with the frequency of the output signal from the voltage controlled crystal oscillator 33 of the qualify PLL circuit. A control voltage corresponding to the difference is output. Since the voltage-controlled crystal oscillator 33 of the qualify PLL circuit 30 oscillates at a stable natural frequency as described above, the voltage control of the main PLL circuit 10 can be performed by window-comparing the control voltage if this is used as a reference frequency. The locked / unlocked state of the oscillator 16 can be monitored. That is, if the window comparator (WC) 35 determines that the control voltage is within the predetermined range, the voltage-controlled oscillator 16 of the main PLL circuit 10 is in the locked state, and if it exceeds the predetermined range, it is unlocked. You can see that it is in a state. The predetermined range of the control voltage monitored by the window comparator 35 is set to a range narrower than the control voltage variable range of the frequency phase comparator 31.

  An output signal of the window comparator 35 is input to the control circuit 40. When the control circuit 40 determines that the main PLL circuit 10 is in the unlocked state, the control circuit 40 connects the switch 24 and operates the starter PLL circuit 20. As described above, since the starter PLL circuit 20 uses the fixed-frequency oscillator 21 using a crystal resonator, the voltage-controlled oscillator 16 can be easily locked, and the unlocked state is returned to the locked state. Can do.

  The control circuit 40 connects the switch 14 (by disconnecting the switch 24) when the voltage controlled oscillator 16 is locked. When the switch 14 is connected, the voltage controlled oscillator 16 is locked to the same frequency as the frequency of the input signal, so that the main PLL circuit 10 can reliably pull in the frequency of the input signal. Since the lock state of the main PLL circuit is constantly monitored by the qualify PLL circuit 30, the starter PLL circuit 20 is switched to lock the voltage-controlled oscillator 16 as described above even if the lock state is set to the unlock state. Thus, the main PLL circuit can be reliably returned to the locked state.

  Thus, the phase-locked oscillator according to the embodiment of the present invention oscillates based on the phase comparator 11 that detects the phase difference between the input signal from the outside and the output signal from the voltage-controlled oscillator, and the phase difference. In addition to the main PLL circuit 10 having the voltage-controlled oscillator 16 whose frequency is controlled, the voltage-controlled oscillator 16 operates in a switchable manner with the main PLL circuit, and synchronizes the voltage-controlled oscillator 16 with a fixed-frequency oscillator using a vibrator having a natural frequency. And a qualify PLL circuit 30 for accurately monitoring the frequency from the voltage controlled oscillator 16, and the control circuit 40 is controlled by the qualify PLL circuit 30 according to the frequency (output of the window comparator 35). It is configured to select and operate either the main PLL circuit 10 or the starter PLL circuit 20 That. Specifically, if the frequency monitored by the qualify PLL circuit 30 is out of a predetermined range, it is determined to be in the unlocked state, and if the starter PLL circuit 20 operates and is within the predetermined range, it is in the locked state. And the main PLL circuit 10 is operated. The operation of the phase locked oscillator shown in FIG. 2 will be described in more detail.

  FIG. 3 is a timing chart of the phase-locked oscillator shown in FIG. If the main PLL circuit 10 is in a locked state with respect to the input signal, the output of the window comparator 35 maintains the H level (FIG. 3 (1)). If the unlocked state is caused for some reason, the control voltage acquired by the window comparator 35 deviates from the predetermined range, and the output of the window comparator 35 changes to the L level (FIG. 3 (2)). The frequency comparator 31 of the qualify PLL circuit 30 also determines the locked / unlocked state based on whether the phase difference is within the variable range of the control voltage, and outputs a lock detect signal (LD31) corresponding to the determination result. However, as described above, since the predetermined range of the control voltage monitored by the window comparator (WC) 35 is narrower than the variable range of the control voltage, the window comparator 35 is in the case where the phase is synchronized but the frequency drifts. The frequency phase comparator 31 detects the unlocked state later (FIG. 3 (3)). The control circuit 40 determines that the main PLL circuit 10 is in the unlocked state when either the window comparator 35 or the frequency phase comparator 31 detects the unlocked state.

  Therefore, when the window comparator 35 detects the unlocked state (FIG. 3 (2)), the state changes (FIG. 3 (4)), and the control circuit 40 switches from the switch 14 to the switch 24 (FIG. 3). 3 (5)). That is, the switch 14 of the main PLL circuit 10 is disconnected and the starter PLL circuit 20 is activated.

  Further, the control circuit 40 is masked at the same time when the starter PLL circuit 20 is activated (FIG. 3 (6)). The frequency phase comparator 22 of the starter PLL circuit 20 locks depending on whether or not the lock detect signal (phase difference is in the variable range of the control voltage) output during the lock pull-in process because the output control voltage greatly fluctuates. The signal for determining the unlocked state (LD22) also varies (FIG. 3 (7)). Therefore, in order to prevent the control circuit 40 from detecting the unlocked state in the lock pull-in process, the signals from the frequency phase comparators 22 and 31 and the window comparator 35 are used for a predetermined period necessary for the starter PLL circuit 20 to lock. Masked to not respond. Specifically, the control circuit 40 includes a timer circuit, and prevents the starter PLL circuit 20 from operating for a predetermined period after the starter PLL circuit 20 is activated.

  After the mask is removed (after the predetermined period has elapsed), when the control circuit 40 detects the locked state of the starter PLL circuit 20 (FIG. 3 (8)), the switch 24 is switched to the switch 14 (FIG. 3 (9)). The main PLL circuit 10 is operated. If the starter PLL circuit 20 is not locked, the switch is not switched, and the control circuit 40 is masked again, and detects the locked state of the starter PLL circuit 20 after a predetermined period.

  When switched to the main PLL circuit 10, the main PLL circuit 10 starts lock pull-in. At this time, the control circuit 40 is masked again (FIG. 3 (10)). This is because the qualify PLL circuit 30 also performs the lock pull-in operation during the lock pull-in of the main PLL circuit 10 and does not respond to the fluctuation of the control voltage in this process.

  Further, in the lock pull-in process in the main PLL circuit 10, the loop constant of the loop filter 12 is switched by the loop constant switching circuit 13 to facilitate locking (FIG. 3 (11)). Specifically, the loop constant is switched so that the band of the loop filter 12 is expanded only during the pull-in period.

  After the mask is removed (after the predetermined period has elapsed) (FIG. 3 (12)), the control circuit 40 detects the locked state of the qualify PLL circuit 30. That is, if both the output signal of the window comparator 35 and the lock detect signal of the frequency phase comparator 31 indicate the locked state, it is determined that the main PLL circuit 10 is also locked at the predetermined frequency, and phase synchronization is completed (FIG. 3 (13 )). If either signal is unlocked, the process returns to the beginning, the switch is switched, and the lock pull-in operation by the starter PLL circuit 20 is performed again.

  By performing the operation as described above, even if the phase comparator 11 of the main PLL circuit 10 does not have a frequency comparison function, the frequency pull-in can be reliably performed by providing the starter PLL circuit 20. .

  That is, when the starter PLL circuit 20 is switched to the starter PLL circuit 20 by using a fixed-frequency oscillator using a crystal oscillator with high accuracy in the starter PLL circuit 20 as a reference signal, the voltage controlled oscillator 16 of the main PLL circuit 10 is previously connected to the crystal. It is possible to synchronize with a center frequency of a fixed frequency oscillator using the vibrator. Thereafter, when the operation is switched to the main PLL circuit 10, the loop filter 12 of the main PLL circuit 10 causes the total deviation given by the frequency deviation of the input signal and the frequency deviation of the fixed frequency oscillator using the crystal resonator. A corresponding beat signal is output. Conventionally, the bandwidth of the loop filter has been designed to be as wide as possible. However, in this embodiment, it is sufficient to design the loop filter characteristics so as to clear the maximum value of the total deviation, and the frequency can be reliably pulled in. It is possible to generate a beat signal (control voltage swell) within a range that can be generated.

  The control circuit 40 switches to the main PLL circuit 10 when the voltage-controlled oscillator 16 of the main PLL circuit 10 is locked by the starter PLL circuit 20. At this time, by determining the lock state based on the lock detect signal of the starter PLL circuit 20, switching from the starter PLL circuit 20 to the main PLL circuit 10 can be performed reliably.

  Further, the starter PLL circuit 20 is switched to the main PLL circuit 10, and the loop constant of the loop filter 12 of the main PLL circuit 10 is changed in the pull-in process of the main PLL circuit 10. That is, the bandwidth is expanded from the locked state. This is because pull-in is performed within the phase error voltage range of the phase comparator 16 regardless of the conditions (resistance ratio, capacitor potential difference) of the loop filter 12 that generates the beat signal and the control voltage. By widening the band of the loop filter 12 at the time of pulling in, reliable frequency pulling becomes possible.

  Further, regarding the problem of the existence of the deadlock zone in the related art, it is possible to reliably detect the frequency by providing the qualify PLL circuit 30.

  That is, in the qualify PLL circuit 30, by using the voltage controlled crystal oscillator 33 with high frequency stability using a crystal resonator of several MHz to several tens of MHz, the control voltage can be window-compared in ppm order. The frequency can be detected with high accuracy. Even in the case where the frequency stability of the voltage controlled oscillator 16 of the main PLL circuit is relatively low, the control PLL window 30 can set the window range of the control voltage to be relatively narrow. It is possible to detect the unlocked state.

  Further, by using the lock detect signal of the qualify PLL circuit 30 and the output signal of the window comparator 35 for the lock / unlock determination of the main PLL circuit 30, the lock / unlock is determined with high accuracy and the unlock state is established. In this case, the main PLL circuit 10 can be switched to the starter PLL circuit 20 with certainty.

  FIG. 4 is a diagram illustrating a second configuration example of the phase-locked oscillator according to the embodiment of the present invention. The second configuration example of FIG. 4 is different from the first configuration example of FIG. 2 in that a fixed-frequency oscillator 21 using a crystal resonator of the starter PLL circuit 20 is replaced with a voltage-controlled crystal oscillator of the qualify PLL circuit 30. The configuration is shared with 33. As described above, the voltage controlled crystal oscillator 33 of the qualify PLL circuit 30 is a highly accurate oscillator using a crystal resonator, and a fixed reference voltage is supplied from the reference voltage generator 27 to the voltage controlled crystal oscillator 33. By doing so, it becomes possible to output a signal with a stable frequency, and a function equivalent to that of the fixed-frequency oscillator 21 using a crystal resonator is realized. In order to share the voltage control crystal oscillator 33 between the qualify PLL circuit 30 and the starter PLL circuit, a switch 26 and a switch 36 are provided in front of the voltage control crystal oscillator 33, respectively, and are switched by the control of the control circuit 40. It is done. In the switch switching, the switch 26 is connected when the starter PLL circuit 20 is activated in accordance with the operation of FIG. 3 described above, and the switch 36 is connected when the operation of the starter PLL circuit 20 is completed.

  FIG. 5 is a diagram showing a third configuration example of the phase-locked oscillator according to the embodiment of the present invention. Compared with the second configuration example of FIG. 4, the third configuration example of FIG. 5 further shares the frequency phase comparator 22 of the starter PLL circuit 20 with the frequency phase comparator 31 of the qualify PLL circuit 30. It is a configuration. In order to share the frequency phase comparator 31, the output of the frequency phase comparator 31 is branched into two, and a switch 27, and a switch 27, are provided in front of each of the loop filter 23 of the starter PLL circuit 20 and the loop filter 32 of the qualify PLL circuit. 37 is provided. The switches 27 and 37 are also switched by the control of the control circuit 40. Similarly to the second configuration example, the switch switching is performed when the starter PLL circuit 20 is activated in accordance with the operation of FIG. When the switch 27 is connected and the operation of the starter PLL circuit 20 is completed, the switch 37 is connected.

  FIG. 6 is a diagram illustrating a fourth configuration example of the phase-locked oscillator according to the embodiment of the present invention. The fourth configuration example of FIG. 6 is further configured to share the loop filter 23 of the starter PLL circuit 20 with the loop filter 32 of the qualify PLL circuit 30 as compared to the third configuration example of FIG. is there. In order to share the loop filter 32, the output of the frequency phase comparator 31 is branched into two, and switches 28, 38 are further provided in front of the loop filter 23 of the starter PLL circuit 20 and the loop filter 32 of the qualify PLL circuit 30, respectively. Is provided. The switches 28 and 38 are also switched by the control of the control circuit 40. Similarly to the second configuration example, the switch switching is performed when the starter PLL circuit 20 is activated in accordance with the operation of FIG. When the switch 28 is connected and the operation of the starter PLL circuit 20 is completed, the switch 38 is connected.

(Appendix 1)
A first PLL circuit having a phase comparator that detects a phase difference between an external input signal and an output signal from the voltage controlled oscillator, and a voltage controlled oscillator in which an oscillation frequency is controlled based on the phase difference;
A second PLL circuit that operates in a switchable manner with the first PLL circuit and synchronizes the voltage-controlled oscillator to a fixed frequency oscillator using a vibrator having a natural frequency;
A third PLL circuit for monitoring the frequency from the voltage controlled oscillator;
A phase-locked oscillator comprising: a control circuit that selects and operates either the first PLL circuit or the second PLL circuit according to a frequency monitored by the third PLL circuit .

(Appendix 2)
A voltage-controlled oscillator that outputs a frequency signal according to an input control voltage, and a first phase comparator that does not have a frequency comparison function that outputs a control signal according to the phase difference between the frequency signal and an external input signal And a first PLL circuit comprising a first filter that outputs a control voltage according to the control signal,
A fixed-frequency oscillator using a vibrator that outputs a predetermined frequency, and a control signal corresponding to a phase difference between a signal obtained by dividing the frequency signal from the voltage-controlled oscillator and the frequency signal from the fixed-frequency oscillator A second PLL circuit comprising: a second phase comparator that outputs a second filter that outputs a control voltage in accordance with the control signal;
A voltage-controlled vibrator oscillator that uses a vibrator having a natural frequency and outputs a frequency signal in accordance with an input control voltage, and the frequency signal and a signal obtained by dividing the frequency signal from the voltage-controlled oscillator. A third PLL circuit including a third phase comparator that outputs a control signal according to the phase difference, and a third filter that outputs a control voltage according to the control signal;
A control circuit that switches between the control voltage of the first filter and the control voltage of the second filter in accordance with the control voltage of the third filter and inputs the control voltage to the voltage controlled oscillator. A featured phase-locked oscillator.

(Appendix 3)
In Appendix 2,
The fixed-frequency oscillator using the vibrator of the second PLL circuit includes a reference voltage generator that generates a predetermined reference voltage and the voltage-controlled vibrator oscillator of the third PLL circuit. When a voltage is supplied to the voltage controlled oscillator of the third PLL circuit, a frequency signal from the voltage controlled oscillator is input to the second phase comparator,
The control circuit switches either the reference voltage or the control voltage of the third filter in accordance with the third control voltage, and inputs it to the voltage controlled oscillator oscillator. Oscillator.

(Appendix 4)
In Appendix 2 or 3,
The second phase comparator of the second PLL circuit and the third phase comparator of the third PLL circuit are configured as the same shared phase comparator;
The control circuit switches and inputs a control signal from the shared phase comparator to either the second filter or the third filter in accordance with a control voltage of the third filter. A phase-locked oscillator.

(Appendix 5)
In Appendix 2 or 3,
The second phase comparator of the second PLL circuit and the third phase comparator of the third PLL circuit are configured as the same shared phase comparator;
Furthermore, the second filter of the second PLL circuit and the third filter of the third PLL circuit are configured as the same shared filter,
The control circuit switches and inputs a control voltage from the shared filter to either the voltage controlled oscillator oscillator or the voltage controlled oscillator in accordance with a control voltage of the third filter. Synchronous oscillator.

(Appendix 6)
In any of Supplementary Notes 2 to 5,
The loop constant of the first filter is switchable,
The control circuit switches the loop constant according to a control voltage of the third filter.

(Appendix 7)
In any of Supplementary Notes 2 to 6,
The phase-locked oscillator is characterized in that the control circuit does not respond to a change in the input to the control circuit for a predetermined time after each switching.

(Appendix 8)
In claim 2,
When the control circuit determines that the control voltage of the third filter is outside a predetermined range, the control circuit inputs the control voltage input to the voltage controlled oscillator from the control voltage of the first filter. Switch to voltage,
When the lock state of the second PLL circuit is detected, the control voltage input to the voltage controlled oscillator is switched from the control voltage of the second filter to the control voltage of the first filter. Oscillator.

It is a figure which shows the example of a conventional structure of the phase locked oscillator using the phase comparator which does not have a frequency comparison function. It is a figure which shows the 1st structural example of the phase-locked oscillator in embodiment of this invention. 3 is a timing chart of the phase-locked oscillator of FIG. It is a figure which shows the 2nd structural example of the phase locked oscillator in embodiment of this invention. It is a figure which shows the 3rd structural example of the phase locked oscillator in embodiment of this invention. It is a figure which shows the 4th structural example of the phase locked oscillator in embodiment of this invention.

Explanation of symbols

  10: main PLL circuit, 11: phase comparator, 12: loop filter, 13: loop constant switching circuit, 14: switch, 15: switching buffer circuit, 16: voltage controlled oscillator, 20: starter PLL circuit, 21: crystal oscillation Fixed frequency oscillator using a child, 22: frequency phase comparator, 23: loop filter, 24: switch, 25: frequency divider, 26: switch, 27: reference voltage generator, 28: switch, 30: qualify PLL Circuit: 31: Frequency phase comparator, 32: Loop filter, 33: Voltage controlled crystal oscillator, 34: Frequency divider, 35: Window comparator, 36: Switch, 37: Switch, 38: Switch, 40: Control circuit

Claims (4)

A voltage controlled oscillator that outputs a first frequency signal corresponding to the first control signal; and a first control signal that outputs the first control signal based on a phase difference between the first frequency signal and an external input signal. A first PLL circuit having a phase comparator ;
A fixed frequency oscillator using a vibrator that outputs a predetermined frequency, a signal obtained by dividing the first frequency signal output from the voltage controlled oscillator, and a second frequency signal from the fixed frequency oscillator; And a second phase comparator having a frequency comparison function for outputting a second control signal based on the frequency difference of the output, and outputting the second frequency signal from the voltage controlled oscillator by the second control signal A second PLL circuit selectively operating with the first PLL circuit;
A voltage controlled oscillator using a vibrator having a natural frequency and outputting a third frequency signal according to a third control signal; and the first frequency from the third frequency signal and the voltage controlled oscillator A third PLL circuit having a third phase comparator having a frequency comparison function for outputting a third control signal based on a frequency difference from a signal obtained by frequency division of the signal ;
When the voltage according to the third control signal is within a predetermined range, the first PLL signal is operated by the first control signal, and when the voltage exceeds the predetermined range, the second control And a control circuit for operating the second PLL circuit by a signal . A voltage-controlled oscillator that outputs a first frequency signal according to an input control voltage, and a frequency comparison function that outputs a first control signal according to a phase difference between the first frequency signal and an external input signal. A first PLL circuit comprising a first phase comparator that does not have and a first filter that outputs a control voltage in accordance with the first control signal;
A frequency of a fixed frequency oscillator using a vibrator that outputs a predetermined frequency, a frequency obtained by dividing the first frequency signal from the voltage controlled oscillator, and a second frequency signal from the fixed frequency oscillator A second PLL comprising a second phase comparator having a frequency comparison function for outputting a second control signal according to the difference, and a second filter for outputting a control voltage according to the second control signal Circuit,
A voltage-controlled vibrator oscillator that uses a vibrator having a natural frequency and outputs a third frequency signal corresponding to the input control voltage; and the first frequency from the third frequency signal and the voltage-controlled oscillator A third phase comparator having a frequency comparison function for outputting a third control signal corresponding to a frequency difference from the signal obtained by frequency division, and a third phase for outputting a control voltage corresponding to the third control signal. A third PLL circuit comprising:
When the control voltage of the third filter is within a predetermined range, the control voltage of the first filter is input to the voltage controlled oscillator. When the control voltage exceeds the predetermined range, the control voltage of the second filter is And a control circuit for inputting to the voltage controlled oscillator. In claim 2,
The loop constant of the first filter is switchable,
The phase locked oscillator according to claim 1, wherein the control circuit switches the loop constant in accordance with a control voltage of the third filter. In claim 2,
The phase-locked oscillator characterized in that the control circuit does not respond to a change in the input to the control circuit for a predetermined time after switching the control voltage input to the voltage-controlled oscillator.

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