JP4658755B2 - Solid-state imaging device and driving method thereof - Google Patents

Description

  The present invention relates to a solid-state imaging device that uses a photoelectric conversion characteristic (logarithmic characteristic) after saturation of a photodiode to increase the dynamic range and a driving method thereof.

  The relationship between the amount of incident light and the output voltage (photoelectric conversion characteristics) in a photodiode with a vertical overflow drain structure is linear in a low-light environment where the charge accumulated in the photodiode exceeds the barrier of the vertical overflow drain. However, in a high illuminance environment where the amount of incident light becomes very large and the charge accumulated in the photodiode exceeds the barrier of the vertical overflow drain, the logarithmic characteristic is non-linear.

  Solid-state imaging devices used in video cameras, digital still cameras, and the like are usually targeted for processing in low-light environments where the relationship between incident light intensity and output voltage is a linear characteristic. A solid-state imaging device that expands the dynamic range using conversion characteristics (logarithmic characteristics) has been proposed (for example, Patent Document 1).

  In other words, in Patent Document 1, the vertical overflow drain barrier (boundary point between the linear characteristic portion and the logarithmic characteristic portion) is set lower than that of a normal solid-state imaging device using only the linear characteristics, so that the accumulated charges are vertically overflowed. By making it easy to cross the drain barrier so that the logarithmic characteristics can be obtained early and the logarithmic characteristic part is within the operating range of the subsequent circuit that amplifies the imaging signal and outputs it to the outside, only the linear characteristics The dynamic range can be expanded as compared with a solid-state imaging device having

JP 2001-94880 A

  However, there is a case where a large gain is applied to a readout circuit that amplifies a signal picked up at a subsequent stage and outputs the amplified signal to the outside. In that case, in the above-described conventional technique, the boundary point between the linear characteristic portion and the logarithmic characteristic portion is fixed in a state set lower than that of the solid-state imaging device having only the linear characteristic, and thus a large gain is applied to the readout circuit provided in the subsequent stage. , The logarithmic characteristic portion deviates from the operation range of the subsequent circuit, and only the signal in the linear characteristic portion appears in the output of the subsequent circuit. In other words, the above conventional technique has a problem that when a large gain is applied in the subsequent circuit, the dynamic range is significantly lowered as compared with a normal solid-state imaging device having only linear characteristics.

  The present invention has been made in view of the above, and in the case of expanding the dynamic range using photoelectric conversion characteristics (logarithmic characteristics) after saturation of the photodiode, the logarithm is changed even if the gain of the readout circuit in the subsequent stage is changed. An object of the present invention is to obtain a solid-state imaging device and a driving method thereof in which the characteristic portion can be accommodated within the operation range of the subsequent circuit.

In order to achieve the above-described object, the present invention is necessary for the photodiode to store electric charge during an off operation between the photodiode that performs photoelectric conversion and the floating diffusion that temporarily holds electric charge. A pixel array in which a pixel circuit of a MOS structure in which a charge transfer transistor for forming a potential barrier and transferring a charge accumulated in the photodiode to the floating diffusion is turned on at the time of ON operation is arranged in a matrix, and pixels in each row in the pixel array A row control circuit comprising: a row control circuit that controls charge accumulation and readout in a circuit; and a readout circuit that amplifies a signal from the pixel array to a set gain value and outputs the amplified signal to the outside of the chip. The charge transfer transistor is turned on and off in The drive buffer for outputting a level signal of two values for driving on the state, the side levels of driving the charge transfer transistor off operating state of the level signal of the two values corresponding to the voltage value applied to the control terminal A drive buffer with a control terminal that can change the potential of the signal, and a gain value set in the readout circuit, and when the readout circuit operates with the gain value, the break potential of the photoelectric conversion characteristic of the photodiode is A relation table for associating with the off-potential control value of the charge transfer transistor so as to be within the operation range of the readout circuit, and when the gain value is input from the outside, the off-potential control corresponding from the relation table The off potential control value output circuit for extracting the value and the off potential control value output by the off potential control value output circuit are shown. A variable voltage source that applies a voltage value for turning off the charge transfer transistor to a control terminal of the drive buffer, and a potential of a level signal on the side that drives the charge transfer transistor to the off operation state is applied to the drive buffer. The voltage value applied to the control terminal is held .

  According to the present invention, the height of the potential barrier formed by the charge transfer transistor between the photodiode and the floating diffusion is lowered when the gain value set in the readout circuit is large, and is increased when the gain value is small. The potential at the boundary point (break point) between the linear characteristic portion and the logarithmic characteristic portion in the photoelectric conversion characteristic of the diode can be made to fall within the operation range of the readout circuit.

  According to the present invention, since the logarithmic characteristic portion can be kept within the operation range of the subsequent circuit even if the gain of the subsequent read circuit is changed, the dynamic range can be expanded regardless of the magnitude of the gain applied to the subsequent circuit. There is an effect that can be.

  Exemplary embodiments of a solid-state imaging device and a driving method thereof according to the present invention will be described below in detail with reference to the drawings.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing a configuration of a solid-state imaging device according to Embodiment 1 of the present invention. In FIG. 1, a solid-state imaging device 1a has, as an element related to the present invention, a pixel in which a plurality of pixel structures 2 in which a plurality of pixel circuits (hereinafter simply referred to as “pixels”) are arranged in the column direction are arranged in the row direction. Charge signals from the array, the scanner 3 and the buffer circuit 4, which are row control circuits that perform scanning control in the column direction with a group of pixels in the row direction of the pixel array, and the pixel structure 2 in each column appearing in the readout line 5 Is related to the gain value for setting the potential at the boundary point between the linear characteristic portion and the logarithmic characteristic portion of the photoelectric conversion characteristic to the AGC circuit 6. First, the gain register 7, the sequencer 8, the off-potential register 9, and the buffer that has the variable voltage source 10 connected to the input terminal, which constitute a control circuit that adjusts to a substantially constant value within the operating range. And a flop 11.

  The pixel structure 2 in one column includes a plurality of pixels 21 arranged in the column direction and a sample / hold circuit (S / H) 23 to which a charge signal appearing on an output line 22 that connects each output terminal of the plurality of pixels 21 is input. And a switch 24 interposed between the output terminal of the S / H 23 and the readout line 5, and a current source 25 interposed between the output line 22 and the ground.

  The pixel 21 is an integrated circuit having a MOS structure, and an equivalent circuit thereof includes a photodiode 30 whose anode is grounded, and NMOS transistors 32 and 33 arranged in series between the cathode of the photodiode 30 and a power supply 31. And NMOS transistors 34 and 35 arranged in series between the power supply 31 and the output line 22. A floating diffusion is formed at the serial connection end 36 of the NMOS transistors 32 and 33.

  In this configuration, the NMOS transistor 32 having the other signal electrode connected to the cathode of the photodiode 30 functions as a charge transfer transistor for transferring and temporarily storing the charge accumulated by the photoelectric conversion of the photodiode 30 to the floating diffusion 36. To do. Further, the NMOS transistor 33 whose other signal electrode is connected to the power supply 31 functions as a reset transistor that removes charges from the floating diffusion 36 and the photodiode 30 and resets them to a predetermined potential. Further, the NMOS transistor 34 whose other signal electrode is connected to the power supply 31 functions as an amplification transistor whose gate electrode is connected to the floating diffusion 36 and outputs a signal corresponding to the electric charge accumulated in the floating diffusion 36. The NMOS transistor 35 having the other signal electrode connected to the output line 22 functions as a read selection transistor that selects and reads the charge signal amplified by the amplification transistor 34.

  The buffer circuit 4 is essentially a part of the scanning signal output circuit built in the output side of the scanner 3, but in FIG. 1, it is extracted and placed between the output end of the scanner 3 and the pixel structure 2 in each column. As arranged in. This buffer circuit 4 includes a plurality of drive buffer groups 40 arranged in a one-to-one relationship with each pixel 21 in each column of pixel structures 2. Each drive buffer group 40 includes three drive buffers 45, 46, and 57, respectively. That is, the scanner 3 outputs three types of scanning signals for each row. Since the output of the scanner 3 is a binary level signal, the outputs of the three drive buffers 45, 46 and 57 are also binary level signals, but the output of the drive buffer 45 is applied to the gate electrode of the reset transistor 33. The output of the drive buffer 46 is applied to the gate electrode of the charge transfer transistor 32, and the output of the drive buffer 47 is applied to the gate electrode of the read selection transistor 35.

  Here, referring to FIG. 2 to FIG. 4, when the pixel 21 is read out in a configuration excluding the control circuit (gain register 7, sequencer 8, off potential register 9, variable voltage source 10, and buffer amplifier 11). The operation will be described.

  FIG. 2 is a diagram for explaining general photoelectric conversion characteristics (conventional photoelectric conversion characteristics) of a pixel. In FIG. 2, the horizontal axis represents the illuminance expressed on a logarithmic scale, and the vertical axis represents the output potential expressed on a linear scale. FIG. 3 is a diagram for explaining the relationship between the elements related to charge accumulation in the pixel and the potential potential. In FIG. 3, a reset transistor 33 on the power supply 31 side, a floating diffusion (FD) 36, a charge transfer transistor 32, and a photodiode (PD) 30 are shown as elements related to charge accumulation in the pixel 21. The photodiode 30 has a shallow potential well, while the floating diffusion 36 has a deep potential well. The potential potential of the charge transfer transistor 32 interposed between them (the potential during the off operation) forms a potential barrier corresponding to the barrier of the vertical overflow drain described in the background art.

  2 and 3, the photoelectric conversion characteristic of the photodiode 30 is a linear characteristic 50 in a low illuminance environment until the charge accumulated in the photodiode 30 exceeds the potential potential of the charge transfer transistor 32. In a high illumination environment where the charge accumulated in the photodiode 30 exceeds the potential potential of the charge transfer transistor 32, the point when the potential potential of the charge transfer transistor 32 exceeds the boundary point (break point) 51 Thereafter, the non-linear logarithmic characteristic 51 is obtained.

  Next, FIG. 4 is a sequence diagram for explaining a change in potential potential at the time of reading. In FIG. 4, (1) in a pixel where charge accumulation is not controlled, the floating diffusion 36 and the photodiode 30 are in a state where charges exist. Normal pixel readout is performed as follows. (2) First, in order to reset the photodiode 30, the charge transfer transistor 32 and the reset transistor 33 are set to the ON operation state, and the charge of the photodiode 30 is extracted. (3) Next, the charge transfer transistor 32 and the reset transistor 33 are set to an off operation state, and charge accumulation is started.

  (4a) In a low illuminance environment, all the electric charges photoelectrically converted by the photodiode 30 are stored in the photodiode 30, so that the potential change of the photodiode 30 is linear with respect to the illuminance 50 (see FIG. 2). A pixel output proportional to the illuminance is obtained. (4b) On the other hand, in a high illuminance environment, excessive charge is generated in the photodiode 30, so that the excess charge flows out from the photodiode 30 to the floating diffusion 36 over the potential barrier formed by the charge transfer transistor 32. At this time, the potential of the photodiode 30 is a potential that balances the amount of charge generated in the photodiode 30 and the amount of charge flowing out of the photodiode 30 to the floating diffusion 36. The potential change in this case shows a logarithmic characteristic 52 (see FIG. 2) with respect to the illuminance. If this logarithmic characteristic part is also used, the dynamic range can be expanded.

  Next, the reset transistor 33 is set to the on operation state to reset the floating diffusion 36 (5a, 5b), and then the reset transistor 33 is set to the off operation state to start the CDS (Correlated Double Sampling) reset level from the floating diffusion 36. Is read out (6a, 6b).

  Thereafter, the charge transfer transistor 32 is set to the on operation state to transfer the accumulated charge of the photodiode 30 to the floating diffusion 36 (7a, 7b), and the charge transfer transistor 32 is set to the off operation state to output a signal from the floating diffusion 36. The potential is read (8a, 8b).

  As can be understood from the above description, the potential at the break point 51 (see FIG. 2) of the photoelectric conversion characteristic is a potential corresponding to the amount of charge when the photodiode 30 is just saturated. By adjusting the potential barrier between the diffusion 36, that is, the potential potential formed when the charge transfer transistor 32 is turned off, the potential at the break point 51 of the photoelectric conversion characteristic can be adjusted. As shown in FIG. 5, various photoelectric conversion characteristics having different breakpoint potentials can be obtained in one pixel.

  FIG. 5 is a diagram for explaining the relationship between the height of the potential barrier between the photodiode and the floating diffusion and the obtained photoelectric conversion characteristics. In FIG. 5, (1) is a diagram showing an example of photoelectric conversion characteristics obtained when the breakpoint potential is adjusted in three ways. (2) to (4) correspond to (1), but the potential potential (potential barrier) formed when the charge transfer transistor 32 is off is (2) low, (3) slightly higher than that (4) It is a figure which shows the potential state of the photodiode 30 and the floating diffusion 36 in the case where it is higher.

  As shown in FIG. 5B, when the potential barrier is low, the potential wells of the photodiode 30 and the floating diffusion 36 become considerably shallow, and the photodiode 30 is saturated soon. In this case, a photoelectric conversion characteristic having a low breakpoint potential indicated by reference numeral 55 in FIG.

  Further, as shown in FIG. 5C, when the potential barrier is slightly high, the potential wells of the photodiode 30 and the floating diffusion 36 are slightly deepened, and the time when the photodiode 30 is saturated is slightly delayed. In this case, a photoelectric conversion characteristic in which the breakpoint potential indicated by reference numeral 56 in FIG.

  Further, as shown in FIG. 5 (4), when the potential barrier is considerably high, the potential wells of the photodiode 30 and the floating diffusion 36 are considerably deepened, and the time when the photodiode 30 is saturated is further delayed. Become. In this case, a photoelectric conversion characteristic in which the breakpoint potential indicated by reference numeral 57 in FIG.

  According to the present invention, when the AGC circuit 6 which is a subsequent circuit operates with a set gain value, the break potential of the photoelectric conversion characteristic can be adjusted so as to be within the operation range of the AGC circuit 6. The purpose is to expand the dynamic range regardless of the magnitude of the gain value set in the circuit 6.

  That is, in this embodiment, as shown in FIG. 1, the drive buffer 46 for driving the charge transfer transistor 32 is a drive buffer with a control terminal, and a control circuit (gain register 7, sequencer 8, off) is connected to this control terminal. The output voltage of the buffer amplifier 11 in the potential register 9, the variable voltage source 10, and the buffer amplifier 11), that is, the output voltage of the variable voltage source 10 is applied. The drive buffer 46 is a level signal on the side that drives the charge transfer transistor 32 to the off operation state among the binary level signals output to the gate electrode of the charge transfer transistor 32 according to the voltage value applied to the control terminal. The potential of can be changed.

  The gain register 7, sequencer 8 and off potential register 9 in the control circuit perform the following operations. When a gain value to be set in the AGC circuit 6 is written from the outside, the gain register 7 gives the set gain value to the gain input terminal of the AGC circuit 6 and indicates to the sequencer 8 that the gain has been changed. The signal and the changed gain value are transmitted. The AGC circuit 6 multiplies the charge signal from the read line 5 by the gain value applied to the gain input terminal from the gain register 7 to obtain an imaging signal, and outputs it to the outside of the chip.

  The sequencer 8 includes a table indicating a correspondence relationship between the gain value notified from the gain register 7 and the register value set in the off potential register 9. This relationship table is created as follows. That is, the photoelectric conversion characteristic is measured by changing the voltage value for turning off the charge transfer transistor 32 for each gain value, and the turning point potential at that point becomes the desired potential that does not deviate from the operating range of the AGC circuit 6. The operating voltage value is found and recorded as a register value to be set in the off potential register 9. By this measurement, the gain value set in the AGC circuit 6 is associated with the off-potential register value that keeps the break potential of the photoelectric conversion characteristics within the operation range of the AGC circuit 6 when the AGC circuit 6 operates with the gain value. A table to be created is created and set in the storage means of the sequencer 8.

  The sequencer 8 sets a register value corresponding to the changed gain value in the off potential register 9 with reference to the relation table. As a result, the voltage value of the variable voltage source 10 variably operated according to the register value of the off-potential register 9 is applied to the control end of the drive buffer 46 via the buffer amplifier 11.

  As a result, the potential of the level signal on the side that turns off the charge transfer transistor 32 among the binary level signals output from the drive buffer 46 is changed according to the gain value applied to the AGC circuit 6. Specifically, the charge transfer transistor 32 is turned off so that the height of the potential barrier formed when the charge transfer transistor 32 is turned off is low when the gain value applied to the AGC circuit 6 is large and high when the gain value is small. The potential of the level signal on the operating side is changed.

  In FIG. 1, since the charge transfer transistor 32 is an NMOS transistor, the off-voltage register 9 causes the variable voltage source 10 to output a higher voltage value than when it is small when the gain value applied to the AGC circuit 6 is large. The register value is set. Therefore, the low level potential applied to the gate electrode of the charge transfer transistor 32 by the drive buffer 46 is changed to a potential close to the high level potential. That is, the off operation state of the charge transfer transistor 32 is set to a shallow off operation state when the gain value applied to the AGC circuit 6 is large, compared to when the gain value is small.

  As described above, in the control circuit (gain register 7, sequencer 8, off potential register 9, variable voltage source 10, and buffer amplifier 11), the gain value indicates the height of the potential barrier between the photodiode 30 and the floating diffusion 36. When the gain is large, the adjustment operation can be made lower than when it is small. Therefore, even when a large gain value is given to the AGC circuit 6, the break point (boundary point) between the linear characteristic portion and the logarithmic characteristic portion of the photoelectric conversion characteristic of the photodiode 30. Can fall within the operating range of the AGC circuit 6 (see FIGS. 6 and 7), and even if a large gain is applied to the AGC circuit 6, the dynamic range can be expanded without any problem.

  FIG. 6 is a diagram for explaining the output characteristics of the AGC circuit in the prior art without the control circuit shown in FIG. FIG. 7 is a diagram for explaining output characteristics of the AGC circuit according to the first embodiment. In both figures, the horizontal axis represents the illuminance represented on a logarithmic scale, and the vertical axis represents the output potential of the pixel represented on a linear scale. A range 60 indicated by a bidirectional arrow on the vertical axis side is an operation range of the AGC circuit 6. A range 61 indicated by a bidirectional arrow on the horizontal axis side is a pixel range that can be used by the AGC circuit 6 before the gain is applied. Ranges 62 and 63 indicated by bidirectional arrows on the horizontal axis side are pixel ranges that can be used by the AGC circuit 6 after gain is applied. A characteristic indicated by reference numeral 64 is a photoelectric conversion characteristic of the pixel when no gain is applied to the AGC circuit 6. The characteristics indicated by reference numerals 65 and 66 are the photoelectric conversion characteristics of the pixels obtained when the AGC circuit 6 is multiplied by a gain.

  As shown in FIG. 6, in the conventional technique, when no gain is applied to the AGC circuit 6, the photoelectric conversion characteristic 64 of the pixel has a certain amount of potential between its breakpoint potential and its upper limit value within the operating range 60. Since a range having a logarithmic characteristic part at least at the breakpoint potential side does not exceed the operating range 60, the dynamic range can be expanded using the logarithmic characteristic part existing in the operating range 60. However, when gain is applied to the AGC circuit 6, if the gain is increased, the breakpoint potential after gain processing increases toward the upper limit of the operating range 60, so that the range of available logarithmic characteristics becomes narrower. Go. When the gain is increased to a certain value or more, as shown in the photoelectric conversion characteristic 65, the breakpoint potential after the gain processing greatly exceeds the upper limit of the operation range 60. In this case, the pixel range 62 that can be used by the AGC circuit 6 is a region that exists in the operation range 60 in the linear characteristic portion of the photoelectric conversion characteristic 65, so that the dynamic range is larger than that of a normal solid-state imaging device having only linear characteristics. Is significantly reduced.

  On the other hand, in this embodiment, when the gain is not applied to the AGC circuit 6, it is the same as the conventional example (FIG. 6), but when the gain is applied to the AGC circuit 6, the gain is set as described above. When a gain value is written to the register 7 from the outside, an adjustment operation for changing the register value of the off-potential register 9 according to the gain value and reducing the height of the potential barrier between the photodiode 30 and the floating diffusion 36 Therefore, as shown in FIG. 7, a photoelectric conversion characteristic 66 in which the breakpoint potential after gain processing falls within the operating range 60 is obtained. The breakpoint potential of the photoelectric conversion characteristic 66 can be made substantially the same as the breakpoint potential of the photoelectric conversion characteristic 64 when no gain is applied to the AGC circuit 6. This area falls within the operating range 60. Therefore, since the pixel range 63 that can be used by the AGC circuit 6 is a range including the logarithmic characteristic portion of the photoelectric conversion characteristic 66, even when the gain is applied to the AGC circuit 6, the dynamic range is not multiplied to the AGC circuit 6. It can be kept almost the same as the case.

  Thus, according to the first embodiment, since the height of the potential barrier between the photodiode and the floating diffusion can be adjusted when the gain value is large, the adjustment operation according to the gain value can be performed. Even when a large gain value is given to the readout circuit (AGC circuit), the break point (boundary point) potential between the linear characteristic portion and the logarithmic characteristic portion of the photoelectric conversion characteristic of the photodiode should be within the operation range of the AGC circuit. Can do. Therefore, even if a large gain is applied to the AGC circuit, the dynamic range can be expanded using the logarithmic characteristic portion without any problem.

Embodiment 2. FIG.
FIG. 8 is a block diagram showing the configuration of the solid-state imaging device according to Embodiment 2 of the present invention. In FIG. 8, components that are the same as or equivalent to the components shown in FIG. 1 (Embodiment 1) are given the same reference numerals. Here, the description will be focused on the portion related to the second embodiment.

  That is, in the solid-state imaging device 1b according to the second embodiment shown in FIG. 8, the sequencer 8 is deleted in the configuration shown in FIG. 1 (first embodiment), and the register value of the off-potential register 9 is set directly from the outside. It is supposed to be. In other words, in the second embodiment, the relationship table held by the sequencer 8 shown in FIG. 1 exists outside, and when the gain value is set in the gain register 7 from the outside as in the first embodiment, The corresponding register value is taken out from the relation table outside and set in the off potential register 9.

  Also with this configuration, like the first embodiment, the drive buffer 46 is configured such that the height of the potential barrier formed during the off operation of the charge transfer transistor 32 is low when the gain value applied to the AGC circuit 6 is large. Can change the potential of the level signal on the side that turns off the charge transfer transistor 32 among the binary level signals output from the signal, even when a large gain value is given to the readout circuit (AGC circuit). It is possible to make the break point (boundary point) potential between the linear characteristic portion and the logarithmic characteristic portion of the characteristic fall within the operation range of the AGC circuit. Therefore, as shown in FIG. 7, the dynamic range can be made substantially the same as before the gain is multiplied, so that even if a large gain is applied to the AGC circuit, the dynamic range is expanded using the logarithmic characteristic portion without any problem. be able to.

  According to the second embodiment, the gain value set in the reading circuit and the potential at the break point of the photoelectric conversion characteristic of the photodiode 30 when the reading circuit operates with the gain value are outside the operating range of the reading circuit. A relation table that associates the off-potential register value to be within the range is provided, and when the gain value is written to the gain register from the outside, the register value of the off-potential register is changed from the outside with reference to the relation table. Since the sequencer shown in FIG. 1 can be omitted, the configuration can be simplified.

Embodiment 3 FIG.
FIG. 9 is a flowchart for explaining the operation of the solid-state imaging device according to Embodiment 3 of the present invention. In the third embodiment, in the solid-state imaging device 1b according to the second embodiment shown in FIG. 8, the gain value set in the readout circuit 6 and the photodiode 30 when the readout circuit 6 operates with the gain value are externally provided. Instead of providing a relational table for associating an off-potential register value with which the breakpoint potential of the photoelectric conversion characteristic of the read-out circuit falls within the operating range of the readout circuit, the register value set in the off-potential register 9 from the outside Will be described in accordance with the magnitude relationship between the gain values before and after the change set in the gain register.

  In FIG. 8, when there is a write to the gain register 7 from the outside, the gain setting of the AGC circuit 6 is changed according to the changed gain value, and a gain is multiplied to the pixel output. Therefore, in FIG. 9, when writing to the gain register 7 from the outside, the magnitude relationship between the gain values before and after the change set in the gain register 7 is examined (ST1).

  As a result, when the gain value after the change is larger than the gain value before the change (ST1: Yes), the register value of the off-potential register 9 is changed to a large value from the outside (ST2). If the off-potential register value is set high, the output potential of the variable voltage source 10, that is, the output potential of the buffer amplifier 11, becomes high because the charge transfer transistor 32 is an NMOS transistor in FIG. The operating potential becomes a shallow potential close to the ON operating potential, and the break potential of the photoelectric conversion characteristic is lowered (ST3). For this reason, even if the gain value of the AGC circuit 6 is set to be large, the break potential of the photoelectric conversion characteristic does not easily deviate from the operation range of the AGC circuit 6.

  On the other hand, when the gain value after the change is smaller than the gain value before the change (ST1: No), the register value of the off potential register 9 is changed to a small value from the outside (ST4). When the off-potential register value is set low, the output potential of the variable voltage source 10 (that is, the buffer amplifier) 11 becomes low, the off-operation potential of the charge transfer transistor 32 becomes deep, and the photoelectric conversion characteristic breakpoint potential. Becomes higher (ST5). For this reason, even if the gain value of the AGC circuit 6 is set to be small, the break potential of the photoelectric conversion characteristic is unlikely to deviate from a desired potential within the operation range of the AGC circuit 6.

  Thus, according to the third embodiment, even when the gain value given to the AGC circuit is changed between a large value and a small value, the AGC to which the gain value after changing the breakpoint potential of the photoelectric conversion characteristic is applied. The potential can be controlled so as not to deviate from the operation range of the circuit, and the dynamic range can be expanded using the logarithmic characteristic portion without any trouble.

  In the first to third embodiments, the pixel circuit has the NMOS structure. However, in the case of the PMOS structure, the charge transfer transistor becomes a PMOS transistor, and therefore the increase / decrease in the output potential of the variable voltage source. Just in the opposite direction to the first to third embodiments, the height of the potential barrier between the photodiode and the floating diffusion is adjusted in accordance with the gain value given to the AGC circuit in exactly the same manner, and the photoelectric conversion characteristics Can be within the operating range of the AGC circuit.

  More specifically, in the example of the third embodiment, when the gain value after the change is larger than the gain value before the change, the charge transfer transistor is changed to a high off-potential control value in the NMOS transistor configuration and input. In the case where the charge transfer transistor has a PMOS transistor configuration, the input value is changed to a low off-potential control value, and when the gain value after the change is smaller than the gain value before the change, the charge transfer transistor is low in the NMOS transistor configuration. When the charge transfer transistor is a PMOS transistor configuration, the value is changed and input to a high off potential control value.

  As described above, the solid-state imaging device and the driving method thereof according to the present invention are useful for expanding the dynamic range regardless of the magnitude of the gain applied to the subsequent readout circuit.

It is a block diagram which shows the structure of the solid-state imaging device by Embodiment 1 of this invention. It is a figure explaining the general photoelectric conversion characteristic (conventional photoelectric conversion characteristic) of the pixel shown in FIG. It is a figure explaining the relationship between the element in connection with charge accumulation in the pixel shown in FIG. 1, and potential potential. FIG. 2 is a sequence diagram for explaining a change in potential potential at the time of readout of the pixel shown in FIG. 1. It is a figure explaining the relationship between the height of the potential barrier between a photodiode and a floating diffusion, and the photoelectric conversion characteristic obtained. It is a figure explaining the output characteristic of the AGC circuit in a prior art without the control circuit shown in FIG. It is a figure explaining the output characteristic of the AGC circuit by Embodiment 1. FIG. It is a block diagram which shows the structure of the solid-state imaging device by Embodiment 2 of this invention. It is a flowchart explaining operation | movement of the solid-state imaging device by Embodiment 3 of this invention.

Explanation of symbols

1a, 1b Solid-state imaging device 2 Single row pixel structure 3 Scanner 3
4 Buffer circuit 5 Read line 6 Read circuit (AGC circuit)
7 Gain register 8 Sequencer 9 Off potential register 10 Variable voltage source 11 Buffer amplifier 21 Pixel circuit (pixel)
22 Output line 23 Sample / hold circuit (S / H)
24 switch 25 current source 30 photodiode 31 power source 32 NMOS transistor (charge transfer transistor)
33 NMOS transistor (reset transistor)
34 NMOS transistor (amplification transistor)
35 NMOS transistor (read selection transistor)
36 Floating diffusion 40 Buffer group 45 Buffer for driving reset transistor 46 Buffer for driving charge transfer transistor 47 Buffer for driving read selection transistor

Claims (7)

A potential barrier is formed between the photodiode for performing photoelectric conversion and the floating diffusion for temporarily holding electric charge so that the photodiode performs charge accumulation during the off operation, and the photodiode during the on operation. A pixel array in which a MOS structure pixel circuit in which a charge transfer transistor for transferring the accumulated charge to the floating diffusion is arranged in a matrix, and a row control circuit for controlling charge accumulation and readout in the pixel circuit of each row in the pixel array And a read-out circuit that amplifies the signal from the pixel array by a set gain value and outputs it to the outside of the chip.
In the row control circuit, a drive buffer for outputting a binary level signal for driving the charge transfer transistor to an on operation state and an off operation state is provided. The binary level signal according to a voltage value applied to a control terminal. And a drive buffer with a control terminal that can change the potential of the level signal on the side that drives the charge transfer transistor to the OFF operation state,
A gain value to be set in the readout circuit, and the charge transfer transistor that causes a break point potential of photoelectric conversion characteristics of the photodiode to fall within an operation range of the readout circuit when the readout circuit operates with the gain value An off-potential control value output circuit that takes out the corresponding off-potential control value from the relation table when the gain value is input from the outside.
A variable voltage source for applying a voltage value for turning off the charge transfer transistor indicated by the off-potential control value output from the off-potential control value output circuit to a control terminal of the drive buffer;
With
A solid-state imaging device , wherein the drive buffer holds the potential of a level signal on the side that drives the charge transfer transistor in an off operation state at the voltage value applied to the control terminal . A potential barrier is formed between the photodiode for performing photoelectric conversion and the floating diffusion for temporarily holding electric charge so that the photodiode performs charge accumulation during the off operation, and the photodiode during the on operation. A pixel array in which a MOS structure pixel circuit in which a charge transfer transistor for transferring the accumulated charge to the floating diffusion is arranged in a matrix, and a row control circuit for controlling charge accumulation and readout in the pixel circuit of each row in the pixel array And a read-out circuit that amplifies the signal from the pixel array by a set gain value and outputs it to the outside of the chip.
In the row control circuit, a drive buffer for outputting a binary level signal for driving the charge transfer transistor to an on operation state and an off operation state is provided. The binary level signal according to a voltage value applied to a control terminal. And a drive buffer with a control terminal that can change the potential of the level signal on the side that drives the charge transfer transistor to the OFF operation state ,
An off-potential control value of the charge transfer transistor is input from the outside so that the breakpoint potential of the photoelectric conversion characteristic of the photodiode falls within the operating range of the readout circuit when the readout circuit operates at a gain value set. An off-potential control value receiving circuit,
A variable voltage source for applying a voltage value for turning off the charge transfer transistor indicated by the off-potential control value received by the off-potential control value receiving circuit to a control terminal of the drive buffer;
With
Wherein the drive buffer, the charge transfer transistor solid-state image sensor you characterized in that to hold the potential of the level signal side to the voltage value applied to the control terminal of driving off operating state. Outside the solid-state imaging device, a gain value to be set in the readout circuit, and when the readout circuit operates with the gain value, the break potential of the photoelectric conversion characteristic of the photodiode is within the operating range of the readout circuit. A relation table for associating with the off-potential control value of the charge transfer transistor to be stored, and the off-potential control value receiving circuit includes an off-potential control value corresponding to a gain value set in the readout circuit. The solid-state image pickup device according to claim 2 , wherein the solid-state image pickup device is inputted after being taken out from the device. In the off potential control value receiving circuit, when the gain value after the change is larger than the gain value before the change, in the NMOS transistor configuration, the charge transfer transistor is closer to the on / off operation boundary voltage of the NMOS transistor. When the charge transfer transistor is a PMOS transistor configuration, it is input after being changed to a lower off potential control value that is closer to the on / off operation boundary voltage of the PMOS transistor. When the gain value after change is smaller than the gain value before change, when the charge transfer transistor is an NMOS transistor, the off-potential control value is changed to a lower value farther from the on / off operation boundary voltage of the NMOS transistor. is to input, the charge transfer transistor is the PMOS tiger a PMOS transistor configuration The solid-state imaging device according to claim 2, wherein the input is changed to OFF potential control value of a high value of farther from the on-off operation boundary voltage register. A potential barrier is formed between the photodiode for performing photoelectric conversion and the floating diffusion for temporarily holding electric charge so that the photodiode performs charge accumulation during the off operation, and the photodiode during the on operation. A pixel array in which a MOS structure pixel circuit in which a charge transfer transistor for transferring the accumulated charge to the floating diffusion is arranged in a matrix, and a row control circuit for controlling charge accumulation and readout in the pixel circuit of each row in the pixel array And a read-out circuit that amplifies the signal from the pixel array by a set gain value and outputs it to the outside of the chip.
The photoelectric conversion characteristic of the photodiode is measured by changing the voltage value for turning off the charge transfer transistor for each gain value set in the readout circuit, and the breakpoint potential there determines the operating range of the readout circuit. By searching for and recording an off-potential control value that achieves a desired potential that does not deviate, the gain value set in the readout circuit and the break-point potential of the photoelectric conversion characteristics when the readout circuit operates with the gain value are read out. Creating a relational table that associates the off-potential control values that fall within the operating range of the circuit and holding them inside the device;
When the gain value is input from the outside of the device, a voltage value for turning off the charge transfer transistor indicated by the off-potential control value obtained from the relation table is changed from the variable voltage source to the charge transfer transistor in the row control circuit. A binary level signal for driving in an on operation state and an off operation state is applied to a control terminal of a drive buffer that outputs the level signal, and the potential of the level signal on the side driving the charge transfer transistor in the off operation state is applied to the drive buffer. Holding the voltage value applied to the control terminal at the voltage value . A potential barrier is formed between the photodiode for performing photoelectric conversion and the floating diffusion for temporarily holding electric charge so that the photodiode performs charge accumulation during the off operation, and the photodiode during the on operation. A pixel array in which a MOS structure pixel circuit in which a charge transfer transistor for transferring the accumulated charge to the floating diffusion is arranged in a matrix, and a row control circuit for controlling charge accumulation and readout in the pixel circuit of each row in the pixel array And a read-out circuit that amplifies the signal from the pixel array by a set gain value and outputs it to the outside of the chip.
The photoelectric conversion characteristic of the photodiode is measured by changing the voltage value for turning off the charge transfer transistor for each gain value set in the readout circuit, and the breakpoint potential there determines the operating range of the readout circuit. By searching for and recording an off-potential control value that is a desired potential that does not deviate, the gain value set in the readout circuit and the breakpoint potential of the photoelectric conversion characteristic when the readout circuit operates with the gain value are read out. Creating a relational table that associates the off- potential control values that fall within the operating range of the circuit and holding them outside the device;
When inputting the gain value from the outside of the apparatus, and taking out and inputting the corresponding off-potential control value from the relationship table;
Driving said off the charge transfer transistor off operation is to voltage described potential control value indicates that input from an external device to said charge transfer transistor and the ON operating state at the row control circuit from the variable voltage source and OFF operation state The voltage applied to the control terminal of the drive buffer that outputs the binary level signal to be applied , and the potential of the level signal on the side that drives the charge transfer transistor to the off operation state is applied to the control buffer. the driving method of the solid-state image sensor you; and a step of Ru is held at the value. When the gain value to be set to the readout circuit is input from the outside of the apparatus, the off-potential control value of the charge transfer transistor is changed so that the breakpoint potential of the photoelectric conversion characteristics input together is within the operation range of the readout circuit. If the gain value after the change is larger than the gain value before the change, the charge transfer transistor is changed to an off-potential control value having a higher value closer to the on / off operation boundary voltage of the NMOS transistor in the NMOS transistor configuration. If the charge transfer transistor is a PMOS transistor configuration, it is changed to an off-potential control value that is lower than the on / off operation boundary voltage of the PMOS transistor and input, and the gain value after the change is the gain before the change. If less than the value, the charge transfer transistor is the NMOS transient in NMOS transistor configuration Type changed from on-off operation boundary voltage data off potential control value farther low value, the charge transfer transistor is high far from the on-off operation boundary voltage of the PMOS transistor is a PMOS transistor structure The method of driving a solid-state imaging device according to claim 6, further comprising: changing to an off-potential control value of the value and inputting the value.

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