JP4660489B2 - Element forming substrate - Google Patents

Description

  The present invention relates to an element forming substrate in which a non-SOI region is provided on an SOI (Silicon On Insulator) substrate, for example.

  In recent years, in order to improve the system performance of an LSI, a technique for integrating a logic circuit and a DRAM on the same semiconductor chip has attracted attention. On the other hand, in order to improve the performance of logic circuits mainly composed of MOSFETs, SOI-MOSFETs formed on thin-film SOI substrates have attracted attention instead of conventional silicon substrates, and commercialization has already started for high-performance logic applications. ing. In such a flow, there is an urgent need to develop an LSI in which DRAM is mixedly mounted on a high performance logic chip based on SOI.

  However, since the potential of the body region in which the channel is formed is floating in the SOI-MOSFET, characteristics variation such as a leakage current and a threshold value accompanying a circuit operation occurs due to a so-called substrate floating effect. For this reason, it is unsuitable for application to a circuit having severe demands for leak current level, threshold value variation, noise, and the like, such as a DRAM cell transistor and a sense amplifier circuit. In order to fundamentally solve the substrate floating, it is necessary to control the body potential by providing an extraction element region and a contact from the body part to the MOSFET pattern. For this purpose, the cell area, the area of the sense amplifier part, etc. There has been a problem in that the number of devices greatly increases and the high integration, which is the greatest feature of DRAM, is impaired.

  In order to avoid this problem, various methods (partial SOI) have been proposed in which a non-SOI region is provided on an SOI substrate to form a circuit portion incompatible with the substrate floating effect in the non-SOI region. For example, there is a method in which an SOI layer and a buried insulating layer (BOX layer) of an SOI substrate are partially removed by etching, silicon is selectively epitaxially grown in the etching region, and polishing and planarization is performed to form a non-SOI region (for example, a patent) Reference 1). Also, there is a method of forming a non-SOI region in which a bulk region is surrounded by an insulating spacer and a conductive spacer, overcoming the floating body effect, and electrically isolating the SOI region from the non-SOI region (for example, Patent Documents). 2).

However, in any of the methods, there is no detailed description regarding the structure of the SOI substrate used as a base and the structure of the BOX layer in the SOI region. For example, when an SOI wafer manufactured by a bonding method is used as a base material, the surface of the support substrate exposed by removing a part of the SOI layer and the BOX layer is a bonding interface, and thus is mixed unexpectedly at the time of bonding. If foreign matter remains on the support substrate surface, it is difficult to form a high-quality non-SOI region. Further, when forming a non-SOI region or forming a semiconductor element in the non-SOI region, it is difficult to control the influence on the semiconductor element when there is metal contamination, for example.
JP-A-8-17694 Japanese Patent Laid-Open No. 11-17001

  As described above, conventionally, in the element formation substrate in which the non-SOI region is formed on the SOI substrate, the quality deterioration of the non-SOI region has been a problem.

  The present invention has been made in consideration of the above-described circumstances. The object of the present invention is to form a high-quality non-SOI region on an SOI substrate, and to combine a logic circuit and a DRAM on the same semiconductor chip. An object of the present invention is to provide an element forming substrate suitable for integration.

  In order to solve the above problems, the present invention adopts the following configuration.

  That is, according to one embodiment of the present invention, an element formation substrate includes a first single crystal semiconductor substrate having a first oxide film on a part of a main surface, and a second oxide film on a main surface. A second single crystal semiconductor substrate formed on a part of the first single crystal semiconductor substrate by bonding a second oxide film to the first oxide film; and the first and second oxide films A recess provided by retreating the interface of the oxide film located on the side surface of the film, a sidewall insulating film formed on the side surface of the second single crystal semiconductor substrate, and the sidewall insulating film through the sidewall insulating film A polycrystalline or amorphous silicon film embedded in the depression and a single crystal semiconductor layer formed on the remaining portion of the first single crystal semiconductor substrate. .

  According to the present invention, an SOI structure is realized by bonding a first single crystal semiconductor substrate and a second single crystal semiconductor substrate through an oxide film, and the second single crystal semiconductor substrate and the oxide film are partially formed. A non-SOI region can be formed by forming a single crystal semiconductor layer in the removed portion. Here, when the substrates are bonded to each other, an oxide film is formed on each of the main surfaces of the first and second single crystal semiconductor substrates, so that foreign matters can be mixed into the main surfaces of the respective substrates. Can be prevented. Therefore, the main surface of the first single crystal semiconductor substrate exposed by partial removal of the second single crystal semiconductor substrate and the oxide film is a clean surface, and a high-quality single crystal semiconductor that becomes a non-SOI region thereon. A layer can be formed. Further, by embedding a polycrystalline or amorphous silicon film in the depression, the depression can function as a gettering site, and adverse effects on the semiconductor device formed in the non-SOI region can be suppressed.

  The details of the present invention will be described below with reference to the illustrated embodiments.

(First embodiment)
FIG. 1 is a cross-sectional view showing a manufacturing process of an element forming substrate according to the first embodiment of the present invention.

First, as shown in FIG. 1A, an oxide film (SiO ₂ ) 111 having a thickness of 0.1 μm or less is formed on the surface of a support side substrate (first semiconductor substrate) 110 made of a single crystal Si wafer, for example, heat It is formed by an oxidation method. Similarly, an oxide film (SiO ₂ ) 121 having a thickness of 0.1 μm or less is formed on the surface of an active layer side substrate (second semiconductor substrate) 120 made of a single crystal Si wafer by, for example, a thermal oxidation method. Note that reference numeral 130 in the drawing denotes minute foreign matter (dust) adhering to the bonding interface during substrate bonding.

  Next, as shown in FIG. 1B, the main surfaces of the substrates 110 and 120 are brought into close contact with each other to bond the oxide films 111 and 121 at room temperature. At this time, a substance other than silicon oxide constituting the oxide films 111 and 121 is prevented from being sandwiched at the bonding interface, but the foreign material 130 may be mixed in unexpectedly. Thereafter, bonding heat treatment for strengthening bonding between the substrates is performed at about 1100 ° C. Subsequently, the active layer side substrate 120 is thinned by polishing or etching. Thereby, the active layer side substrate 120 becomes an SOI layer, and the oxide films 111 and 121 become BOX layers.

Next, as shown in FIG. 1C, an oxide film (SiO ₂ ) 141 having a thickness of about 0.05 μm is formed on the active layer side substrate 120 by, for example, a thermal oxidation method, and a thickness of about 0 is formed thereon. A silicon nitride film (SiN) 142 having a thickness of 2 μm is formed.

  Next, as shown in FIG. 1D, a resist mask 143 is formed on the silicon nitride film 142, and the silicon nitride film 142 and the oxide film 141 are selectively etched using the resist mask 143. Thereafter, the resist mask 143 is removed.

  Next, as shown in FIG. 1E, using the silicon nitride film 142 as a mask, a part of the active layer side substrate 120 and a part of the oxide films 121 and 111 are removed. Specifically, the active layer side substrate 120 is selectively etched using a hydrofluoric acid solution etchant, and the oxide films 121 and 111 are selectively etched to a position including the bonded interface, that is, to the middle of the oxide film 111. In this process, since the bonding interface has a higher etching rate than that of a normal oxide film, a dent 150 is formed in the lateral direction in the BOX layer.

  Next, as shown in FIG. 2 (f), a sidewall insulating film 145 having a thickness of about 0.1 μm is formed on the side surface portion of the active layer side substrate 120. Specifically, an extremely thin thermal oxide film (on the silicon nitride film 142, the oxide film 11, and the silicon nitride film 142, the oxide film 141, the active layer side substrate 120, and the etching side surfaces of the oxide films 121 and 111) on the entire surface. (Not shown) is formed, and a silicon nitride film 145 is further formed thereon. Thereafter, the entire surface is etched by RIE (Reactive Ion Etching) to leave the silicon nitride film 145 only on the side wall portion of the active layer side substrate 120. By this step, the inner surface of the recess 150 in the BOX layer made in the previous step is also covered with the silicon nitride 145.

  Next, as shown in FIG. 2G, the remaining oxide film 111 other than directly under the active layer side substrate 120 is removed. For removing the buried oxide layer, a generally used hydrofluoric acid solution etching method is used. Since the surface of the support side substrate 110 exposed in this step is not a bonding interface, for example, when the foreign material 130 is unintentionally mixed into the bonding interface when the active layer side substrate 120 and the support side substrate 110 are bonded. Even so, these contaminants do not remain and the surface is clean. Therefore, a high-quality single crystal silicon layer can be formed on the exposed surface of the support side substrate 110 in a later step. Further, since the oxide film 111 is removed by the wet etching method, the surface of the support side substrate 110 is not damaged by the etching.

Next, as shown in FIG. 2H, an amorphous Si layer 146 is formed on the entire surface. Specifically, in order to remove the natural oxide film on the surface of the support side substrate 110, hydrogen cleaning is performed at 1000 ° C., 400 Pa, 3 min in a hydrogen atmosphere, and then SiH ₄ gas is shown in FIG. Then, an amorphous Si layer 146 having a thickness of about 0.3 μm is uniformly formed on the wafer at a temperature of 500 ° C.

  Next, as shown in FIG. 2I, crystallization annealing is performed in a hydrogen atmosphere at 600 ° C. and 25 Pa (hydrogen flow rate 10 L / min) in order to crystallize the amorphous Si layer 146. In this step, the amorphous Si layer 146 becomes the single crystal Si layer 147 on the support side substrate 110, and the amorphous Si layer 146 becomes the polycrystalline Si layer 148 on the silicon nitride film 142.

  Here, in the process of FIG. 2G, when the surface of the clean support substrate is not exposed, crystallization does not proceed normally, and a good quality single crystal Si layer is formed on the support substrate surface. Can not. In this embodiment, since the clean support substrate surface is exposed, crystallization proceeds normally. In addition, since crystallization proceeds with a single seed on the support-side substrate 110, a high-quality single crystal Si layer can be manufactured.

  Since the rate of single crystallization in the above crystallization annealing is about 0.6 nm / sec, 0.3 μm is single-crystallized by processing for 500 sec, and the support-side substrate 110 and the silicon nitride film 142 are It is possible to leave the silicon at the boundary with the top in a polycrystalline state. Further, since the silicon in the depression 150 of the oxide films 111 and 121 is surrounded by the silicon nitride film 145, it is difficult to crystallize and is in a polycrystalline state.

Next, as shown in FIG. 2J, the polycrystalline Si layer 148 on the silicon nitride film 142 is removed by polishing or etching using a mixed solution of hydrofluoric acid and nitric acid. Here, since single crystal Si and polycrystalline Si have a sufficiently high etching selectivity with respect to the above mixed solution, it is possible to remove only polycrystalline Si even by solution etching. Subsequently, after removing the silicon nitride film 142 and the oxide film 141, a thermal oxide film (SiO ₂ ) 149 is newly formed on the surface of the active layer side substrate 120 and the surface of the single crystal Si layer 147.

  Through the above steps, an element formation substrate having both an SOI region and a high quality non-SOI region can be manufactured.

  As described above, according to the present embodiment, when the SOI substrate is manufactured by bonding the substrates, the oxide films 111 and 121 are formed on the surfaces of both the substrates 110 and 120, so that the foreign matter 130 is mixed at the time of bonding. Even if this is the case, the foreign matter can be retained between the oxide films 111 and 121, and the foreign matter does not adhere to the surface of the support-side substrate 110. Therefore, the surface of the support side substrate 110 can be kept clean, and the clean surface of the support side substrate 110 can be exposed in the step shown in FIG. For this reason, subsequent deposition and single crystallization of amorphous Si can be performed satisfactorily, and a non-SOI region can be formed with high quality.

  In addition, by using solution etching when the substrate 120 and the oxide films 121 and 111 are selectively etched, the depression 150 can be formed on the side surfaces of the oxide films 121 and 111. The recess 150 functions as a gettering site, and even if there is metal contamination in the non-SOI region, the adverse effect on the semiconductor device formed in the non-SOI region can be suppressed by gettering this. .

  Note that the film thicknesses of the oxide films 111 and 121 formed on the surfaces of the substrates 110 and 120 before the substrate bonding are each 0.1 μm or less, and the total thickness is preferably 0.2 μm or less. This is because if the oxide films 111 and 121 are thicker than this, heat generated during operation of the device formed on the SOI layer cannot be released. That is, it is difficult to suppress self-heating. Furthermore, stress is applied to the SOI layer, and the mobility of carriers deteriorates.

(Second Embodiment)
FIG. 3 is a cross-sectional view showing a manufacturing process of an element forming substrate according to the second embodiment of the present invention. Note that 310 to 349 in FIG. 3 correspond to 110 to 149 in FIGS. 1 and 2.

  The difference between the present embodiment and the first embodiment described above is that the buried oxide layer is etched to a position not including the bonding interface.

  After the step shown in FIG. 1D, as shown in FIG. 3A, a part of the active layer side substrate 320 and a part of the oxide film 321 are removed using the silicon nitride film 342 as a mask. Specifically, the active layer side substrate 320 is selectively etched using a hydrofluoric acid-based solution etchant, and the oxide film 321 is selectively etched to a position not including the bonding interface, that is, to the middle of the oxide film 321.

  Next, as shown in FIG. 3B, a sidewall protective film 345 is formed on the side surface portion of the active layer side substrate 320. The sidewall insulating film 345 is a silicon nitride film, and the formation method is the same as that in the first embodiment.

  Next, as shown in FIG. 3C, the remaining oxide films 321 and 311 other than those immediately below the active layer side substrate 320 are removed. For removing the buried oxide layer, a hydrofluoric acid type solution etching method generally used is used. In this step, since the bonding interface has a higher etching rate than a normal oxide film, a dent 350 is formed in the lateral direction in the BOX layer.

  In addition, since the surface of the support side substrate 310 exposed in this step is not a bonding interface, the foreign matter 330 is unintentionally mixed into the bonding interface when the active layer side substrate 320 and the support side substrate 310 are bonded. Even in this case, these contaminants do not remain and the surface is clean. Therefore, a high-quality single crystal silicon layer can be formed on the surface of the supporting substrate 310 in a later step. Further, since the oxide films 312 and 311 are removed by the wet etching method, the surface of the support side substrate 310 is not damaged by the etching.

  Next, as shown in FIG. 3D, an amorphous Si layer 346 is formed on the entire surface. The method for forming the amorphous Si layer 346 is the same as that in the first embodiment.

  Thereafter, as in the first embodiment, crystallization annealing for crystallizing the amorphous Si layer 346 is performed, and then the silicon on the silicon nitride 345 film is removed, and the silicon nitride film 345 and A structure shown in FIG. 3E is obtained by forming a new thermal oxide film 349 after removing the oxide film 341.

  Through the above steps, an element formation substrate having both an SOI region and a high quality non-SOI region can be manufactured. The final structure is the same as that of the first embodiment except that the silicon nitride film 345 is not provided in the depression 350 on the side surfaces of the oxide films 311 and 312 and the other structure is the same as that of the first embodiment. The effect is obtained.

(Third embodiment)
FIG. 4 is a cross-sectional view showing a manufacturing process of an element forming substrate according to the third embodiment of the present invention. In addition, 410-449 in FIG. 4 respond | corresponds to 110-149 in FIG.1 and FIG.2.

  This embodiment is different from the first embodiment described above in that a selective epitaxial method is used in the formation of the Si layer in the steps shown in FIGS. 2 (h) and (i).

  After the step shown in FIG. 2G, a single crystal silicon layer 447 is selectively epitaxially grown on the exposed surface of the support side substrate 410 as shown in FIG. Specifically, the single crystal Si layer 447 is epitaxially grown only on the surface of the support side substrate 410 without growing the Si layer on the silicon nitride film 442 by selective epitaxial growth using dichlorosilane and hydrochloric acid. In this case, in the first and second embodiments, the portion where the polycrystalline silicon layer is embedded becomes a cavity. This cavity also functions as a gettering site. Further, since the polycrystalline silicon layer is not formed on the silicon nitride film 442, the polycrystalline silicon layer removing process is not necessary.

  Next, as shown in FIG. 4B, after removing the silicon nitride films 442 and 445 and the oxide film 442 on the active layer side substrate 420, a new thermal oxide film 449 is formed, so that the SOI region and the high region are formed. It is possible to manufacture a substrate for forming an element having a quality non-SOI region.

(Fourth embodiment)
FIG. 5 is a cross-sectional view showing a manufacturing process of an element forming substrate according to the fourth embodiment of the present invention. Note that 510 to 549 in FIG. 5 correspond to 110 to 149 in FIGS. 1 and 2.

  This embodiment is different from the first embodiment described above in that the bonding heat treatment for substrate bonding is performed at a higher temperature.

  In the step shown in FIG. 1B, the bonding heat treatment is performed at a higher temperature of about 1200 ° C. instead of 1100 ° C. Thereby, the bond strength between the oxide films 511 and 521 is increased, and the increase in the etching rate at the bonding interface can be suppressed.

  Thereafter, as in the first embodiment, a thermal oxide film 541, a silicon nitride film 542, and a resist mask 543 are formed, and the silicon nitride film 542 and the thermal oxide film 541 are selectively removed. Thereafter, the resist mask 543 is removed.

  Next, as shown in FIG. 5A, part of the active layer side substrate 520 and part of the oxide films 521 and 511 are removed using the silicon nitride film 542 as a mask. Specifically, the active layer side substrate 520 is selectively etched using hydrofluoric acid-based solution etching, and the oxide films 521 and 511 are selectively etched to a position including the bonded interface, that is, to the middle of the oxide film 511. In this step, since the bonding annealing temperature between the oxide films at the bonding interface is about 100 ° C. higher than that in the first embodiment, no depression is generated in the lateral direction in the BOX layer.

  Thereafter, as in the first embodiment, as shown in FIG. 5B, a sidewall insulating film 545 made of silicon nitride is formed on the side surface portion of the active layer side substrate 520, and then, FIG. As shown in FIG. 3, the remaining portion of the oxide film 511 is removed.

  Next, as shown in FIG. 5D, a single crystal Si layer 547 is formed only on the surface of the support side substrate 510. As in the first embodiment, the single crystal Si layer 547 is formed by forming an amorphous Si layer on the entire surface, then crystallizing the amorphous Si layer, and further forming silicon on the silicon nitride film 542. Can be removed by polishing or etching using a mixed solution of hydrofluoric acid and nitric acid.

  Next, as shown in FIG. 5E, after the silicon nitride films 542 and 545 and the oxide film 542 on the active layer side substrate 520 are removed, a new thermal oxide film 549 is formed, so that the SOI region and the high region are formed. It is possible to manufacture a substrate for forming an element having a quality non-SOI region.

(Fifth embodiment)
FIG. 6 is a sectional view showing the structure of an element forming substrate according to the fifth embodiment of the present invention. Note that reference numerals 610 to 649 in FIG. 6 correspond to 110 to 149 in FIGS. 1 and 2.

  This embodiment is different from the first embodiment described above in that a polycrystalline silicon layer 650 is sandwiched between oxide films 611 and 621 at the time of substrate bonding.

  In the step of FIG. 1A in the first embodiment, oxide films 611 and 621 having a thickness of 0.1 μm or less are formed on both the active layer side substrate 620 and the support side substrate 610 by, for example, a thermal oxidation method. Form. Then, a polycrystalline Si film 650 is formed on at least one oxide film.

  Thereafter, the principal surfaces of the two substrates 610 and 620 are brought into close contact with each other, thereby bonding one of the oxide films 611 and 621 and the polycrystalline Si film 650 at room temperature. Thereafter, a bonding heat treatment for strengthening the bonding is performed at about 1100 ° C. The subsequent steps are the same as those in the first embodiment.

  Even with such a method, the structure similar to that of the first embodiment can be obtained only by the presence of the polycrystalline Si film 650 between the oxide films 611 and 612. Therefore, the same effect as the first embodiment can be obtained.

  Next, the significance of the element forming substrate in each of the above embodiments will be described. FIG. 7A shows the result of fabricating a TEG for evaluating the oxide film breakdown voltage in the non-SOI regions of the partial SOI wafers fabricated in the first to fifth embodiments and evaluating the breakdown voltage. Here, “withstand voltage C + mode” has the same meaning as “intrinsic withstand voltage” and means a withstand voltage due to the quality of the oxide film itself. That is, the oxide film itself is broken due to an intrinsic cause, not an exogenous deterioration.

  Further, FIG. 7B shows the result of evaluation of junction leakage characteristics when about 9000 pn junctions are fabricated in an 8-inch wafer surface and a reverse bias is applied. “High leak” indicates that a leak current that is two orders of magnitude larger than the standard leak current flows at a certain bias.

  Compared to the conventional example, in any of the embodiments, the partial SOI wafer has a higher breakdown voltage than the conventional partial SOI wafer, and there are few chips through which a large junction leakage current flows. This is presumably because the non-SOI region of the partial SOI wafer according to the present embodiment has few crystal defects and few metal impurities that are sources of leakage current. Therefore, by using the partial SOI wafer according to the present embodiment, it is possible to manufacture a semiconductor element with higher quality than before.

  FIG. 8 shows an example in which a semiconductor element is formed on a partial SOI wafer manufactured according to the first embodiment. A non-SOI region in which a logic element is provided in an SOI region composed of an active layer side substrate 820 bonded to a support side substrate 810 through oxide films 811 and 821, and a single crystal Si layer 847 is formed on the support side substrate 810 DRAM is provided.

  In the figure, 830 is a foreign substance, 845 is a silicon nitride film, 861 and 871 are gate electrodes, 862 and 872 are gate oxide films, 863 and 873 are source / drain diffusion layers, 864 and 874 are element isolation insulating films, 875 is a capacitor electrode serving as a storage node, 876 is a diffusion layer for connecting the source / drain and the capacitor electrode, 877 is a nitride film for insulating and isolating the capacitor electrode from the substrate, 878 is a capacitor insulating film, and 879 is a capacitor A diffusion layer serving as a common electrode is shown.

  Thus, by providing a logic element in the SOI region, it is possible to improve the performance of the logic element, and by providing a DRAM in the non-SOI area, characteristic fluctuations such as a leakage current and a threshold value caused by circuit operation can be achieved. Can be reduced. That is, both the logic element and the DRAM can be formed in an optimum region, and a high-performance LSI in which the logic element and the DRAM are integrated on the same semiconductor chip can be realized.

  The present invention is not limited to the above-described embodiments. The etching depth for partially removing the active layer side substrate is not limited to the middle of the oxide film on the surface of the support side substrate or the middle of the oxide film on the surface of the active layer side substrate. Etching may be performed up to. Further, the thickness of the oxide film formed on the surface of the support side substrate and the thickness of the oxide film formed on the surface of the active layer side substrate are each appropriately determined within a range of 0.1 μm or less and a total of 0.2 μm or less. That's fine. Further, in forming the single crystal Si layer on the support side substrate, in the embodiment, the amorphous Si layer is formed and then single crystallized. However, the polycrystalline Si layer is formed and then single crystallized. good.

  In the embodiment, silicon is used as the first and second single crystal semiconductor substrates. However, a semiconductor other than silicon can be used as the substrate material. In addition, various modifications can be made without departing from the scope of the present invention.

Sectional drawing which shows the first half of the manufacturing process of the board | substrate for element formation concerning 1st Embodiment. Sectional drawing which shows the latter half of the manufacturing process of the element formation board | substrate concerning 1st Embodiment. Sectional drawing which shows the manufacturing process of the element formation board | substrate concerning 2nd Embodiment. Sectional drawing which shows the manufacturing process of the board | substrate for element formation concerning 3rd Embodiment. Sectional drawing which shows the manufacturing process of the element formation board | substrate concerning 4th Embodiment. Sectional drawing which shows the structure of the board | substrate for element formation concerning 5th Embodiment. The figure which shows the oxide film pressure | voltage resistant characteristic and junction leak characteristic in each embodiment. Sectional drawing which shows the structure of the semiconductor device produced using the board | substrate for element formation by 1st Embodiment.

Explanation of symbols

110... Support side substrate (first single crystal semiconductor substrate)
111... Thermal oxide film (first oxide film)
120... Active layer side substrate (second single crystal semiconductor substrate)
121 ... Oxide film (second oxide film)
DESCRIPTION OF SYMBOLS 130 ... Foreign material 141 ... Oxide film 142 ... Silicon nitride film 143 ... Resist mask 145 ... Silicon nitride film (side wall protective film)
146 ... Amorphous Si layer 147 ... Single crystal Si layer 148 ... Polycrystalline Si layer 149 ... Thermal oxide film 150 ... Recess

Claims (4)

A first single crystal semiconductor substrate having a first oxide film on a part of a main surface;
A second oxide film formed on a part of the first single crystal semiconductor substrate by bonding the first oxide film to the second oxide film on the main surface; A crystalline semiconductor substrate;
A recess provided by retreating the interface of the oxide film located on the side surfaces of the first and second oxide films;
A sidewall insulating film formed on a side surface of the second single crystal semiconductor substrate;
A polycrystalline or amorphous silicon film embedded in the recess through the sidewall insulating film;
A single crystal semiconductor layer formed on the remaining portion of the first single crystal semiconductor substrate;
An element forming substrate comprising:   The first and second single crystal semiconductor substrates and the single crystal semiconductor layer are silicon, the first and second oxide films are silicon oxide, and the sidewall insulating film is silicon nitride. The element forming substrate according to claim 1.   2. The element forming substrate according to claim 1, wherein the recess is a hemispherical groove having a deepest boundary between the first and second oxide films.   The element forming substrate according to claim 1, wherein the total thickness of the first and second oxide films is set to 0.2 μm or less.

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