JP4660975B2 - High voltage output circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a high withstand voltage output circuit composed of a CMOS circuit.
[0002]
[Prior art]
A CMOS circuit technology constituted by a p-channel MOSFET and an n-channel MOSFET can achieve low power consumption, and is therefore an essential technology for a monolithic IC. Further, the CMOS circuit has been used in a digital signal processing IC. However, with the recent progress of CMOS circuit technology, an analog signal processing IC using a CMOS circuit has also been realized.
[0003]
Further, the CMOS circuit is employed not only in a low voltage signal processing IC but also in a high voltage power IC. For example, in a driver IC for driving a plasma display (PDP) or the like, a CMOS circuit constituted by a p-channel MOSFET and an n-channel MOSFET having an element withstand voltage of 120 V is integrated as an output circuit.
[0004]
As described above, the CMOS circuit is applied not only to a low voltage drive digital signal processing IC and an analog signal processing IC, but also to a high breakdown voltage driver IC, and its uses are expanding.
FIG. 3 is a circuit diagram of a conventional high voltage output circuit. This high voltage output circuit is a high voltage output circuit of a high voltage IC (integrated circuit) for driving a plasma display or the like. This high withstand voltage output circuit is mounted on the high withstand voltage IC for 64 outputs.
[0005]
The CMOS circuit 1 is composed of a high-side p-channel MOSFET (P1) and a low-side n-channel MOSFET (N1). In front of this circuit, there is a CMOS circuit 2 constituted by a p-channel MOSFET (P2) and an n-channel MOSFET (N2). The CMOS circuit 1 is an output stage circuit, and a load is driven by the output. On the other hand, the CMOS circuit 2 is a pre-stage circuit that drives the CMOS circuit 1. This output stage circuit and the previous stage circuit constitute a high withstand voltage output circuit.
[0006]
The current drive capability required for each of the P1 and N1 devices is determined by the capacity of the load connected to Vout. P2 and N2 are required to have a current driving capability for charging and discharging the gate capacities of P1 and N1. Usually, P1 and N1 require a larger current driving capability than P2 and N2.
The steady operation of the CMOS circuit 1 and the COMS circuit 2 is as follows.
When a LOW signal is input to Vin, P2 is turned on, and the midpoint potential Va of the CMOS circuit 2 (potential at the connection point a between the drain of P2 and the drain of N2) becomes the same potential as the power supply voltage VH. . Then, N1 is turned on, and an off signal, that is, a GND potential is output to Vout. P1 and N2 are off.
[0007]
On the other hand, when a HIGH signal is input to Vin, the switching state of each element is reversed, and an ON signal, that is, VH is output to Vout. The output Vout of the CMOS circuit 1 is a signal repeatedly turned on and off controlled by Vin.
[0008]
[Problems to be solved by the invention]
Next, the transient operation of the CMOS circuit 1 will be described. There is a period in which P1 and N1 are turned on simultaneously at the rise and fall of the voltage input to Vin. In this state, current flows from VH to GND via P1 and N1. This current increases the power consumption of the integrated circuit. In addition, when a capacitor C such as a plasma display is connected as a load, this current becomes a load current Iout to charge the capacitor C and cause a malfunction such as a change in the density of the panel of the plasma display (malfunction of the load). ) May occur.
[0009]
Switching operations of N1, N2, P1, and P2 constituting the high withstand voltage output circuit are controlled by voltages applied to the respective gates. The threshold voltage of each element dominates the switching operation with respect to the gate voltage. In the following description, the threshold value is an absolute value. For example, when VH−Vin is lower than the threshold voltage (Vtp2) of P2 in the Vin signal, P2 cannot be switched. Further, when VH−Vin is slightly higher than Vtp2, P2 cannot be driven sufficiently. Therefore, normal operation of the CMOS circuit 1 cannot be obtained from either signal level. As described above, in the operation of the CMOS circuit, the threshold voltage of the MOSFET constituting the circuit is an important parameter.
[0010]
Usually, the threshold voltage of a circuit component mounted on an IC is manufactured to be constant according to each conductivity type. However, all elements of the same conductivity type do not have the same threshold voltage due to manufacturing variations. For example, the threshold voltage (Ptp1) of P1 shown in FIG. 3 does not completely match Vtp2.
In a high voltage power IC or the like, since the output element has a low on-resistance, if the gate voltage through which the same minute drain current flows is defined as the threshold voltage, the CMOS circuit 1 of the output stage circuit The threshold voltage of the MOSFET becomes lower than the threshold voltage of the MOSFET of the CMOS circuit 2 of the preceding stage circuit. For example, if the circuit of FIG. 3 is an output circuit of a high voltage power IC, Vtp1 <Vtp2.
[0011]
Thus, when Vtp1 <Vtp2, the following problem occurs when the power supply voltage rises. The operation of raising the power supply voltage is performed constantly in the sustain period of the plasma display.
Consider a state in which a load is connected to the output terminal Vout and the power supply voltage is raised from 0 V to VH when P1 is OFF, that is, when Vout is LOW.
[0012]
Since a signal is input to Vin so that P1 is turned off, P2 is turned on. However, since the power supply voltage is 0 V in the initial state, the gate-source voltage of P2 is lower than Vtp2. Therefore, P2 is off in the initial state. The midpoint voltage Va of the CMOS circuit 2 is 0V.
As the power supply voltage rises, the gate-source voltage of P2 increases, and P2 is turned on. Then, Va also rises, and the gate-source voltage of P1 becomes Vtp1 or less, and the off state of P1 is maintained.
[0013]
Here, since the potential of Va rises when P2 is turned on, when Vtp1 <Vtp2 is established, P1 is turned on before P2 is turned on. As a result, the load current Iout flowing from the power supply terminal to Vout shown in FIG. 3 is generated.
FIG. 4 shows the relationship between the power supply voltage and Iout. The upper diagram shows the power supply voltage, and the lower diagram shows the time change of Iout. When the power supply voltage rises and reaches Vtp1, P1 is turned on and Iout begins to flow. When the power supply voltage reaches Vtp2, I2 becomes zero because P2 is turned on and P1 is turned off.
[0014]
This Iout increases as the current driving capability of P1 increases, and the degree of malfunction due to Iout increases as the difference between Vtp1 and Vtp2 increases. Further, in a plasma display driving IC or the like, power consumption increases because Iout is generated simultaneously in all output circuits mounted on the IC.
As described above, in a high-breakdown-voltage output circuit in which a CMOS circuit is mounted as an output circuit, the threshold voltage of the p-channel MOSFET in the output stage circuit is lower than the threshold voltage of the p-channel MOSFET in the previous stage circuit. In addition, when the power supply voltage rises, that is, during the sustain period of the plasma display, a malfunction (load malfunction) occurs or the power consumption of the output stage circuit is increased.
[0015]
An object of the present invention is to provide a high voltage output circuit capable of solving the above-described problems, reducing power consumption, and preventing malfunction of a load.
[0016]
[Means for Solving the Problems]
In order to achieve the above object, the first p-channel MOSFET and the second n-channel MOSFET are configured, and the drain of the first p-channel MOSFET and the drain of the second n-channel MOSFET are included. An output stage circuit from which an output signal is output from a first connection point, a third p-channel MOSFET and a fourth n-channel MOSFET for driving the output stage circuit, and the third p-channel A high withstand voltage output circuit comprising: a second connection point between a drain of the MOSFET and a drain of the fourth n-channel MOSFET; and a pre-stage circuit to which a gate of the first p-channel MOSFET is connected. The threshold voltage of the first p-channel MOSFET is set higher than the threshold voltage of the third p-channel MOSFET.
[0017]
The output stage circuit configured by a CMOS circuit in which an input signal is input to a third connection point between the gate of the first p-channel MOSFET and the gate of the second n-channel MOSFET; An output signal is output from the two connection points to the third connection point, and an input signal is input to the fourth connection point between the gate of the third p-channel MOSFET and the gate of the fourth n-channel MOSFET. And a pre-stage circuit composed of a CMOS circuit.
[0018]
In addition, the drain of the fifth p-channel MOSFET is connected to the drain of the sixth n-channel MOSFET, the connection point is connected to the gate of the third p-channel MOSFET, and the fifth p-channel MOSFET is connected. The former circuit connected to the gate of the MOSFET and the second connection point is provided.
As described above, by setting the threshold voltage of the p-channel MOSFET constituting the output stage circuit higher than the threshold voltage of the p-channel MOSFET of the previous stage circuit that drives the p-channel MOSFET, the output stage It is possible to prevent the p-channel MOSFET constituting the circuit from being turned on first, and to prevent malfunction during the plasma display sustain period. Further, the power consumption of the output stage circuit can be reduced.
[0019]
In Japanese Patent Laid-Open No. 7-231253, the threshold value of the p-channel MOSFET of the output stage circuit is made higher than the threshold value of the p-channel MOSFET of the previous stage circuit in a similar circuit in which the output circuit is constituted by a CMOS circuit. However, in this publication, the circuit is a signal circuit and is not a high withstand voltage circuit that takes power, and the threshold value of the CMOS circuit of the output stage circuit is increased by a delay time. Is the main purpose and effect, and is different from the malfunction prevention which is the main purpose and effect of the invention proposed by the author.
[0020]
Japanese Patent Application Laid-Open No. 6-164361 also discloses that the threshold value of the CMOS circuit of the output stage circuit is increased. It is the main object and effect to achieve a reduction in the rate of change of current at the same time, which is different from the main object and effect of the invention proposed by the author.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a circuit diagram of a principal part of a high voltage output circuit according to a first embodiment of the present invention. The same parts as those in FIG.
This high withstand voltage output circuit includes an output stage circuit of the CMOS circuit 1 constituted by a high-side p-channel MOSFET (P1) and a low-side n-channel MOSFET (N1), a p-channel MOSFET (P2) and an n It consists of a pre-stage circuit of the CMOS circuit 2 constituted by a channel-type MOSFET (N2). An output signal Vout is output from the middle point of the CMOS circuit 1, and the load is driven by the output signal Vout. The relationship between the threshold voltages of P1 and P2 is set to satisfy Vtp1> Vtp2. The threshold voltage value is an absolute value.
[0022]
By setting Vtp1> Vtp2, since P2 is turned on earlier than P1, P1 is not turned on in the process of rising the power supply voltage.
Therefore, Iout does not flow as shown in FIG. 4 when the power supply voltage rises, so that it is possible to prevent malfunction (load malfunction) during the plasma display maintenance period. Further, since Iout does not flow, the power consumption of the output stage circuit can be reduced.
[0023]
FIG. 2 is a circuit diagram showing the principal part of the high voltage output circuit according to the second embodiment of the present invention. In the following description, P3, P4 and P5 are p-channel MOSFETs, N3, N4 and N5 are n-channel MOSFETs, and Vin3, Vin4 and Vin5 are input terminals / input signals.
This high withstand voltage output circuit is composed of CMOS circuits 3, 4, and 5. The CMOS circuit 3 is an output stage circuit, and the CMOS circuits 4 and 5 are pre-stage circuits. The gate of P3 of the CMOS circuit 3 is connected to the midpoint of the CMOS circuit 4, and Vin3 is input to the gate of N3.
[0024]
The gate of P4 is connected to the midpoint of the CMOS circuit 5, and the gate of P5 is connected to the midpoint of the CMOS circuit 4. Vin4 and Vin5 are input to the gates of N4 and N5.
The relationship between the threshold voltages of P3 and P4 is set so that Vtp3> Vtp4.
Next, the operation of the circuit of FIG. 2 will be described. Switching of P3 is controlled by Vin4 and Vin5, and switching of N3 is controlled by Vin3. The output state of Vout is determined by the following operation.
[0025]
A case where Vout = HIGH is described. P3 is turned on and N3 is turned off. To turn on P3, a HIGH signal is input to Vin4 and a LOW signal is input to Vin5. In this signal state, N4 and P5 are turned on, and N5 and P4 are turned off. GND is applied to the gate of P3 via N4, and P3 is turned on. On the other hand, a LOW signal is input to Vin3, and N3 is off.
[0026]
A case of an operation in which Vout = LOW will be described. P3 is turned off and N3 is turned on. By inverting the signals of Vin4 and Vin5 from the above, VH is applied to the gate of P3 via P5. As a result, P3 is turned off. On the other hand, N3 is turned on by inputting HIGH to Vin3.
Since this circuit can adjust the timing of Vin3, Vin4, and Vin5, unlike the circuit of FIG. 1, there is no period during which P3 and N3 are turned on simultaneously. Further, by shifting the timing of Vin4 and Vin5, it is possible to prevent the through current via P4-N4 and the through current via P5-N5.
[0027]
When the power supply voltage rises, a signal is input so that Vout is in the HIGH impedance mode. That is, a LOW signal is input to Vin3 and Vin4, and a HIGH signal is input to Vin5. When the power supply voltage is raised from 0V to HV in this state, Vtp3> Vtp4, so that Iout does not flow as shown in FIG. Therefore, it is possible to prevent malfunction (load malfunction) during the sustain period of the plasma display. Further, since Iout does not flow, the power consumption of the output stage circuit can be reduced.
[0028]
In the first embodiment and the second embodiment, the threshold voltages of P2 and P4 are set lower than P1 and P3 by adopting a terrace gate structure or using a manufacturing technique such as channel doping. Can be easily realized.
[0029]
【The invention's effect】
According to the present invention, in a high withstand voltage output circuit having a CMOS circuit mounted as an output circuit, the threshold voltage of the p-channel MOSFET constituting the CMOS circuit of the output stage circuit is set to the level before the p-channel MOSFET is driven. By making the threshold voltage higher than the threshold voltage of the p-channel MOSFET of the circuit, malfunction (load malfunction) during the sustain period such as plasma display is prevented when the power supply voltage rises, and the power consumption of the output stage circuit is reduced. can do.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a main part of a high voltage output circuit according to a first embodiment of the present invention. FIG. 2 is a circuit diagram of a main part of a high voltage output circuit according to a second embodiment of the present invention. Output circuit diagram [Fig. 4] Diagram showing the relationship between power supply voltage and Iout [Explanation of symbols]
1 CMOS circuit (output stage circuit)
2, 3 CMOS circuit (front circuit)
P1, P2, P3, P4, P5 p-channel MOSFET
N1, N2, N3, N4, N5 n-channel MOSFET
Vin, Vin3, Vin4, Vin5 Input signal / input terminal Vout Output signal / output terminal VH Power supply voltage / power supply high potential terminal GND Ground / ground terminal C Load capacitance

Claims (3)

An output signal from a first connection point between the drain of the first p-channel MOSFET and the drain of the second n-channel MOSFET. Output stage circuit, a third p-channel MOSFET and a fourth n-channel MOSFET for driving the output stage circuit, and a drain of the third p-channel MOSFET and the fourth p-channel MOSFET. A high-breakdown-voltage output circuit comprising: a second connection point with a drain of an n-channel MOSFET; and a pre-stage circuit to which a gate of the first p-channel MOSFET is connected. A high withstand voltage output circuit, characterized in that the threshold voltage is made higher than the threshold voltage of the third p-channel MOSFET. The output stage circuit configured by a CMOS circuit in which an input signal is input to a third connection point between the gate of the first p-channel MOSFET and the gate of the second n-channel MOSFET; and the second connection A CMOS circuit that outputs an output signal from a point to the third connection point, and an input signal is input to a fourth connection point between the gate of the third p-channel MOSFET and the gate of the fourth n-channel MOSFET The high breakdown voltage output circuit according to claim 1, further comprising: a pre-stage circuit configured by: The drain of the fifth p-channel MOSFET is connected to the drain of the sixth n-channel MOSFET, the connection point is connected to the gate of the third p-channel MOSFET, and the fifth p-channel MOSFET is connected. The high-breakdown-voltage output circuit according to claim 1, further comprising: the pre-stage circuit connected to the gate of the first stage and the second connection point.

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