JP4664224B2 - Netlist generation method and generation apparatus - Google Patents

Description

The present invention relates to a generation method for generating a top netlist.
In the previous process for designing the layout of the semiconductor device, the top netlist is generated. It is necessary to make this top-level netlist generation method more efficient and reduce the man-hours.

  FIG. 8 shows a conventional process from creation of external specifications to layout design. An external specification is first created based on a meeting with a customer (step 1), and then an internal specification is examined based on the external specification (step 2).

Next, a top connection diagram is created (step 3), and a top netlist is generated based on the connection diagram (step 4).
When the highest netlist is generated, a logic verification process is performed (step 5). If an error occurs, steps 3 to 5 are repeated. If there is no error in step 5, logic synthesis processing is performed (step 6), layout design is performed based on the highest netlist (step 7), and the process proceeds to the manufacturing process.
JP 2002-24311 A

  In the generation process of the top netlist as described above, the worker's personal skill greatly affects man-hours. In other words, in the internal specification review in Step 2, circuit elements necessary for reviewing the internal specification are extracted from the data held by the operator and used, and the generated internal specification is created as an internal specification. Without proceeding to Step 3. Further, since the net list is manually generated in step 4, when the skill of the operator is low, mistakes increase and man-hours for correcting the increase increase.

As described above, when the net list is generated, there is a problem that the skill of the worker greatly affects the man-hours.
Patent Document 1 discloses a procedure of purchase order → algorithm design → system specification design → RTL description → logic verification → net list → layout design, and whether or not the algorithm and RTL description are equivalent while utilizing IP. A configuration for verifying the above and improving the design efficiency is disclosed.

However, the idea for improving the efficiency of the algorithm design and improving the design accuracy is not disclosed.
An object of the present invention is to provide a netlist generation method capable of streamlining processes from creation of external specifications to generation of a top-level netlist, and leveling man-hours and design accuracy regardless of worker skills. is there.

The above object is achieved by a net list generation method net list generating device generates the control unit provided in the said net list generating unit is input with the framework according to the input screen, the connection information of the parameter level, stored in the storage means, and macro information set in advance, on the basis of a general purpose port information is information for generating the netlist, IP information, address decoding information, interrupt information, port information, I / O This is achieved by a netlist generation method that generates a logical specification including information and environment information as a rule file.

  According to the present invention, it is possible to provide a netlist generation method capable of streamlining processes from creation of external specifications to generation of a top-level netlist, and leveling man-hours and design accuracy regardless of worker skills. it can.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 7 shows the configuration of an LSI top-level netlist generation apparatus. The control unit 1 includes a GUI (graphical user interface) device, reads product type information, macro data, a model master, and the like from the database 2 and inputs hierarchical macro information from the hierarchical macro generation engine 3 by an operator's input operation. Based on each information, each input screen for inputting basic information of the chip, inputting a module list, inputting a PAD information list, inputting interrupt information, and inputting an IO map is sequentially displayed on the display 4. To do.

The control unit 1 generates internal specifications such as specific connection information from each data input based on the external specifications on each input screen, and stores the internal specifications as a rule file 5.
The rule file 5 is automatically converted into the highest netlist 10 by the operation of the conversion engine 6 and stored. The rule file 5 can be output as an internal specification 7 a by the form creation engine 7.

  FIG. 1 shows a procedure for generating a top netlist by the top netlist generating apparatus. This generation procedure is roughly divided into a logical information generation step 8 for generating the rule file 5 and a netlist generation step 9 for generating the highest netlist 10 from the rule file 5.

  Logic information generation step 8 includes input of chip basic information (step 11), module list input (step 12), PAD information list input (step 13), interrupt information input (step 14), and address map input. (Step 15) are sequentially performed.

  In each of the above steps, the operator inputs the input information on the display 4 at the parameter level in each step, and is stored in advance in the template template 12, the macro RTL 13 based on the RTL (Resister Transfer Level) description, and the macro information master 14. Data is read.

  FIG. 2 shows the processing of the logical information generation step 8. In each of the steps 11 to 15, the corresponding input screens 15 a to 15 e are displayed on the display 4. Each of the input screens 15 a to 15 e is displayed based on the data stored in the template template 12 and the data stored in the macro information master 14. And in each input screen 15a-15e, the default value displayed by the blank is initialized at a parameter level (text level). The input screens 15b to 15e are not displayed until the input operation on the previous screen is completed.

  The parameter level input information initially set by the framework of the input screens 15a to 15e is converted from the input format to the output format by the control unit 1, and the rule file 5 is generated. FIG. 3 shows the relationship between the input information initially set on each of the input screens 15a to 15e and the rule file 5 generated by converting the input information.

  Each data is read from the macro information master 14 by the input process of each step 11-15. Then, each piece of information shown in FIG. 3 is generated as a rule file 5 based on these data and the input information initially set on the input screens 15a to 15d.

The information includes general-purpose port information 16, IP information 17, address decode information 18, interrupt information 19, port information 20, I / O information 21, and environment information 22.
FIG. 5 is an example of the input screens 15a to 15e, and shows the PAD information list input screen in step 13. In the figure, a blank field 23a is a field for inputting a connection start point, and a blank field 23b is a field for inputting a connection end point.

  When the setting button 24 is clicked with the start point information and end point information entered in the blanks 23a and 23b, the instance of the connection destination IP is automatically entered in the blank 23c based on the data stored in the macro information master 14. Name and terminal name are set automatically.

  FIG. 6 shows the navigator screen of the logical information generation step 8, showing the progress status of each of the steps 11 to 15, which is displayed by clicking the selection button 25 shown in FIG.

  Then, the first to fourth statuses 31a to 31d are displayed, and the first status 31a indicates whether or not the product information input, that is, the input processing in steps 11 and 12 has been completed. The second status 31b indicates whether or not the input process in step 13 has been completed, and the third status 31c indicates whether or not the input process in step 14 has been completed. The fourth status 31d indicates whether or not the input process in step 15 has been completed.

  For example, the status being input is displayed in red, the input completion status is displayed in blue, and the uninput status is displayed in colorless. The input status and the input completion status can be input, and the non-input status cannot be input.

  In FIG. 1, the net list generation step 9 includes creation of a connection rule file based on the rule file 5 (step 16), generation of an I / O frame (step 17), generation of an address decoder (step 18), net list. The top netlist 10 is automatically generated through each step of the conversion process (step 19).

  In step 16, a connection rule is created from the rule file 5 and stored in the file 26a. In step 17, port information in the RTL description is generated from the data stored in the rule file 5 and the I / O frame control file 27. Store in file 26b.

  In step 18, address decoder information described in the RTL description is generated from the data stored in the rule file 5 and the address decoder control file 28, and stored in the file 26c.

  In step 19, a process for generating a netlist is performed based on the information stored in the files 26a to 26c and the macro information stored in advance in the file 26d. FIG. 4 shows the processing contents of step 19.

  As shown in the figure, each information of the RTL description stored in the files 26a to 26d is converted into, for example, an XML format language, and the information and the connection information 29 described at the text level in the rule file 5 are obtained. In combination, the text is converted into the RTL information 30 in the Verilog format, and the highest netlist 10 is generated.

  Then, the highest netlist 10 is verified, and if an error occurs, the process returns to step 13 of the logical information generation step 8. If no error has occurred, the process proceeds to layout design.

  The rule file 5 generated as described above is stored in the database 2 and managed as logic design information. That is, the operation history on the framework, the identification version number of the rule file 5 and the identification version number of the internal specification generated from the rule file 5 are managed in association with each other.

With the highest-level netlist generation device configured as described above, the following operational effects can be obtained.
(1) A rule file 5 corresponding to an internal specification can be automatically generated by a framework for sequentially setting parameter level input information on the input screens 15a to 15e displayed on the display 4 of the control unit 1. it can. Therefore, the generation of the rule file 5 can be leveled.
(2) Since the generation of the rule file 5 can be leveled, man-hours do not increase or decrease depending on the skill of the operator, and the accuracy of the generated rule file 5 can be improved.
(3) The netlist generation step 9 can automatically generate the highest netlist 10 from the rule file 5. Therefore, it is possible to generate the top netlist 10 with high accuracy.
(4) Various internal specifications 7a can be easily generated by the form creation engine 7 from the rule file 5 generated at the text level.
(5) The rule file 5 can be stored and managed in the database 2. Accordingly, when a revision occurs in the macro information constituting the rule file 5, the revision management can be easily performed by searching the database 2 for a product on which the macro is mounted and correcting it.

It is a flowchart which shows the production | generation procedure of the highest netlist of one Embodiment. It is explanatory drawing which shows the process of a logical information generation step. It is explanatory drawing which shows the content of a rule file. It is explanatory drawing which shows a net list conversion process. It is explanatory drawing which shows an example of an input screen. It is explanatory drawing which shows the navigator screen of a logical information generation step. It is a block diagram which shows the highest netlist production | generation apparatus. It is a flowchart which shows the conventional highest netlist production | generation process.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Control part 2 Database 4 Display 5 Rule file 15a-15e Input screen

Claims (5)

A netlist generating method generated by a netlist generating device,
The control unit provided in the net list generation device,
Entered in the framework according to the input screen, the connection information of the parameter level,
Preset macro information stored in the storage means ;
Based on the general-purpose port information is information for generating the netlist, IP information, address decoding information, interrupt information, port information, to generate a rule file logical specification including I / O information and environment information A characteristic netlist generation method. The netlist generation method according to claim 1 , wherein the conversion engine included in the netlist generation apparatus generates a netlist by performing a text level conversion process on the rule file. Storing the rule file in a database ;
3. The net list generation method according to claim 1, wherein the rule file can be managed by revision. 4. The net list generation method according to claim 1 , wherein a form creation engine included in the net list generation device generates an internal specification from the rule file. 5. A GUI device that enables input of parameter level connection information in the framework;
Wherein a GUI device, and the connection information, and a pre-stored macro information, general port information is information for generating the netlist, IP information, address decoding information, interrupt information, port information, I / O A net list generation apparatus comprising: a control unit that generates a logical specification including information and environment information as a rule file.

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