JP4667445B2 - Digital broadcast receiver - Google Patents

Description

  The present invention relates to a digital broadcast receiving apparatus, and more particularly to a digital broadcast receiving apparatus that performs a channel search to check whether there is a receivable broadcast in each frequency band.

  It has been conventionally known that a digital broadcast receiver uses a TMCC (Transmission and Multiplexing Configuration Control) signal included in a broadcast wave signal to determine whether there is a receivable broadcast wave in a channel of a certain frequency. . The TMCC frame synchronization signal takes a long time until it can be detected after the TMCC is synchronized by the demodulator circuit after being tuned by the tuner, and this time is not an average value that allows TMCC synchronization, but waits for the maximum time. Since it is necessary to determine that there is no broadcast wave, it is necessary to wait for the maximum time required for TMCC synchronization, so it takes time to determine whether there is a broadcast wave, and when searching all channels Had the disadvantage of taking time.

  An automatic channel selection device that has improved this drawback is already known (see, for example, Patent Document 1). In this automatic channel selection device, the reception level and noise level of the broadcast wave signal detected by the receiving unit are used to determine the presence or absence of the broadcast wave, and if the reception level is not higher than a predetermined level, it is determined that there is no broadcast wave. Also, even if the reception level is equal to or higher than a predetermined level, if the noise level does not decrease below a certain level, it is determined that there is no broadcast wave.

  Also, an OFDM (Orthogonal Frequency Division Multiplexing) type receiving apparatus in which the above-described drawbacks are improved is known (for example, see Patent Document 2). The OFDM receiver has multiple combinations of transmission mode (transmission symbol length mode) and guard interval (guard period) in the OFDM reception signal of the terrestrial digital broadcast wave, and detects this transmission mode during demodulation. There is a need. In the OFDM receiver, if the transmission mode detection of the OFDM received signal cannot be detected within a certain period, a signal indicating that reception is not possible is output, and this is used in the receiver during channel search. The channel can be skipped at high speed.

Japanese Patent Laid-Open No. 11-68519

JP 2001-313622 A

  However, in the former automatic channel selection device, when analog and digital broadcast waves are mixed in the broadcast wave, it is erroneously determined that there is a digital broadcast wave at the frequency at which the analog broadcast signal exists. There is a possibility. In addition, there is a problem that the accuracy is insufficient to determine whether there is a digital broadcast wave only with the reception level and the noise level.

  Further, in the latter OFDM receiver, in the case of determining only by the determination based on the transmission mode, there is a possibility of erroneously determining that there is a broadcast wave due to an analog broadcast signal, a noise signal, or the like even when there is no digital broadcast wave. There is. If an erroneous determination is made, the demodulation process is continued thereafter, and the determination of the presence / absence of a broadcast wave must wait until TMCC frame synchronization is established, and time is required when searching all channels. There was a problem of hanging.

  The present invention has been made in view of the above-described problems, and it is an object of the present invention to prevent erroneous determination due to an analog broadcast signal, a noise signal, or the like, accurately determine the presence or absence of a digital broadcast wave, and efficiently determine at high speed. And

In order to achieve the above object, the invention according to claim 1 is a receiving means for receiving a broadcast wave, a reception level detecting means for detecting a reception level of the broadcast wave, and a demodulating means for demodulating the broadcast wave. And means capable of switching between at least the first search mode and the second search mode. In the first search mode, the reception level detected by the reception level detection means is higher than a predetermined level. The second search mode is a mode for proceeding to a process for determining whether or not the digital broadcast wave is higher when the reception level is higher, and shifting to a search for another channel frequency when the reception level is lower than a predetermined level. the channel search of the migration is not performed based on the reception level, if the frame synchronization is established based on the detected TMCC signal by the demodulating means It determines that the digital broadcast wave, characterized in that it is a mode to shift to search for another channel frequency if no take frame synchronization based on the detected TMCC signal by the demodulating means.

According to a second aspect of the present invention, in the digital broadcast receiving apparatus according to the first aspect of the present invention, the digital broadcast receiving apparatus includes a storage unit that stores a channel frequency determined to be a digital broadcast wave, and the channel frequency stored in the storage unit is stored in the storage unit. A third search mode for performing a search by skipping is provided .

The invention according to claim 3 is configured such that in the digital broadcast receiving device according to claim 1, a fixed reception mode for receiving with a fixed antenna and a mobile reception mode for receiving while moving can be switched, In the mobile reception mode, channel frequency search is performed in the second search mode .

According to a fourth aspect of the present invention, in the digital broadcast receiving device according to the first aspect, the determination of the reception level in the first search mode and the determination of frame synchronization in the second search mode are respectively It is characterized by being repeatedly executed within a predetermined time .

  According to the present invention, the first search mode with excellent search speed and the second search mode with excellent search accuracy can be used properly according to the situation.

  A digital broadcast receiver according to the present invention will be described with reference to FIGS. 1 shows the configuration of the digital broadcast receiving apparatus of the present invention, FIG. 2 shows the configuration of the broadcast wave determination circuit, FIG. 3 shows the flowchart (part 1) of the channel search processing 300 of the first embodiment, and FIG. 4 shows the channel search. FIG. 5 is a flowchart of the process 300 (part 2), FIG. 5 is a display example of the search mode setting (1) menu screen, FIG. 6 is a search mode setting (2) menu screen display example, and FIG. FIG. 8 is a flowchart (part 2) of the channel search process 400 according to the second embodiment, FIG. 8 is a flowchart (part 2) of the channel search process 400, and FIG. 9 is a display example of a menu screen for setting the search mode (3). FIG.

  In FIG. 1, a digital broadcast receiving apparatus of the present invention includes a tuner 1, an A / D converter (analog / digital conversion) 2, an IQ demodulator 3, an AGC control circuit 4, and a GI (guard interval) removal circuit 5. And a mode determination circuit 6, an AFC circuit 7, an FFT circuit 8, a synchronous reproduction circuit 9, an OFDM frame decoding unit 10, a TMCC reproduction circuit 11, a broadcast wave determination circuit 12, and a CPU 13.

  The tuner 1 receives an RF signal of a digital broadcast wave received by an antenna, selects a desired reception frequency band from the RF signal, and outputs it as an intermediate frequency signal (IF signal). In the tuner 1, the received signal is amplified by a built-in amplifier based on the level of the AGC control signal from the AGC control circuit 4.

  The A / D converter 2 receives the IF signal (analog signal) output from the tuner 1, performs analog / digital conversion, and outputs the digital signal to the IQ demodulator 3 and the AGC control circuit 4.

  The IQ demodulator 3 converts the digital signal output from the A / D converter 2 into a complex baseband signal of an I signal and a Q signal, and outputs the output signal to the GI removal circuit 5 as well as the complex baseband signal. Is output to the mode determination circuit 6.

  The AGC control circuit 4 creates an AGC control signal based on the digital signal level output from the A / D converter 2 and applies it to the amplifier built in the tuner 1 to set the level of the output signal of the tuner 1 to an optimum level. It is something to control. The AGC control signal is converted into a voltage signal and output as an AGC level signal a. The AGC level signal a is, for example, 0V to 3.3V, and is set so that the reception level corresponds to the minimum when 3.3V.

  The GI removal circuit 5 removes the guard interval portion from the output signal of the IQ demodulator 3, takes out a signal in the effective symbol period, and outputs it to the AFC circuit 7.

  The mode determination circuit 6 uses a method such as detecting a correlation with a signal delayed by one symbol using a guard interval signal of the OFDM signal, and further calculating a correlation amplitude waveform by a moving average within the guard period. Thus, this is a circuit for discriminating at which value the OFDM signal transmission mode (2K, 4K, 8K) and guard interval (1/4, 1/8, 1/16, 1/32) are transmitted. A mode determination result signal b is output from the mode determination circuit 6. For example, the mode determination result signal b is set to output “H” when the mode determination is completed, and to output “L” when the mode determination is not completed.

  The AFC circuit 7 corrects the frequency offset generated in the tuner 1 and is a circuit that detects the center of the IF signal from the tuner 1 and incorporates an internal PLL. A frequency synchronization detection signal c is output from the AFC circuit 7. The frequency synchronization detection signal c is a signal for determining that the center of the IF signal has been detected. For example, “H” is output when the frequency synchronization detection is completed, and “L” is output when the frequency synchronization detection is not completed. Set to do.

  The FFT circuit 8 converts the signal in the effective symbol period from the signal in the time axis direction to the frequency in the frequency axis direction by fast Fourier transform, and then outputs the signal to the OFDM frame decoding unit 10.

  The synchronous reproduction circuit 9 accurately matches the operation of the internal circuit with the sampling timing cycle on the transmission side. The synchronous reproduction circuit 9 outputs a timing synchronization detection signal d. For example, the timing synchronization detection signal d is set to output “H” when the timing synchronization detection is completed, and “L” when the timing synchronization detection is not completed.

  The OFDM frame decoding unit 10 detects frame synchronization using a synchronization word included in the TMCC of the OFDM signal.

  The TMCC reproduction circuit 11 is a circuit that demodulates the TMCC signal included in the signal from the OFDM signal detected by the OFDM frame decoding unit 10 and outputs a TMCC frame synchronization detection signal e. The TMCC frame synchronization detection signal e is set, for example, to output “L” when the demodulation of the TMCC signal is not completed and output “H” when the demodulation is completed.

  FIG. 2 is a diagram illustrating a configuration of the broadcast wave determination circuit 12.

  In FIG. 2, a broadcast wave determination circuit 12 includes a broadcast wave determination unit 20, a level determination circuit 21, a mode determination result circuit 22, a frequency synchronization determination circuit 23, a TMCC frame synchronization determination circuit 25, and a level determination timer. 26, a mode determination timer 27, a frequency synchronization determination timer 28, a TMCC frame synchronization determination timer 30, a level determination connection switching unit 31, a mode determination connection switching unit 32, and a frequency synchronization determination connection switching unit 33. Consists of The broadcast wave determination circuit 12 includes an AGC level signal a, a mode determination result signal b, a frequency synchronization detection signal c, (timing synchronization detection signal d). The TMCC frame synchronization detection signal e is input, channel search processing 300 and 400 shown in FIGS. 3 and 4 are performed, and the result of search channel selection is output as a broadcast wave detection signal g. The broadcast wave detection signal g, for example, outputs “L” at the start of channel selection, continues to output “L” when search channel selection is successful, and “H” when it is determined that search channel selection has failed. "Is output.

When the timing synchronization detection signal d is used as the search channel selection condition and the timing synchronization determination is used, the timing synchronization determination circuit 24, the timing synchronization determination timer 29, and the timing synchronization determination connection switching unit 34 are constituent elements. It becomes.

  The broadcast wave determination unit 20 includes a level determination signal f from the level determination circuit 21, a mode determination result signal b from the mode determination result circuit 22, a frequency synchronization detection signal c from the frequency synchronization determination circuit 23, and a TMCC frame synchronization. Using the TMCC frame synchronization detection signal e from the determination circuit 25 and the timeout signals from the level determination timer 26, the mode determination timer 27, the frequency synchronization determination timer 28, and the TMCC frame synchronization determination timer 30, FIG. The channel search processes 300 and 400 in the flowchart shown in FIG. 4 are performed, and the search channel selection result is output as the broadcast wave detection signal g. Further, based on the user's operation, the predetermined level N for determination of the level determination circuit 21 is set by the broadcast determination circuit control signal sent from the CPU 13, and the level determination timer 26, mode determination timer 27, frequency synchronization is set. The determination timer 28 and the TMCC frame synchronization determination timer 30 are timed out, and the level determination connection switching unit 31, the mode determination connection switching unit 32, and the frequency synchronization determination connection switching unit 33 are switched to determine the search channel selection. Determine the conditions.

  The level determination circuit 21 determines the magnitude of the AGC level signal a and outputs the result as a level determination signal f. That is, it is determined whether or not the AGC level signal a is smaller than the predetermined level N (the received broadcast wave is larger than the predetermined level and can be received). When the AGC level signal a is larger than the predetermined level N, the signal f is set to output “L”.

  The mode determination result circuit 22 outputs the mode determination result signal b from the mode determination circuit 6 as it is.

  In addition, it is possible to read the register from outside by recording the mode judgment result in the register.

  The frequency synchronization determination circuit 23 outputs the frequency synchronization detection signal c from the AFC circuit 7 as it is.

  It is also possible to record the frequency synchronization status and read the register from outside by providing a register.

  The TMCC frame synchronization determination circuit 25 outputs the TMCC frame synchronization detection signal e from the TMCC reproduction circuit 11 as it is.

It is also possible to read a register from outside by registering the TMCC synchronization status.

  The level determination timer 26 sets a determination time when the AGC level signal a is used as a determination condition for search channel selection to a time commensurate with the determination process. For example, it is set to 100 ms. In this case, the level determination timer 26 first outputs “L” and outputs “H” after 100 ms.

  The mode determination timer 27 sets the determination time when the mode determination result signal b is used as the determination condition for search channel selection to a time commensurate with the determination process. For example, it is set to 100 ms.

  The frequency synchronization determination timer 28 sets the determination time when the frequency synchronization detection signal c is used as the determination condition for search channel selection to a time commensurate with the determination process.

  The TMCC frame synchronization determination timer 30 sets a determination time when the TMCC frame synchronization detection signal e is used as a search channel selection determination condition to a time commensurate with the determination process.

  The level determination connection switching unit 31 determines whether or not to use the AGC level signal a as a search channel determination condition. FIG. 2 shows a case where the AGC level signal a is used, and the level determination signal f is input to the broadcast wave determination unit 20 as it is. When the level determination connection switching unit 31 is switched, the level determination signal f cannot be input and the “H” signal is input.

  The mode determination connection switching unit 32 determines whether to use the mode determination result signal b as a search channel selection determination condition. Others are the same as the level determination connection switching unit 31.

  The frequency synchronization determination connection switching unit 33 determines whether or not to use the frequency synchronization detection signal c as a search channel selection condition. Others are the same as the level determination connection switching unit 31.

  The CPU 13 controls the entire digital broadcast receiving apparatus, decodes the user's operation, and generates a broadcast wave determination circuit control signal for setting a determination condition necessary for the broadcast wave determination circuit 12 to perform search channel selection. And sent to the broadcast wave determination unit 20. Further, the success or failure of the tuning is determined using the broadcast wave detection signal g obtained from the broadcast wave judgment unit 20 and the TMCC frame synchronization detection signal e obtained from the TMCC reproduction circuit 11. For example, if the broadcast wave detection signal g is “H”, it is determined that reception is impossible. If the broadcast wave detection signal g is “L” and the TMCC frame synchronization detection signal e is “H”, it is determined that reception is possible. If the broadcast wave detection signal g is “L” and the TMCC frame synchronization detection signal e is also “L”, it is determined that the channel selection operation is currently being executed.

  Next, the operation of the digital broadcast receiving apparatus of the present invention when performing a channel search for the presence of a receivable digital broadcast wave in each channel (frequency band) will be described. In the following, a case where the frequency assigned to terrestrial digital is 13 to 62 channels in the UHF band, an analog broadcast wave is present in 15 channels, and a digital broadcast wave is present in 16 channels will be described as an example.

  3 and 4 are flowcharts of the channel search process 300 according to the first embodiment.

  3 and 4, the CPU 13 notifies the broadcast wave determination unit 20 that the channel selection has been started by the broadcast wave determination circuit control signal, and starts the channel search processing program 300.

  When the broadcast wave determination unit 20 knows from the CPU 13 that the channel selection has been started by the broadcast wave determination circuit control signal, the broadcast wave detection signal g is reset to “L” if the broadcast wave detection signal g is “H”. Similarly, the mode determination connection switching unit 32 and the frequency synchronization determination connection are connected so that the level determination signal f which is an output signal from the level determination circuit 21 is input to the broadcast wave determination unit 20. The switching unit 33 (and the frequency synchronization determination connection switching unit 34) also switches so that the mode determination result signal b and the frequency synchronization detection signal c (and the timing synchronization detection signal d) are input to the broadcast wave determination unit 20.

  Subsequently, the broadcast wave determination unit 20 first sets the first channel (13 channels) as the channel selection frequency (frequency) of the tuner 1 (step S301). Next, the level determination timer 26 is started (step S302), and then it is determined whether or not the level determination signal f is “H” (step S303). When the level determination signal f is “L”, after waiting for a certain period (for example, 10 ms) (step S304), it is determined whether or not the output signal from the level determination timer 26 is “H” (step S304). In step S305), it is confirmed whether or not the level determination period has passed the timeout time. If the output signal from the level determination timer 26 is not “H”, the process returns to step S303 to repeat the processing after step S303 (determines the level of the level determination signal f at intervals of 10 ms). In the case of the first 13 channels, there is no broadcast wave, the level of the AGC level signal a is maximum, the level determination signal f from the level determination circuit 21 remains “L”, and for level determination after 100 ms elapses. The signal from the timer 26 becomes “H”, the elapse of the time-out time for level determination is detected, and the process proceeds to step S319.

  In step S319, after setting the next channel frequency, it is determined whether or not the set channel is the last next channel (step S320). If it is determined that the channel is not the last channel, the process returns to step S302 and the processing from step S302 is repeated (if it is determined that the channel is the last channel, the broadcast wave detection signal g is determined as a search channel selection failure). Is set to “H” (step S321), and the channel search process is terminated). Since there are no digital broadcast waves in channel 13 and channel 14, the above processing is repeated until channel 15 is set. When 15 channels are set, an analog broadcast wave exists, so the level determination signal f from the level determination circuit 21 becomes “H”, and it is determined as “H” in step S303, and the process proceeds to step S306. (First-stage processing) By the above-described processing (first-stage processing), if the level determination signal f is “H”, there is a digital broadcast wave immediately, and if the level determination signal f is “L”. Since it is determined that there is no digital broadcast wave after waiting for a certain period (100 ms in this case), it is determined that there is no digital broadcast wave at a higher speed than the conventional example in which the presence or absence of the digital broadcast wave is determined by the TMCC frame synchronization detection signal. I can do it. For example, if the timeout period of the TMCC frame synchronization detection signal is set to 2 seconds (when it normally takes 1 second to complete detection of the TMCC synchronization frame synchronization detection signal e and 2 seconds is required as the maximum value) In order to determine the presence or absence of a digital broadcast wave, it takes 2 seconds, but it can be completed in the time-out time 100 ms of the level determination signal f.

  Next, the broadcast wave determination unit 20 starts the mode determination timer 27 in step S306, and then determines whether or not the mode determination result signal b from the mode determination result circuit 22 is “H” (step S307). . When it is not “H”, after waiting for a certain period (step S308), it is determined whether or not the output signal from the mode determination timer 27 is “H” (step S309), so that the mode determination period has passed the timeout time. Check if you did. If the output signal from the mode determination timer 27 is not “H”, the process returns to step S307 to repeat the processing from step S307. In the case of 15 channels, since there is no digital broadcast wave, the mode determination result signal b remains “L”, and the signal from the mode determination timer 27 becomes “H” after the timeout time set in the mode determination timer 27. Then, the elapse of the time-out time for mode determination is detected, and the process proceeds to step S319. Step S319 and subsequent steps are the same as the first stage process. Even in the 15th channel, the signal from the mode determination result circuit 22 may erroneously become “H” due to noise or the like, and if it is determined as “H” in step S307, the process proceeds to step S310. (Second-stage processing) By the above-described processing (second-stage processing), when the timeout time of the mode determination timer 27 is set to 100 ms, for example, the total of 100 ms of the level determination timer 26 is 20 ms. The presence or absence of waves can be determined.

Next, the broadcast wave determination unit 20 starts the frequency synchronization determination timer 28 in step S310, and then determines whether or not the frequency synchronization detection signal c from the frequency synchronization determination circuit 23 is “H” (step S311). ). When it is not “H”, after waiting for a certain period (step S312), it is determined whether the output signal from the frequency synchronization determination timer 28 is “H” (step S313), so that the frequency synchronization determination period becomes the timeout time. Check whether or not If the output signal from the frequency synchronization determination timer 28 is not "H", the process returns to step S311 and the processes in and after step S311 are repeated. In channel 15, since the broadcast wave is not a digital signal, the AFC does not converge within the timeout time set in the frequency synchronization determination timer 28, and the signal from the frequency synchronization determination timer 28 is “H” after the timeout time. If it is determined that there is a timeout period of the frequency synchronization determination, the process proceeds to step S319. Step S319 and subsequent steps are the same as the first stage process. Since the broadcast wave is a digital signal in the 16th channel, it is determined in step S311 that the frequency synchronization detection signal c from the frequency synchronization determination circuit 23 is “H”, and the process proceeds to step S314. (3rd stage processing)
In this embodiment, the timing synchronization detection signal d is not used as a search channel selection determination condition, but the timing synchronization determination circuit 24 and the timing synchronization determination circuit 24 are synchronized with each other as in the third stage processing using the frequency synchronization detection signal c. It is also conceivable to add processing for determining whether timing synchronization can be detected in a certain period using the determination timer 29 and the timing synchronization determination connection switching unit 34. By using the timing synchronization detection signal d, the presence / absence of a digital broadcast wave can be correctly determined even if frequency synchronization is erroneously detected. (Fourth Stage Process) Next, the broadcast wave determination unit 20 starts the TMCC frame synchronization determination timer 30 in step S314, and then the TMCC frame synchronization detection signal e from the TMCC frame synchronization determination circuit 25 is “H”. Whether or not (step S315). If it is not “H”, after waiting for a certain period (step S316), it is determined whether the output signal from the timer 30 for TMCC frame synchronization determination is “H” (step S317), so that the TMCC frame synchronization determination period is Check whether the timeout period has elapsed. If the output signal from the TMCC frame synchronization determination timer 30 is not “H”, the process returns to step S315 and the processes in and after step S315 are repeated. Since the broadcast wave is not a digital signal in channels 13 to 15, the TMCC frame synchronization detection signal e does not exist within the timeout time set in the TMCC frame synchronization determination timer 30. It is determined that the signal from the timer 30 is “H”, a time-out of TMCC frame synchronization determination is detected, and the process proceeds to step S319. Step S319 and subsequent steps are the same as the first stage process. (Fifth stage processing)
In the case of 16 channels, since there is a digital broadcast wave, it is determined in step S303 that the level determination signal f is “H” within a certain period, and mode determination is also “H” within a certain period in step S307. In step S311, it is determined that the frequency synchronization detection is completed within a certain period and the frequency synchronization detection signal c is “H”. In step S315, TMCC synchronization is established, and the TMCC frame synchronization determination circuit 25 The TMCC frame synchronization detection signal e becomes “H” and it is detected that there is a broadcast wave, and the process proceeds to step S318. In step S318, assuming that the search channel selection has succeeded, the broadcast wave detection signal g is set to “L”, and then the channel search process is terminated.

  Even if the above-described channel search processing is performed for all channels, if there is no digital broadcast wave and the search channel selection fails, it is determined that the search channel selection has failed, and the broadcast wave detection signal g is set to “ After “H”, the channel search process is terminated.

  In the embodiment described above, the channel search process is terminated when the digital broadcast wave is present and the search channel selection is successful. However, all channels may be searched and terminated.

  Next, the setting of the channel search processing 300 of the first embodiment described above will be described with reference to FIGS. FIGS. 5 and 6 are display examples of menu screens for setting search modes (1) and (2) on the display screen using the on-screen display OSD.

  In FIG. 5, search mode setting (1) search modes include a normal search mode for searching at a normal speed, a high-speed search mode for searching at a high speed, and a low-speed search mode for searching at a low speed. Click one of the high-speed search mode, normal search mode, and low-speed search mode to set the search mode, and then click search execution to perform channel search.

  In the normal search mode, as is conventionally known, a channel search is performed so as to determine whether TMCC synchronization can be achieved within a certain period (for example, 2 seconds).

In the high-speed search mode, a search is performed by the channel search processing 300 of the first embodiment of the present invention.
At this time, the first search mode in the first embodiment proceeds to processing for determining a digital broadcast wave when the reception level detected by the reception level detection means is higher than a predetermined level, and the reception level detection means When the detected reception level is lower than a predetermined level, the mode shifts to another channel frequency search. In the second search mode, the channel search is not shifted according to the reception level. When the frame synchronization based on the detected TMCC signal is established, the digital broadcast wave is determined. When the frame synchronization based on the TMCC signal is not established, the search mode is shifted to a search for another channel frequency.
In this case, the first search mode corresponds to the high-speed search mode, and the second search mode corresponds to the low-speed search mode.

  In the low-speed search mode, in the channel search processing 300 according to the first embodiment of the present invention, the level determination timer 26, the mode determination timer 27, the frequency synchronization determination timer 28 (and the timing synchronization determination timer 29), and the respective timeouts. Set the time longer than the fast search mode. For example, the timeout time of the level determination timer 26 is changed from 100 ms to 200 ms so as to increase the detection time.

  Further, when the mode determination of the second stage processing of the channel search processing 300 is used as the setting of the high speed search mode and the low speed search mode, there are the following methods. In the mode determination, whether or not the transmission mode can be detected is detected while changing each combination of the transmission mode and the guard interval. This detection is used. For example, it is conceivable that the number of detections is set to 1 in the high-speed search mode, and is set to 3 in the low-speed search mode.

  In FIG. 6, search mode setting (2) search modes include a fixed reception mode and a mobile reception mode.

  The fixed reception mode is a case of receiving with an antenna fixed in a room or the like. A search is performed in the channel search process 300 of the first embodiment of the present invention.

  The mobile reception mode is a case of receiving while moving in a car or the like or a case of mobile reception that is received by hand. In this case, because of the influence of fading, the variation of the AGC level signal a is larger than that in the fixed reception mode, and it is difficult to determine the presence / absence of a broadcast wave using the AGC level signal a. To do. The exclusion is performed by switching the level determination connection switching unit 31. Alternatively, the level determination timer 26, the mode determination timer 27, the frequency synchronization determination timer 28 (timing synchronization determination timer 29), the TMCC frame synchronization determination timer 30, and the respective timeout times are compared in the case of the fixed reception mode. It is also possible to take longer.

  Next, the operation of the channel search process 400 of the second embodiment will be described using the flowcharts of FIGS. The channel search processing 400 of the second embodiment performs channel search and records channels that have been successfully received in the broadcast wave in the channel selection success list, skips channels that have been successfully selected in the past, and can be newly tuned. Only select the channel. This channel search mode is called an additional search mode.

  7 and 8, the CPU 13 notifies the broadcast wave determination unit 20 that the channel selection has been started by the broadcast wave determination circuit control signal, and starts the channel search processing program 400.

  When the broadcast wave determination unit 20 knows from the CPU 13 that the channel selection has been started by the broadcast wave determination circuit control signal, it first sets the first channel (channel 13) as the channel selection frequency (frequency) of the tuner 1 ( Step S401). Next, it is determined whether or not the channel is in the channel selection success list (step S402). If it is determined that the channel is in the channel selection success list, the process proceeds to step S420.

If it is determined that the channel is not in the channel selection success list, the process proceeds to step S403. Since the process of step S403-step S418 is the same as the process of step S302-step S317 of the channel search process 300, description is abbreviate | omitted. (Steps S403 to S406 are steps S302 to S305, steps S407 to S410 are steps S306 to S309, steps S411 to S414 are steps S310 to S313, and steps S415 to S418 are steps S314 to S314. (S317 corresponds to each)
When the elapse of the timeout time is detected in any of step S406, step S410, step S414, and step S418, the process proceeds to step S420.

  In step S416, when it is determined that the TMCC frame synchronization detection signal e is “H” and the digital broadcast wave is present and the search channel selection is successful, the channel is added to the channel selection success list. (Step S419) to step S420.

  In step S420, the next channel frequency is set. Subsequently, it is determined whether or not the set channel is the last next channel (step S421). If it is determined that the channel is not the last next channel, the process returns to step S402 to repeat the processes after step S402. If it is determined that the channel is the last channel, the channel search process 400 is terminated.

  The CPU 13 can view a receivable digital broadcast wave by using the channel selection success list before performing a channel search.

  Next, setting of an additional search mode for performing the channel search process 400 of the second embodiment described above will be described with reference to FIG.

  In FIG. 9, the search mode setting (3) search mode includes an additional search mode and a new search mode.

  In the new search mode, a search is performed by the channel search processing 300 of the first embodiment of the present invention.

  In the additional search mode, the channel search processing 400 according to the second embodiment of the present invention performs a search.

  In this embodiment, the AGC level signal, the mode determination detection result signal, and the frequency synchronization detection signal are analog processed as analog signals. However, these signals are digital signals, a register is provided and digital processing is performed by the CPU. A similar search channel selection determination can be considered.

  As described above, according to the present embodiment, it is possible to prevent erroneous determination due to an analog broadcast signal, a noise signal, or the like, accurately determine the presence or absence of a digital broadcast wave, and efficiently determine at high speed. There is.

It is a figure which shows the structure of the digital broadcast receiver of this invention. 2 is a diagram illustrating a configuration of a broadcast wave determination circuit 12. FIG. FIG. 6 is a diagram showing a flowchart (part 1) of a channel search process 300; FIG. 11 is a flowchart (part 2) of a channel search process 300. It is a figure which shows the example of a display of the menu screen of search mode setting (1). It is a figure which shows the example of a display of the menu screen of search mode setting (2). FIG. 10 is a diagram showing a flowchart (part 1) of a channel search process 400; FIG. 11 is a flowchart (part 2) of a channel search process 400. It is a figure which shows the example of a display of the menu screen of search mode setting (3).

Explanation of symbols

1: Tuner 2: A / D converter 3: IQ demodulator 4: AGC control circuit 5: GI removal circuit 6: Mode determination circuit 7: AFC circuit 8: FFT circuit 9: Synchronous reproduction circuit 10
OFDM frame decoding unit 11: TMCC reproduction circuit 12: broadcast wave determination circuit 13: CPU
20: Broadcast wave determination unit 21: Level determination circuit 22: Mode determination circuit 23: Frequency synchronization determination circuit
(24: Timing synchronization judgment circuit)
25: TMCC frame synchronization determination circuit 26: Level determination timer 27: Mode determination timer 28: Frequency synchronization determination timer
(29: Timer for timing synchronization judgment)
30: Timer for TMCC frame synchronization determination 31: Level determination connection switching unit 32: Mode determination connection switching unit 33: Frequency synchronization determination connection switching unit
(34: Timing synchronization determination connection switching unit)
a: AGC level signal b: Mode determination result signal c: Frequency synchronization detection signal d: Timing synchronization detection signal e: TMCC frame synchronization detection signal f: Level determination signal g: Broadcast wave detection signal

Claims (4)

Receiving means for receiving broadcast waves;
Reception level detection means for detecting the reception level of the broadcast wave;
Demodulation means for demodulating the broadcast wave;
Means for switching between at least the first search mode and the second search mode;
In the first search mode, when the reception level detected by the reception level detection means is higher than a predetermined level, the process proceeds to a process for determining whether or not it is a digital broadcast wave, and the reception level is determined in advance. It is a mode to shift to the search of another channel frequency when it is lower than the specified level,
In the second search mode, the channel search based on the reception level is not shifted , and when the frame synchronization based on the TMCC signal detected by the demodulation means is established, it is determined as a digital broadcast wave, and the demodulation is performed. A digital broadcast receiver characterized in that the mode shifts to a search for another channel frequency when frame synchronization is not established based on the TMCC signal detected by the means . The digital broadcast receiver according to claim 1,
Having storage means for storing the channel frequency determined to be a digital broadcast wave;
A digital broadcast receiving apparatus comprising a third search mode for performing a search while skipping channel frequencies stored in the storage means . The digital broadcast receiver according to claim 1,
It is configured to be switchable between fixed reception mode for receiving with a fixed antenna and mobile reception mode for receiving while moving,
In the case of the mobile reception mode, a digital broadcast receiving apparatus that performs a channel frequency search in the second search mode . The digital broadcast receiver according to claim 1,
The digital broadcast receiving apparatus , wherein the determination of the reception level in the first search mode and the determination of frame synchronization in the second search mode are each repeatedly executed within a predetermined time .

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