JP4669652B2 - Fluorescent display tube drive circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a fluorescent display tube driving circuit that improves the reliability of a fluorescent display tube.
[0002]
[Prior art]
A fluorescent fluorescent display (hereinafter referred to as VFD) emits thermoelectrons by applying a voltage to a directly heated cathode called a filament to generate heat by heating the filament in a vacuum vessel. Is a self-luminous display device that displays a desired pattern by accelerating the light with a grid electrode and causing the phosphor on the anode (segment) electrode to collide and emit light. VFD has excellent features such as visibility, multiple colors, low operating voltage, and reliability (environmental resistance), and is used in various applications and fields such as automobiles, home appliances, and consumer use. Has been.
[0003]
Here, in the VFD, when a short circuit or disconnection occurs with respect to the filament and its wiring, when a short circuit occurs between the wiring of the filament and the wiring of another electrode (anode electrode or grid electrode), or the filament is driven. If an abnormal state relating to the filament is left unattended in the case of an element failure or the like, there is a risk that the filament may be damaged or the filament may be ignited. Therefore, a mechanism for quickly detecting an abnormal state related to the filament is required for the VFD.
[0004]
FIG. 7 is a diagram for explaining a conventional mechanism for detecting an abnormality in the filament voltage applied to the filament 11 as one of the mechanisms described above. In the figure, as a method of applying a voltage to the filament 11, a pulse driving method of applying a pulse voltage (hereinafter referred to as a filament pulse voltage) obtained by chopping a DC voltage considerably higher than the normal rated voltage of the filament is used. The example used is shown. That is, in the pulse driving method, when an abnormality occurs such that the filament pulse voltage is fixed on the high potential side, the filament driving method is different from the other methods (direct current (DC) driving method, alternating current (AC) driving method). Since the progress of damage, ignition, etc. is fast, it is an important issue to promptly detect abnormality of the filament pulse voltage.
[0005]
In FIG. 7, an external controller 40 such as a microcomputer outputs a pulse drive signal set to a desired duty ratio to the filament drive circuit 110. The filament driving circuit 110 generates a filament pulse voltage from the power source for driving the filament 11 by a switching operation based on the pulse driving signal received from the external controller 110 and applies the filament pulse voltage to the filament 11. Here, regarding the filament pulse voltage applied to the filament 11, the external controller 40 includes a detection unit that detects, for example, the pulse width and voltage level of the filament pulse voltage. The external controller 40 performs feedback control such as adjusting the setting of the duty ratio of the pulse drive signal output to the filament drive circuit 110 according to the pulse width and voltage level of the filament pulse voltage detected by the detection means. .
[0006]
The conventional mechanism as described above is disclosed in, for example, Patent Document 1 shown below.
[0007]
[Patent Document 1]
JP 2002-108263 A
[0008]
[Problems to be solved by the invention]
As described above, in the conventional mechanism for detecting an abnormality in the filament pulse voltage, the external controller 40 detects the pulse width, voltage level, etc. of the filament pulse voltage, and the filament pulse voltage is detected according to the detected value. Desired feedback control. However, this has been a factor that increases the processing load on the external controller 40. Also, the external controller 40 detects an abnormality of the filament pulse voltage due to an increase in its processing load, and then executes a predetermined process at the time of abnormality (for example, turning off the power of the filament driving circuit 110). It took a considerable amount of time to cause damage to the filament 11 and ignition.
The present invention has been made on the basis of the above-described circumstances, and is to provide a VFD driving circuit that improves the reliability of the VFD.
[0009]
[Means for Solving the Problems]
The main present invention for solving the above problems is to detect that the level of the pulse voltage is fixed in a fluorescent display tube driving circuit for driving the filament of the fluorescent display tube with a pulse voltage. Based on the detection means for outputting a detection signal representing the result of To an external controller that transmits a signal for driving the fluorescent display tube to the fluorescent display tube driving circuit Means for outputting a signal for notifying abnormality of the pulse voltage; And the detection means is a pulse detection means for detecting that the level of the pulse voltage is fixed based on the number of pulses per predetermined period TP of the pulse voltage. I will do it.
The fluorescent display tube driving circuit according to the present invention has the characteristics as described above, thereby reducing the processing load of an external controller such as a microcomputer. This also makes it possible to quickly detect an abnormality in the pulse voltage applied to the filament of the fluorescent display tube, and improve the reliability of the fluorescent display tube (particularly, the reliability of the filament of the fluorescent display tube). be able to.
Other features of the present invention will become apparent from the accompanying drawings and the description of this specification.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
=== Summary of Disclosure ===
The following disclosure will reveal at least the following.
In a fluorescent display tube driving circuit for driving the filament of the fluorescent display tube with a pulse voltage, detection means for detecting that the level of the pulse voltage is fixed and outputting a detection signal representing the result of the detection; And a means for outputting a signal for notifying the abnormality of the pulse voltage based on the detection signal.
[0011]
Here, the aforementioned “detection means” is an “abnormality detection means” described later, and outputs an “abnormality detection signal” described later as the above-mentioned “detection signal”. The above-mentioned “signal for notifying the abnormality of the pulse voltage” is, for example, data of an “abnormality detection flag ANF” output to an external controller described later.
[0012]
The fluorescent display tube driving circuit according to the present invention has the characteristics as described above, thereby reducing the processing load of an external controller such as a microcomputer. This also makes it possible to quickly detect an abnormality in the pulse voltage applied to the filament of the fluorescent display tube, and improve the reliability of the fluorescent display tube (particularly, the reliability of the filament of the fluorescent display tube). be able to.
[0013]
In the second aspect of the present invention, the detection means is pulse detection means for detecting that the level of the pulse voltage is fixed based on the number of pulses per predetermined period TP of the pulse voltage.
[0014]
In the third aspect of the present invention, the pulse detecting means counts the number of pulses per predetermined period TP of the pulse voltage, and the counted number of pulses per predetermined period TP is equal to or less than a reference pulse number PN. In this case, the detection signal indicating that the level of the pulse voltage is fixed is output.
The fluorescent display tube driving circuit according to the present invention has the pulse detecting means as described above, and can detect even when the pulse voltage is fixed at either the H level or the L level. is there. Further, since the pulse detection means does not require a “low-pass filter (integration means)” described later, compared with a “level detection means” described later, there is an advantage that the number of parts can be reduced.
[0015]
In the fourth aspect of the present invention, the detection means is a level detection means for detecting that the level of the pulse voltage is fixed based on the level of the DC voltage obtained by integrating the pulse voltage.
[0016]
In the fifth aspect of the present invention, the level detection unit measures a period in which the level of the DC voltage obtained by integrating the pulse voltage is a level indicating that the level of the pulse voltage is fixed, and the measurement When the measured period is equal to or longer than the predetermined period TL, the detection signal indicating that the level of the pulse voltage is fixed is output.
The fluorescent display tube driving circuit according to the present invention can detect that the level of the pulse voltage is fixed by having the level detecting means as described above. In addition, since the amount of power supplied to the filament is limited, the pulse voltage is usually set within a low range (predetermined duty ratio) of about “5 to 20%”. For this reason, by detecting that the level of the pulse voltage is fixed, it is possible to detect whether or not the pulse voltage has a predetermined duty ratio.
[0017]
About the 6th aspect of this invention, based on the pulse number per predetermined period TP of the said pulse voltage, the pulse detection means which detects that the level of the said pulse voltage was fixed, The DC voltage which integrated the said pulse voltage Level detecting means for detecting that the level of the pulse voltage is fixed on the basis of the level of the pulse voltage, and the operation can be switched to either the pulse detecting means or the level detecting means.
[0018]
In the seventh aspect of the present invention, the fluorescent display tube driving circuit receives data for switching to the operation of either the pulse detection means or the level detection means from the outside, and the data received from the outside And a means for switching to the operation of either the pulse detection means or the level detection means.
Here, the above-mentioned “data received from the outside” refers to “ADS setting data” described later. The above-mentioned “switching means” refers to control means of the fluorescent display tube driving circuit including “abnormality detection means selection means” described later.
In this way, the fluorescent display tube driving circuit according to the present invention has the switching unit as described above, so that either the pulse detection unit or the level detection unit is used to detect the filament of the fluorescent display tube. It is possible to detect that the pulse voltage applied to is fixed. Further, the pulse detection means and the level detection means may be switched alternately and operated in a time division manner.
[0019]
According to an eighth aspect of the present invention, the fluorescent display tube driving circuit is a semiconductor integrated circuit that outputs a pulse driving signal for pulse driving the filament, and is configured to generate the pulse voltage based on the pulse driving signal. The element can be connected to the outside.
The above-mentioned “switching element” is, for example, a Pch-MOS type FET or an Nch-MOS type FET, and the fluorescent display tube driving circuit according to the present invention enables such a switching element to be connected to the outside. An interface (an FPCON terminal described later) may be provided.
[0020]
According to a ninth aspect of the present invention, the fluorescent display tube driving circuit outputs a pulse driving signal for pulse driving the filament, and includes a switching element that generates the pulse voltage based on the pulse driving signal.
[0021]
As described above, in the present invention, various application circuits (for example, a fluorescent display tube module) using the fluorescent display tube driving circuit according to the present invention may be provided with the switching elements as described above. Preferably, as a tenth aspect of the present invention, the fluorescent display tube driving circuit is a semiconductor integrated circuit, and the switching element may be connected to the outside. As an eleventh aspect of the present invention, the fluorescent display tube driving circuit may be The display tube driving circuit may be a semiconductor integrated circuit in which the switching elements are integrated.
[0022]
In the twelfth aspect of the present invention, the fluorescent display tube driving circuit is a semiconductor integrated circuit, and integration means for integrating the pulse voltage into a DC voltage can be connected to the outside.
The above-mentioned “integrating means” refers to a “low-pass filter” described later, and the fluorescent display tube driving circuit according to the present invention is an interface that allows such integrating means to be connected to the outside (described later, DETIN). Terminal).
[0023]
According to a thirteenth aspect of the present invention, there is provided integration means for integrating the pulse voltage into a DC voltage.
[0024]
Thus, in the present invention, various application circuits (for example, a fluorescent display tube module) using the fluorescent display tube driving circuit according to the present invention may be provided with an integration unit as described above. Preferably, as a fourteenth aspect of the present invention, the fluorescent display tube driving circuit is a semiconductor integrated circuit, and the integrating means may be connected to the outside. In the fifteenth aspect of the present invention, The display tube driving circuit may be a semiconductor integrated circuit in which the integrating means is integrated.
[0025]
=== Example ===
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0026]
<System configuration>
FIG. 1 is a schematic configuration diagram of a system including a VFD driving circuit 20 according to an embodiment of the present invention. In the VFD drive circuit 20 shown in the figure, a pulse drive system is adopted as a system for applying a voltage to the filament 11. The pulse driving method is a method in which a pulse voltage (hereinafter referred to as a filament pulse voltage) obtained by chopping a DC voltage that is considerably higher than the normal rated voltage of the filament 11 is applied to the filament 11.
[0027]
Further, the VFD drive circuit 20 shown in the figure employs a dynamic drive system for driving the grid electrode 12 and the segment electrode 13, and sets the number of display digits by the grid electrode 12 to “2” digits (such grid electrode 12 The form is called "1/2 duty"), and the number of segments is "90". Note that the VFD driving circuit 20 according to the present invention is not limited to the number of grids (two digits) and the number of segments (90 segments) described above, and the driving of the grid electrodes 12 and the segment electrodes 13 is dynamic driving. A driving method combining at least one of a method and a static driving method may be used. For example, when the static drive method is adopted, all the digits are displayed by the segment electrodes 13 and one grid electrode 12 corresponding to the number of segments. In this case, a constant voltage (grid voltage) is applied to one grid electrode 12.
[0028]
An outline of the dynamic drive method and the static drive method is described in, for example, “Display Technology Series Fluorescent Display Tube 8.2 Basic Drive Circuit (pages 154 to 158)” issued by Sangyo Tosho.
[0029]
Next, regarding the peripheral circuits of the VFD driving circuit 20, the VFD 10, the external oscillator 30, the external controller 40, the switching element 50, the low-pass filter 60, and the switch means 70 will be described in order.
[0030]
The VFD 10 includes a filament 11, a grid electrode 12, and a segment (anode) electrode 13. The filament 11 is heated by applying a filament pulse voltage from the VFD driving circuit 20 via the switching element 50 based on a pulse driving method, and emits thermoelectrons. The grid electrode 12 acts as an electrode for selecting a digit, and accelerates or blocks the thermal electrons emitted from the filament 11. The segment electrode 13 functions as a segment selection electrode. The surface of the segment electrode 13 is coated with a phosphor in the shape of a pattern to be displayed. The thermoelectrons accelerated by the grid electrode 12 are caused to collide with the phosphor to emit light. Will be displayed.
[0031]
Further, in the VFD 10, lead wires are independently drawn from the grid electrode 12 for each digit independently, while the segments corresponding to each digit are internally connected in common from the segment electrode 13 to lead out the lead wires. It is. The lead wires drawn out from the grid electrode 12 and the segment electrode 13 are respectively connected to corresponding output terminals of the VFD drive circuit 20 (the grid output terminals are G1 to G2 and the segment output terminals are S1 to S45).
[0032]
The external oscillator 30 is RC oscillating means constituted by a resistor R, a capacitive element C, and the like, and constitutes an RC oscillating circuit by being connected to an oscillator terminal (OSCI terminal, OSCO terminal) of the VFD driving circuit 20. . The external oscillator 30 may be a crystal resonator or a ceramic resonator having a specific oscillation frequency, and may constitute a crystal or ceramic oscillation circuit as a free-running oscillation means. In addition, the external oscillator 30 may be a separate oscillation means for supplying a clock signal for other oscillation to the VFD drive circuit 20.
[0033]
The external controller 40 is a microcomputer or the like that does not include a VFD drive element, and is connected to the VFD drive circuit 20 via a data bus for serial data transfer, in order to drive the VFD 10 in a predetermined data transfer format. Necessary signals are transmitted to the VFD driving circuit 20. The data transfer between the external controller 40 and the VFD drive circuit 20 is not limited to the serial data transfer described above, and may be a parallel data transfer.
[0034]
The switching element 50 is a Pch MOS type FET, and its gate terminal is connected to the FPCON terminal of the VFD drive circuit 20 that outputs a pulse drive signal described later. The switching element 50 is not limited to a Pch MOS type FET. For example, the switching element 50 may be configured by an Nch MOS type FET, or may be configured by combining an Nch MOS type FET and a Pch MOS type FET. . The switching element 50 is turned on / off (switching) in accordance with a pulse drive signal supplied from the FPCON terminal of the VFD drive circuit 20, whereby a filament pulse applied from the filament power supply voltage VFL to the filament 11 of the VFD 10. Generate voltage.
[0035]
The FPR terminal of the VFD drive circuit 20 shown in FIG. 1 is an input terminal for setting the polarity of the pulse drive signal output from the FPCON terminal according to the input / output characteristics of the switching element 50. For example, as shown in FIG. 1, when a Pch-MOS type FET is adopted as the switching element 50, the power supply voltage VDD ("H" fixed) is connected to the FPR terminal. When an Nch-MOS type FET is adopted as the switching element 50, the FPR terminal is grounded (fixed to “L”).
[0036]
The low-pass filter 60 is an RC integrating circuit composed of a resistor R and a capacitive element C. The input side is connected to the filament pulse voltage output terminal of the switching element 50, and the output side is connected to the DETIN terminal of the VFD drive circuit 20. Connected. The resistor R and the capacitive element C constituting the low-pass filter 60 are each having a rated value large enough to integrate the filament pulse voltage into a DC voltage. That is, when the filament pulse voltage generated by the switching element 50 is input, the low-pass filter 60 integrates the filament pulse voltage to obtain a DC voltage and inputs the voltage to the DETIN terminal of the VFD drive circuit 20. Become.
[0037]
Note that the low-pass filter 60 is an external circuit of the VFD driving circuit 20 that is required in the level detection means described later, and is not required in the pulse detection means described later. Therefore, when using a pulse detection means described later, the low-pass filter 60 may be removed and the filament pulse voltage generated by the switching element 50 may be input to the DETIN terminal of the VFD drive circuit 20.
[0038]
Alternatively, as shown in the figure, when the switch means 70 connected in parallel with the resistance of the low-pass filter 60 (or the low-pass filter 60 itself) is used and the pulse detection means described later is used, the resistance of the low-pass filter 60 is short-circuited. Alternatively, the switch means 70 may be operated so as to short-circuit the low-pass filter 60 itself. In this case, the control signal for operating the switch means 70 may be supplied directly from the external controller 40 to the switch means 70 or supplied from the external controller 40 to the switch means 70 via the VFD drive circuit 20. You may do it.
[0039]
FIG. 2 is a timing chart regarding a data transfer format between the external controller 40 and the VFD driving circuit 20. As shown in the figure, the data transfer format includes a sequence related to the grid electrode G1 (hereinafter referred to as G1 sequence) and a sequence related to the grid electrode G2 (hereinafter referred to as G2 sequence). The data transfer format is not limited to the above-described format, and for example, the G1 sequence and the G2 sequence may be executed in a single sequence.
[0040]
Hereinafter, the G1 sequence and the G2 sequence will be schematically described.
First, the external controller 40 transmits the bus address (8 bits) given to the VFD driving circuit 20 together with the synchronous clock signal CL to the VFD driving circuit 20. The VFD drive circuit 20 identifies whether or not the received bus address is a bus address assigned to itself. Then, if it is identified as the own bus address, a control command (such as control data described later) transmitted along with the bus address received from the external controller 40 is accepted as a control command to itself. As described above, the bus address is a unique address given to each IC. In the embodiment in which the external controller 40 and a plurality of ICs are connected on the same bus line, the external controller 40 This is used to control a plurality of ICs on the same bus line.
[0041]
Next, the external controller 40 asserts the chip enable signal CE (sets it to the H level) to enable (select) the VFD drive circuit 20, and subsequently, 45-bit display data (D1 to D45) related to the grid electrode G1. ), 16-bit control data used for each control of the VFD drive circuit 20 is transmitted. The 16-bit control data includes 10-bit dimmer adjustment data (DM0 to DM9) as brightness adjustment data for VFD10 display, grid identifier DD (for example, “1” for grid electrode G1, grid electrode G2) In the case of “0”).
Thereafter, the external controller 40 negates the chip enable signal CE (sets it to the L level), disables the VFD drive circuit 20 (non-selection), stops transmission of the synchronous clock signal CL, and executes the G1 sequence. It will be completed.
[0042]
On the other hand, in the G2 sequence, 45-bit display data (D46 to D90) related to the grid electrode G2 is transmitted in the same procedure as the G1 sequence described above. In the G2 sequence, the control data transmitted to the VFD drive circuit 20 includes ADS (Abnormal Detect type Select) setting data described later.
[0043]
<VFD drive circuit>
FIG. 3 is a block diagram of the VFD driving circuit 20 according to the present invention.
The VFD driving circuit 20 includes an interface unit 201, an oscillation circuit 202, a frequency dividing circuit 203, a timing generator 204, a shift register 205, a control register 206, a latch circuit 207, a multiplexer 208, a segment driver 209, a grid driver 210, and a dimmer control unit. 211, filament pulse control means 212, and abnormality detection means 213.
[0044]
The interface unit 201 is interface means for transmitting and receiving data to and from the external controller 40 as shown in FIG.
The oscillation circuit 202 generates a reference clock signal related to the VFD drive circuit 20 by connecting the external oscillator 30 to the oscillator terminals (OSCI, OSCO). This reference clock signal is frequency-divided into a predetermined frequency by the frequency divider 203 and supplied to the timing generator 204.
The timing generator 204 is a signal (hereinafter referred to as an internal signal) that determines the timing of a signal for driving the grid electrodes G1 to G2 (hereinafter referred to as a grid drive signal) based on the signal supplied from the frequency dividing circuit 203. A clock signal A), and a filament pulse control means 212 outputs a signal for determining the timing of the pulse drive signal (hereinafter referred to as an internal clock signal B).
[0045]
The shift register 205 receives 45-bit display data (D1 to D45 or D46 to D90) and 16-bit control data (dimer adjustment data (DM0 to DM9)) received by the interface unit 201 for each G1 or G2 sequence described above. Etc.) are converted into parallel data and supplied to the control register 206, the latch circuit 207, the filament pulse control means 212, and the like.
The control register 206 stores 32 (16 bits × 2) bits of control data supplied from the shift register 205. The dimmer adjustment data (DM0 to DM9) included in the control data is supplied to the dimmer control means 211.
[0046]
The latch circuit 207 holds 45-bit display data (D1 to D45) related to the grid electrode G1 and 45-bit display data (D46 to D90) related to the grid electrode G2 supplied from the shift register 205. That is, the latch circuit 207 holds 90-bit display data (D1 to D90) for each repetition period related to driving of the grid electrodes G1 to G2.
[0047]
The multiplexer 208 relates to the grid electrode G1 or G2 to be driven out of the 90-bit display data (D1 to D90) held by the latch circuit 207 at the timing of driving the grid electrodes G1 to G2. 45-bit display data is selected and supplied to the segment driver 209.
[0048]
The segment driver 209 forms a signal for driving the segment electrodes S1 to S45 based on the 45-bit display data selected and supplied by the multiplexer 208, and outputs the signal to the segment electrodes S1 to S45. The signal for driving the segment electrodes S1 to S45 may be a voltage applied to the segment electrodes S1 to S45 (hereinafter referred to as segment voltage), or a driving element between the segment driver 209 and the segment electrodes S1 to S45. May be used as a control signal supplied to the drive element (hereinafter, the segment voltage and the control signal are collectively referred to as a segment drive signal).
[0049]
The grid driver 210 forms a grid drive signal based on the internal clock signal A supplied from the timing generator 204 and outputs it to the grid electrodes G1 to G2. The signal for driving the grid electrodes G1 to G2 may be a voltage applied to the grid electrodes G1 to G2 (hereinafter referred to as a grid voltage), or a drive element between the grid driver 210 and the grid electrodes G1 to G2. And a control signal supplied to the drive element (hereinafter, the grid voltage and the control signal are collectively referred to as a grid drive signal).
[0050]
The dimmer control means 211 can adjust the duty ratio of the grid drive signal and the segment drive signal based on the dimmer adjustment data (DM0 to DM9) supplied from the control register 206.
[0051]
The filament pulse control means 212 forms a pulse drive signal for driving the filament 11 based on the internal clock signal B supplied from the timing generator 204 and outputs the pulse drive signal to the switching element 50 via the FPCON terminal. Further, the filament pulse control means 212 sets the polarity of the pulse drive signal based on the signal supplied from the FPR terminal.
The abnormality detection means 213 is a means for detecting that the filament pulse voltage level is fixed and outputting a signal for notifying the abnormality of the filament pulse voltage.
[0052]
The VFD driving circuit 20 shown in the figure has a BLK terminal for turning on or off the VFD display. The BLK terminal is connected so that data is supplied from the external controller 40. For example, when “1” is supplied from the external controller 40 to the BLK terminal, each control unit operates so as to fix the above-described grid drive signal and segment drive signal to the L level and the pulse drive signal to the H level. The VFD display can be turned off.
Hereinafter, the abnormality detection means 213 that performs characteristic operations in the present invention will be described.
[0053]
<Abnormality detection means>
A circuit configuration as one embodiment of the abnormality detection means 213 according to the present invention will be described with reference to FIG.
The abnormality detection means 213 includes a pulse detection means 80, a level detection means 90, and a selection means 100 as shown in FIG.
The pulse detecting means 80 is means for detecting that the level of the filament pulse voltage is fixed based on the number of pulses per predetermined period TP of the filament pulse voltage input from the DETIN terminal.
The level detecting means 90 is means for detecting that the level of the filament pulse voltage is fixed based on the level of the DC voltage obtained by integrating the filament pulse voltage input from the DETIN terminal.
[0054]
By the way, the level of the DC voltage is normally set within a low range where the duty ratio of the filament pulse voltage is about “5 to 20%” because the amount of power supplied to the filament 11 is limited. For this reason, it is lower than the maximum value VILmax of the input voltage recognized as L level in the IC (Integrated Circuit) in the VFD driving circuit 20. That is, when the filament pulse voltage is normal, the level of the DC voltage is recognized as the L level in the IC in the VFD drive circuit 20.
Further, the level of the DC voltage is higher than the minimum value VIHmin of the input voltage that is recognized as H level in the IC in the VFD drive circuit 20 when an abnormality occurs in which the filament pulse voltage is fixed at H level. Therefore, it is recognized as the H level.
In this way, the level detection means 90 can detect that the filament pulse voltage is fixed based on the level of the DC voltage.
[0055]
For example, when the ADS setting data is “0”, the selection unit 100 detects the level based on the ADS (Abnormal Detect type Select) setting data included in the control data of the G2 sequence received from the external controller 40. The output of the means 90 is selected. In the case of “1”, the output of the pulse detecting means 80 is selected. The selection unit 100 outputs the output of the selected level detection unit 90 or pulse detection unit 80 as an abnormality detection signal. The abnormality detection signal is output from the DO terminal to the external controller 40 as an abnormality detection flag ANF (for example, “1” at normal time, “0” at abnormal time).
[0056]
Thus, the VFD drive circuit 20 according to the present invention can reduce the processing load of the external controller 40 such as a microcomputer. This also makes it possible to quickly detect that the level of the filament pulse voltage is fixed (abnormality), and improve the reliability of the VFD 10 (particularly, the reliability of the VFD 10 with respect to the filament 11). .
Below, the circuit structure as one embodiment of each of the pulse detection means 80 and the level detection means 90 is demonstrated.
[0057]
<Pulse detection means>
First, a circuit configuration as one embodiment of the pulse detection means 80 will be described with reference to FIG.
The pulse detection unit 80 includes a first count unit 801, a D flip-flop 802, and an RS flip-flop 803.
[0058]
The first counting unit 801 counts the number of pulses per predetermined period TP of the filament pulse voltage input from the DETIN terminal, and if the counted number is equal to or less than the reference pulse number PN, One level (for example, “1”) indicating that the level is fixed is output. When the count number exceeds or exceeds the reference pulse number PN, the other level (eg, “0”) indicating that the filament pulse voltage is normal is output.
[0059]
The first counting means 801 resets the count at the timing when a signal for specifying the end of the predetermined period TP (hereinafter referred to as an internal reset signal (FIG. 5B)) rises. Here, the predetermined period TP is, for example, a period for driving each of the grid electrodes G1 to G2. Further, the reference pulse number PN is set to about 9 pulses assuming that noise is counted.
[0060]
The D flip-flop 802 latches the output of the first count means 801 with the internal reset signal and outputs it to the next stage RS flip-flop 803.
The RS flip-flop 803 is means for holding the output of the D flip-flop 802. The RS flip-flop 803 sets an abnormality detection signal when “1” is input to the S terminal as the output of the D flip-flop 802. The state where the abnormality detection signal is set is held until the BLKIN signal (signal input from the BLK terminal) is input to the R terminal. That is, when the abnormality of the filament pulse voltage is confirmed on the external controller 40 side and “1” is input to the BLK terminal to turn off the display of the VFD 10 as one of the processing modes at the time of abnormality, the abnormality detection signal Will be reset.
[0061]
FIG. 5 is a timing chart for explaining the operation of the pulse detecting means 80. In the figure, the level of the filament pulse voltage (FIG. 5C) input from the DETIN terminal at time t1 in the period for driving the grid electrode G1 (hereinafter referred to as the grid electrode G1 period) is H It is assumed that the level is fixed. Further, during the period from time t0 to time t1, the number of pulses of the filament pulse voltage (FIG. 5C) counted by the first counting means 801 exceeds or exceeds the reference pulse number PN (9 pulses). It shall be.
[0062]
First, in the grid electrode G1 period, as described above, an abnormality occurs in which the level of the filament pulse voltage (FIG. 5C) is fixed at the H level at time t1. However, during the period from time t0 to time t1, the pulse number of the filament pulse voltage (FIG. 5C) counted by the first counting means 801 exceeds or exceeds the reference pulse number PN (9 pulses). . Therefore, at the time when the internal reset signal (FIG. 5B) rises in order to specify the end of the grid electrode G1 period, the output of the first counting means 801 switches from “1” in the initial state to “0”. ing. Therefore, in the D flip-flop 802 and the RS flip-flop 803, “0” is latched by the rising edge of the internal reset signal (FIG. 5B), and as a result, the abnormality detection signal (FIG. 5D) is not set. It will be.
[0063]
Next, at the start time t2 of the period for driving the grid electrode G2 (hereinafter referred to as the grid electrode G2 period), the count number counted by the first counting means 801 is reset in the grid electrode G1 period, The number of pulses of the filament pulse voltage (FIG. 5C) is counted again. Here, according to FIG. 5, the count number counted by the first counting means 801 by the time when the internal reset signal (FIG. 5B) rises to specify the end of the grid electrode G2 period is “0”. “Because it is a pulse (ie, less than or less than the reference pulse number PN), the output of the first counting means 801 remains“ 1 ”. Therefore, “1” is latched in the D flip-flop 802 and the RS flip-flop 803 by the rising edge of the internal reset signal (FIG. 5B), and as a result, the abnormality detection signal (FIG. 5D) is set. It will be.
[0064]
The abnormality detection signal (FIG. 5D) is output from the DO terminal to the external controller 40 as the abnormality detection flag ANF. Then, it is assumed that the external controller 40 that has read the abnormality detection flag ANF outputs “1” to the BLK terminal based on the determination that the display of the VFD 10 is turned off and initialization is performed at time t5. In this case, the abnormality detection signal (FIG. 5D) is reset. By the way, as a process after the abnormality detection flag ANF is read and an abnormality is detected, the display of the VFD 10 may be initialized and then turned on again as described above, or the VFD driving circuit 20 and the switching element 50 may be used as they are. You may turn off the power. This process determination is left to the external controller 40 to the last.
[0065]
As described above, the VFD driving circuit 20 according to the present invention includes the pulse detection unit 80 as described above, so that the filament pulse voltage is fixed at either the H level or the L level. Even if it exists, it is detectable.
Further, since the pulse detection unit 80 does not require the low-pass filter 60 as compared with the level detection unit 90, there is an advantage that the number of parts can be reduced.
[0066]
<Level detection means>
Next, a circuit configuration as an embodiment of the level detection means 90 will be described with reference to FIG.
The level detection unit 90 includes a second counter unit 901 and an RS flip-flop 902.
[0067]
The second counter means 901 is a counter when the level of the DC voltage obtained by integrating the filament pulse voltage input from the DETIN terminal becomes a level (for example, H level) indicating that the filament pulse voltage is fixed. Start operation.
[0068]
Further, the second counter means 901 sets a period during which the level of the DC voltage becomes a level (for example, H level) indicating that the filament pulse voltage is fixed based on the internal clock signal CX having a predetermined cycle TX. Count. A period obtained by multiplying the counted number by the period TX of the internal clock signal CX is a predetermined period TL (for example, about “408 / 3072≈0.133” times the period for driving the grid electrodes G1 to G2, respectively). When it is above or above, one level (for example, “1”) indicating that the filament pulse voltage is abnormal is output.
[0069]
On the other hand, when the period obtained by multiplying the counted number by the period TX is less than or less than the predetermined period TL, the second counter unit 901 displays the other level indicating that the filament pulse voltage is normal (for example, "0") is output. The counted number is reset when the level of the DC voltage becomes a level indicating that the filament pulse voltage is normal (for example, L level).
[0070]
The RS flip-flop 902 is a unit that holds the output of the second counter unit 901. The RS flip-flop 902 sets an abnormality detection signal when “1” is input to the S terminal as the output of the second counter unit 901, similarly to the RS flip-flop 803 of the pulse detection unit 80 described above. The state where the abnormality detection signal is set is held until the BLKIN signal is input to the R terminal.
[0071]
FIG. 6 is a timing chart for explaining the operation of the level detection means 90. It is assumed that the filament pulse voltage (FIG. 6B) input from the DETIN terminal is fixed at the H level at time t1.
[0072]
First, during the period from time t0 to time t1, the level of the DC voltage (FIG. 6C) is in the L level indicating that the filament pulse voltage (FIG. 6B) is normal. The second counter unit 901 does not start the counter operation. For this reason, the RS flip-flop 902 does not operate, and the abnormality detection signal (FIG. 6D) is not set.
[0073]
Next, at time t1, the level of the filament pulse voltage (FIG. 6B) is fixed to the H level, and the level of the DC voltage (FIG. 6C) is changed to the filament pulse voltage (FIG. B)) is fixed to the H level indicating that it is abnormal. Here, the second counter means 901 performs a counting operation for counting a period in which the level of the DC voltage (FIG. 6C) is H level based on the internal clock signal CX having a predetermined period TX. Start.
[0074]
Next, at the time t2, the count number counted from the time t1 by the second counter unit 901 exceeds or exceeds the reference count number ("17" in the circuit example shown in FIG. 4) corresponding to the predetermined period TL. Therefore, the second counter unit 901 outputs “1” indicating that the filament pulse voltage is abnormal. The output of the second counter means 901 is input to the S terminal of the RS flip-flop 902, and the abnormality detection signal (FIG. 6D) is set.
[0075]
The abnormality detection signal (FIG. 6D) is output from the DO terminal to the external controller 40 as the abnormality detection flag ANF. Then, it is assumed that the external controller 40 that has read the abnormality detection flag ANF outputs “1” to the BLK terminal based on the determination that the display of the VFD 10 is turned off and initialization is performed at time t3. In this case, the abnormality detection signal (FIG. 6D) is reset. By the way, as a process after the abnormality detection flag ANF is read and an abnormality is detected, the display of the VFD 10 may be initialized and then turned on again as described above, or the VFD driving circuit 20 and the switching element 50 may be used as they are. You may turn off the power. This process determination is left to the external controller 40 to the last.
[0076]
In this way, the VFD driving circuit 20 according to the present invention includes the level detecting unit 90 as described above, so that it can detect that the level of the filament pulse voltage is fixed, and the filament pulse voltage is normal. It can also be detected that the duty ratio is “5 to 20%”.
[0077]
=== Other Embodiments ===
In the VFD driving circuit 20 according to the present invention as described above, in the pulse detection means 80, the number of pulses per predetermined period TP of the filament pulse voltage is a specified number of pulses (for example, the period of the predetermined period TP / reference clock signal). ) An abnormality detection signal may be set when the number is greater than or equal to.
[0078]
For example, it may be assumed that the number of pulses per predetermined period TP of the filament pulse voltage is equal to or greater than the specified number of pulses due to the case where pulsed noise having a phase shift is superimposed on the filament pulse voltage. Therefore, the VFD driving circuit 20 according to the present invention can detect that the filament pulse voltage is fixed when the number of pulses per predetermined period TP of the filament pulse voltage is greater than or equal to the specified number of pulses.
[0079]
In the embodiment described above, the VFD driving circuit 20 according to the present invention includes both the pulse detection unit 80 and the level detection unit 90 in the abnormality detection unit 213, and the pulse detection unit 80 or the level detection unit 90. However, you may make it provide only one of the pulse detection means 80 or the level detection means 90. Alternatively, the pulse detection means 80 and the level detection means 90 may be alternately switched and operated in a time division manner.
[0080]
In the above-described embodiment, the switching element 50 may be provided for various application circuits (for example, a fluorescent display tube module) using the VFD drive circuit 20 according to the present invention. Preferably, the VFD drive circuit 20 may be a semiconductor integrated circuit, and the switching element 50 may be connected to the outside, or may be a semiconductor integrated circuit that includes the integrated switching element 50.
[0081]
Further, when the level detector 90 is operated as the above-described embodiment, the low-pass filter 60 is provided for various application circuits (for example, fluorescent display tube modules) using the fluorescent display tube driving circuit according to the present invention. It may be. Preferably, the VFD driving circuit 20 is a semiconductor integrated circuit, and may be connected to the low-pass filter 60 or may be a semiconductor integrated circuit incorporating the integrated low-pass filter 60.
[0082]
【The invention's effect】
ADVANTAGE OF THE INVENTION According to this invention, the fluorescent display tube drive circuit which improves the reliability of a fluorescent display tube can be provided.
[Brief description of the drawings]
FIG. 1 is a schematic configuration diagram of a system including a fluorescent display tube driving circuit according to an embodiment of the present invention.
FIG. 2 is a timing chart regarding a data transfer format between an external controller and a fluorescent display tube driving circuit according to an embodiment of the present invention.
FIG. 3 is a block diagram of a fluorescent display tube driving circuit as an embodiment according to the present invention.
FIG. 4 is a circuit configuration diagram of abnormality detection means as an embodiment according to the present invention.
FIG. 5 is a timing chart for explaining the operation of the pulse detecting means as one embodiment according to the invention.
FIG. 6 is a timing chart for explaining the operation of the level detection means as one embodiment according to the invention.
FIG. 7 is a diagram for explaining a conventional mechanism for detecting an abnormality in a filament pulse voltage.
[Explanation of symbols]
10 VFD 11 filament
12 Grid electrode 13 Segment electrode
20 VFD drive circuit 201 Interface section
202 Oscillator circuit 203 Divider circuit
204 Timing generator 205 Shift register
206 Control register 207 Latch circuit
208 Multiplexer 209 Segment driver
210 Grid driver 211 Dimmer control means
212 Filament pulse control means 213 Abnormality detection means
30 External oscillator 40 External controller
50 switching element 60 low-pass filter
70 Switch means
80 Pulse detection means 801 First counter means
802 D flip-flop 803 RS flip-flop
90 level detection means
901 Second counter means 902 RS flip-flop
100 selection means

Claims (12)

In a fluorescent display tube driving circuit for driving a filament of a fluorescent display tube with a pulse voltage,
Detecting means for detecting that the level of the pulse voltage is fixed and outputting a detection signal representing the result of the detection;
Means for outputting a signal for notifying the abnormality of the pulse voltage to an external controller that transmits a signal for driving the fluorescent display tube to the fluorescent display tube driving circuit based on the detection signal; ,
The fluorescent display tube driving circuit according to claim 1, wherein the detecting means is pulse detecting means for detecting that the level of the pulse voltage is fixed based on the number of pulses per predetermined period TP of the pulse voltage. The pulse detection means includes
The number of pulses per predetermined period TP of the pulse voltage is counted, and the level of the pulse voltage is fixed when the counted number of pulses per predetermined period TP is less than or less than a reference pulse number PN. The fluorescent display tube driving circuit according to claim 1, wherein the detection signal is output. In a fluorescent display tube driving circuit for driving a filament of a fluorescent display tube with a pulse voltage,
Detecting means for detecting that the level of the pulse voltage is fixed and outputting a detection signal representing the result of the detection;
Means for outputting a signal for notifying the abnormality of the pulse voltage to an external controller that transmits a signal for driving the fluorescent display tube to the fluorescent display tube driving circuit based on the detection signal; ,
The detection means includes
The pulse based voltage on the level of integration the direct current voltage, fluorescent display tube drive circuit you wherein the level of the pulse voltage is at the level detecting means for detecting that it has been fixed. The level detecting means includes
A period in which the level of the DC voltage obtained by integrating the pulse voltage is a level indicating that the level of the pulse voltage is fixed is measured, and when the measured period is equal to or more than a predetermined period TL, the pulse 4. The fluorescent display tube driving circuit according to claim 3, wherein the detection signal indicating that the voltage level is fixed is output. In a fluorescent display tube driving circuit for driving a filament of a fluorescent display tube with a pulse voltage,
Detecting means for detecting that the level of the pulse voltage is fixed and outputting a detection signal representing the result of the detection;
Means for outputting a signal for notifying the abnormality of the pulse voltage to an external controller that transmits a signal for driving the fluorescent display tube to the fluorescent display tube driving circuit based on the detection signal; ,
The detection means includes
Based on the number of pulses per predetermined period TP of the pulse voltage, pulse detection means for detecting that the level of the pulse voltage is fixed, and on the basis of the level of the DC voltage obtained by integrating the pulse voltage, a level detecting means for detecting that the level is fixed, the said pulse detection means or the level or to be switched to one of operations you wherein fluorescent display tube drive circuit of the detection means . The fluorescent display tube driving circuit includes:
Data for switching to the operation of either the pulse detection means or the level detection means is received from the outside, and the operation of either the pulse detection means or the level detection means is based on the data received from the outside The fluorescent display tube driving circuit according to claim 5, further comprising means for switching to The fluorescent display tube driving circuit is a semiconductor integrated circuit that outputs a pulse driving signal for pulse driving the filament, and a switching element that generates the pulse voltage based on the pulse driving signal can be connected to the outside. fluorescent display driving circuit according to any one of claims 1 to 6, wherein. A said fluorescent display driving circuit which outputs a pulse driving signal for pulse driving the filament, claims 1 to 6, wherein a switching element for generating the pulse voltage based on the pulse driving signal A fluorescent display tube driving circuit according to any one of the above.   9. The fluorescent display tube driving circuit according to claim 8, wherein the fluorescent display tube driving circuit is a semiconductor integrated circuit, and the switching element is connected to the outside. 9. The fluorescent display tube driving circuit according to claim 8 , wherein the fluorescent display tube driving circuit is a semiconductor integrated circuit in which the switching elements are integrated. 7. The fluorescent display tube driving circuit is a semiconductor integrated circuit, and integrating means for integrating the pulse voltage into a DC voltage can be connected to the outside . 2. A fluorescent display tube driving circuit according to 1. 7. The fluorescent display tube driving circuit according to claim 3, further comprising integrating means for integrating the pulse voltage into a DC voltage.

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