JP4670243B2 - Manufacturing method of EEPROM - Google Patents

Description

  The present invention relates to a method of manufacturing a semiconductor device such as an EEPROM (electrically erasable / programmable read-only memory).

  Conventionally, in an EEPROM, a connection hole that exposes the shoulder of the lower gate electrode layer is provided in an insulating film that covers the lower gate electrode layer, and an upper gate electrode layer is connected to the lower gate electrode layer through the connection hole. There is known a type in which information is written and erased by transferring electrons by a tunnel phenomenon between floating gate electrodes formed by lower and upper gate electrode layers (see, for example, Patent Document 1). ). FIG. 22 shows an example of this type of EEPROM. FIG. 23 shows a cross section taken along line X-X 'of FIG. 22, and FIG. 24 shows a cross section taken along line Y-Y' of FIG. 22 to 24, the gate electrode layers 3A and 9B correspond to the aforementioned lower and upper gate electrode layers, respectively.

  On the surface of the silicon substrate 1, electrode layers 3A and 3B made of doped polysilicon are formed through gate insulating films 2a and 2b made of silicon oxide, respectively. On the surface of the substrate 1, portions other than the arrangement portions of the gate electrode layers 3A and 3B are covered with an insulating film 6 made of silicon oxide. The insulating film 6 is slightly thicker than the gate insulating film such as 2a.

  An insulating film 4A made of silicon oxide is formed on the upper surface of the gate electrode layer 3A, and side portions of the gate electrode layer 3A are covered with insulating films 6a, 6b, 6e, and 6f made of silicon oxide. An insulating film 4B made of silicon oxide is formed on the upper surface of the gate electrode layer 3B, and side portions of the gate electrode layer 3B are covered with insulating films 6c and 6d made of silicon oxide. In FIG. 23, the left shoulders of the insulating films 4A and 4B are both thin in order to facilitate the flow of the tunnel current.

  The gate electrode layer 9A made of doped polysilicon is formed on the insulating films 4A, 6, 6a, 6e, and 6f so as to partially overlap the gate electrode layer 3A. The electrode layer 9B made of doped polysilicon is formed on the insulating films 4A, 6, 6b, 6e, and 6f so that a part thereof overlaps the gate electrode layer 3A, and the other part is formed on the gate electrode layer 3B. It is formed on the insulating films 4B, 6 and 6c so as to overlap. The gate electrode layer 9B is connected to the gate electrode layer 3A through connection holes provided in the insulating films 4A and 6b corresponding to the shoulders of the gate electrode layer 3A. The floating gate electrode is connected to the gate electrode layer 3A together with the gate electrode layer 3A. Constitute. The gate electrode layer 3B is used as an isolation line, and the gate electrode layer 9A is used as a word line.

  As a manufacturing method of the MOS type transistor portion of the EEPROM as described above, the one shown in FIGS. 25 to 33 has been proposed. 25 to 33, the gate electrode layer 3B is not shown for simplicity.

  In the process shown in FIG. 25, after an insulating film 2 made of silicon oxide is formed on the surface of the silicon substrate 1 by a thermal oxidation method, a polysilicon layer 3 is formed on the insulating film 2 by a CVD (chemical vapor deposition) method. Form. During or after the deposition of the polysilicon layer 3, the polysilicon layer 3 is doped with a conductivity-determining impurity, so that the resistance of the polysilicon layer 3 is reduced to such an extent that it can be used as a gate electrode layer.

  Next, an insulating film 4 made of silicon oxide is formed on the surface of the doped polysilicon layer 3 by a thermal oxidation method. Then, a resist layer 5 is formed on the insulating film 4 in accordance with a desired gate electrode pattern.

  In the process of FIG. 26, the insulating film 4 is selectively removed by isotropic wet etching using the resist layer 5 as a mask and HF (hydrofluoric acid) as an etchant, and a part 4A of the insulating film 4 is interlayer-insulated. It remains as a film. At this time, the corners of the insulating film 4A are relaxed by side etching.

  In the step of FIG. 27, the polysilicon layer 3 is selectively removed by anisotropic dry etching using the resist layer 5 and the insulating film 4A as a mask, and a part 3A of the polysilicon layer 3 remains as a gate electrode layer. Let

  In the step of FIG. 28, after removing the resist layer 5 by ashing or the like, insulating films 6, 6a, 6b made of silicon oxide are formed by thermal oxidation. The insulating film 6 is formed on a portion of the substrate surface other than the portion where the gate electrode layer 3A is disposed, and is formed continuously and thicker than the gate insulating film 2a immediately below the electrode layer 3A. The insulating films 6a and 6b are formed on the side portions of the gate electrode layer 3A. At this time, insulating films 6e and 6f made of silicon oxide are also formed on the side portions of the gate electrode layer 3A as shown in FIG.

In the step of FIG. 29, the resist layer 7 is formed on the upper surface of the substrate by a spin coating method or the like. Then, the resist layer 7 is thinned by half etching treatment or half ashing treatment until the shoulder portion of the insulating film 4A is exposed, so that the thin resist layer 7 is left around the gate electrode layer 3A. The half etching process is performed by a batch process in which a large number of wafers to be processed (corresponding to the substrate 1) are manually immersed in a resist developer. The half ashing process is performed by irradiating the resist layer with O ₂ (oxygen) plasma in a state where a large number of wafers to be processed are arranged in the ashing chamber of the batch ashing apparatus.

  In the process of FIG. 30, a resist layer 8 having a hole 8a exposing the shoulder portion of the insulating film 4A and a part of the resist layer 7 in the vicinity thereof is formed on the upper surface of the substrate by photolithography.

  In the process of FIG. 31, the insulating films 4A and 6b are selectively removed by an isotropic wet etching process using the resist layers 8 and 7 as a mask and HF as an etchant to expose the shoulder of the gate electrode layer 3A. A connection hole 4a is formed.

32, the resist layers 8 and 7 are removed by ashing or the like. 33, after forming a low-resistance polysilicon (doped polysilicon) layer 9 on the upper surface of the substrate, it corresponds to the gate electrode layers 9A and 9B in FIGS. Resist layers Ra and Rb are formed in a pattern by photolithography. The polysilicon layer 9 is patterned by anisotropic dry etching using the resist layers Ra and Rb as masks to form gate electrode layers 9A and 9B. The gate electrode layer 9B is formed in a form connected to the gate electrode layer 3A through the connection hole 4a.
Japanese Patent No. 2512181

According to the prior art described above, after removing all the resist layers 8 and 7 in the step of FIG. 32, the polysilicon layer 9 is deposited on the upper surface of the substrate in the step of FIG. At this time, the polysilicon layer 9 is formed thick due to a steep step at the side of the gate electrode layer 3A. Therefore, when the polysilicon layer 9 is patterned, as shown in FIGS. 22 and 24 (shown with hatching in FIG. 22), the gate electrode layer 3A has a side portion between the gate electrode layers 9A and 9B as shown in FIG. A part of the polysilicon layer 9 is not etched and remains as etching residues (also called stringers) S ₁ and S ₂ . Such etching residues S ₁ and S ₂ increase the parasitic capacitance of the gate electrode layer 9A or 9B or cause the gate electrode layers 9A and 9B to be short-circuited, resulting in a decrease in manufacturing yield.

  An object of the present invention is to provide a novel method for manufacturing a semiconductor device capable of eliminating an etching residue when an upper gate electrode layer overlapping with a lower gate electrode layer is formed.

The manufacturing method of the first semiconductor device according to the present invention is as follows:
A semiconductor substrate is prepared in which a first gate electrode layer is formed on a first insulating film covering one main surface, and an upper surface and sidewalls of the first gate electrode layer are covered with a second insulating film. And a process of
Forming an insulating layer that covers the first and second insulating films and is thicker than the thickness of the first gate electrode layer and the second insulating film;
Side spacers comprising the remaining portion of the insulating layer are etched back so that a portion of the insulating layer remains in contact with the second insulating film on the side of the first gate electrode layer. Forming a step;
Forming an electrode material layer covering the first and second insulating films and the side spacers;
The electrode material layer is formed by a selective etching process so that a part of the electrode material layer remains in a state of being overlapped with the first gate electrode layer and the side spacer, thereby forming a remaining portion of the electrode material layer. Forming a second gate electrode layer.

  According to the manufacturing method of the first semiconductor device, since the side spacer is formed on the side portion of the first gate electrode layer, the step is reduced on the side portion of the first gate electrode layer. In such a state, when the electrode material layer is formed so as to cover the first and second insulating films and the side spacers, it is possible to suppress the electrode material layer from becoming thick at the side portion of the first gate electrode layer. . Thereafter, when the electrode material layer is patterned by selective etching processing so that a part of the electrode material layer remains in a state of being overlapped with the first gate electrode layer and the side spacer, etching is performed on the side portion of the first gate electrode layer. The rest can be eliminated. Therefore, an increase in parasitic capacitance can be avoided in the second gate electrode layer composed of the remaining portion of the electrode material layer.

The manufacturing method of the second semiconductor device according to the present invention is as follows:
A semiconductor substrate is prepared in which a first gate electrode layer is formed on a first insulating film covering one main surface, and an upper surface and sidewalls of the first gate electrode layer are covered with a second insulating film. And a process of
Forming an insulating layer that covers the first and second insulating films and is thicker than the thickness of the first gate electrode layer and the second insulating film;
Side spacers comprising the remaining portion of the insulating layer are etched back so that a portion of the insulating layer remains in contact with the second insulating film on the side of the first gate electrode layer. Forming a step;
Selectively etching the second insulating film and the side spacer to form a connection hole exposing a shoulder of the first gate electrode layer;
Forming an electrode material layer covering the first and second insulating films and the side spacers;
The electrode material layer is selected such that a part of the electrode material layer remains in a state where it overlaps with the first gate electrode layer and the side spacer and is connected to the first gate electrode layer through the connection hole. Forming a second gate electrode layer comprising a part of the electrode material layer remaining by patterning by an etching process.

  According to the manufacturing method of the second semiconductor device, when the electrode material layer is patterned by the selective etching process in the same manner as described above with respect to the manufacturing method of the first semiconductor device, the etching residue is left on the side of the first gate electrode layer. Can be eliminated. The first and second gate electrode layers are interconnected via a connection hole and used as a floating gate electrode. Therefore, in such a floating gate electrode, an increase in parasitic capacitance can be avoided.

  In the manufacturing method of the first or second semiconductor device described above, instead of the step of forming the side spacer, a step of forming an insulating thin layer may be executed as follows. That is, after forming the insulating layer, the insulating layer covers the first insulating film and remains in contact with the second insulating film on the side of the first gate electrode layer. Etching back is made thin to form an insulating thin layer composed of the remaining portion of the insulating layer. In this case, after the electrode material layer is formed so as to cover the insulating thin layer, the second gate electrode layer is formed so as to overlap the insulating thin layer. In this way, the same effect as described above with respect to the manufacturing method of the first or second semiconductor device can be obtained, and the flatness is improved by the insulating thin layer, so that the patterning accuracy of the second gate electrode layer is improved. There is an advantage to improve.

A method for manufacturing a third semiconductor device according to the present invention includes:
A semiconductor substrate is prepared in which a first gate electrode layer is formed on a first insulating film covering one main surface, and an upper surface and sidewalls of the first gate electrode layer are covered with a second insulating film. And a process of
Forming an insulating layer that covers the first and second insulating films and is thicker than the thickness of the first gate electrode layer and the second insulating film;
The insulating layer is thinned around the first gate electrode layer by etching back the insulating layer until the second insulating film is exposed above the first gate electrode layer. The process of remaining in
Selectively etching the second insulating film and the thinned insulating layer to form a connection hole exposing a shoulder of the first gate electrode layer;
Etching back the insulating layer so that a part of the thinned insulating layer remains in contact with the second insulating film on the side of the first gate electrode layer, thereby removing the remaining portion of the insulating layer. Forming a side spacer,
Forming an electrode material layer covering the first and second insulating films and the side spacers;
The electrode material layer is selected such that a part of the electrode material layer remains in a state where it overlaps with the first gate electrode layer and the side spacer and is connected to the first gate electrode layer through the connection hole. Forming a second gate electrode layer comprising a part of the electrode material layer remaining by patterning by an etching process.

  According to the third method for manufacturing a semiconductor device, the etching residue is eliminated at the side of the first gate electrode layer when the electrode material layer is patterned by selective etching as in the case of the method for manufacturing the second semiconductor device. In addition, an increase in parasitic capacitance can be avoided in the floating gate electrode constituted by the first and second gate electrode layers. In addition, a thin insulating layer is left around the first gate electrode layer, and a resist mask for forming a connection hole is formed by photolithography in a state with good flatness, and a selective etching process using this resist mask is performed. Since the connection hole is formed by the above, the formation accuracy of the connection hole is improved.

  In the manufacturing method of the third semiconductor device described above, instead of the step of forming the side spacer, a step of forming an insulating thin layer may be performed as follows. That is, after the connection hole is formed, the thinned insulating layer covers the first insulating film and remains in contact with the second insulating film on the side of the first gate electrode layer. The insulating layer is etched back to make it thinner, thereby forming an insulating thin layer composed of the remaining portion of the insulating layer. In this case, after the electrode material layer is formed so as to cover the insulating thin layer, the second gate electrode layer is formed so as to overlap the insulating thin layer. In this way, the same effects as described above with respect to the method for manufacturing the third semiconductor device can be obtained, and the flatness is improved by the insulating thin layer, thereby improving the patterning accuracy of the second gate electrode layer. There is.

  In the first to third semiconductor device manufacturing methods, in the step of forming the second gate electrode layer, another part of the electrode material layer overlaps with the first gate electrode layer and the side spacer. And a third gate formed of the remaining part of the electrode material layer by patterning the electrode material layer by the selective etching process so as to remain in a state of being disposed close to the second gate electrode layer. An electrode layer may be formed. In the first to third semiconductor device manufacturing methods, when the insulating thin layer is formed instead of the side spacer, in the step of forming the second gate electrode layer, the other electrode material layer By patterning the electrode material layer by the selective etching process so that a portion thereof overlaps the first gate electrode layer and the insulating thin layer and remains in a state of being close to the second gate electrode layer. A third gate electrode layer made of the remaining part of the electrode material layer may be formed. In this case, there is no etching residue between the second and third gate electrode layers arranged close to each other at the side portion of the first gate electrode layer, thereby preventing a short circuit between the second and third gate electrode layers. Can do.

  According to the present invention, the etching residue is eliminated when the upper gate electrode layer overlapping the lower gate electrode layer is formed, so that it is possible to avoid an increase in parasitic capacitance and occurrence of a short circuit failure in the upper gate electrode layer. Thus, the manufacturing yield of semiconductor devices such as EEPROM can be improved.

  1 to 11 show an EEPROM manufacturing method according to an embodiment of the present invention, and steps (1) to (11) corresponding to the respective drawings will be sequentially described.

  (1) For example, an insulating film 12 for gate insulation made of silicon oxide is formed on the surface of the semiconductor substrate 10 made of silicon by a thermal oxidation method or the like. The thickness of the insulating film 12 can be 200-300 [２００] as an example. Then, a polysilicon layer 14 is formed on the insulating film 2 by the CVD method. During or after the deposition of the polysilicon layer 14, the polysilicon layer 14 is doped with a conductivity-determining impurity such as phosphorus, so that the resistance of the polysilicon layer 14 is reduced to such an extent that it can be used as a gate electrode layer.

The gate insulating film 12 is not limited to a single layer film made of silicon oxide (SiO ₂ ) but may be a laminated film. For example, when a high dielectric constant material such as silicon nitride (SiN) or tantalum oxide is used, a laminated film of SiN / SiO ₂ (SiO ₂ is below), SiO ₂ / SiN / SiO ₂ or the like can be formed. Use of a high dielectric constant material is advantageous for miniaturization and speeding up of the element.

  Next, an insulating film 16 for interlayer insulation made of silicon oxide is formed on the surface of the doped polysilicon layer 14 by thermal oxidation. Then, resist layers 18A and 18B are formed on the insulating film 16 according to a desired gate electrode pattern by photolithography.

  (2) The insulating film 16 is selectively removed by an isotropic wet etching process using the resist layers 18A and 18B as a mask and HF as an etchant, and the portions 16a and 16b of the insulating film 16 are left as interlayer insulating films. . At this time, the corners of the shoulder portions of the portions 16a and 16b of the insulating film 16 are relaxed by side etching.

  (3) The polysilicon layer 14 is selectively removed by anisotropic dry etching using the resist layers 18A and 18B and the insulating films 16a and 16b as masks, so that the portions 14a and 14b of the polysilicon layer 14 are gate electrode layers. Remain as

  (4) After removing the resist layers 18A and 18B by ashing or the like, insulating films 20, 20a to 20d made of silicon oxide are formed by thermal oxidation. The insulating film 20 is formed on a portion of the substrate surface other than the portion where the gate electrode layers 14a and 14b are arranged, and is formed continuously and thicker than the gate insulating films 12a and 12b immediately below the electrode layers 14a and 14b. The The thickness of the insulating film 20 can be set to 300 to 600 [Å] as an example.

As the insulating films 20 and 20a to 20d, a laminated film in which another insulating film is stacked on a silicon oxide film formed by a thermal oxidation method may be used. For example, a laminated film such as SiN / SiO ₂ (SiO ₂ is below) or SiO ₂ / SiN / SiO ₂ may be used. In this case, the SiN film can be formed by normal low-pressure CVD (for example, a film forming method using a CVD reaction between silane gas and nitrogen gas or ammonia gas). In order to form the SiO ₂ film on the SiN film, an annealing process (mainly rapid thermal annealing [RTA] process) at about 800 to 1100 ° C. in an oxidizing gas atmosphere that also serves as a sinter of the SiN film, or It is possible to use a method of forming a very thin SiO ₂ film by the CVD method and performing sintering (mainly annealing by the RTA method) at about 800 to 1100 ° C. in an atmosphere of N ₂ gas, inert gas or oxidizing gas.

  The insulating films 20a and 20b are formed on one and the other side walls of the gate electrode layer 14a, respectively, and the insulating films 20a and 20b are both formed continuously with the insulating films 16a and 20. The insulating films 20c and 20d are formed on one and the other side walls of the gate electrode layer 14b, respectively. The insulating films 20c and 20d are both formed continuously to the insulating films 16b and 20. Simultaneously with the formation of the insulating films 20a to 20d, insulating films 20e and 20f made of silicon oxide are formed on the side walls of the gate electrode layer 14a facing each other between the insulating films 20a and 20b, respectively, as shown in FIG. Is done. 12 shows a cross section of the gate portion (portion including 12a, 14a, 16a) in a direction orthogonal to the paper surface of FIG. 4, and is a cross section of FIG. 24 in the prior art (YY ′ line in FIG. 22). Corresponds to the cross section).

  The thickness of each of the insulating films 20a to 20f can be set to 500 to 900 [Å] as an example. The thicknesses of the insulating films 16a and 16b can be 900 to 1500 [Å] as an example, and the thicknesses of the gate electrode layers 14a and 14b can be 2000 to 4000 [Å] as an example.

  (5) Covering the insulating films 16a, 16b, 20, 20a to 20f on the upper surface of the substrate, the insulating layer 22 is formed in a flat shape thicker than the thickness of the gate electrode layer 14a and the insulating film 16a. As the insulating layer 22, a glassy insulating layer formed by applying a flowable glass material such as SOG (spin-on-glass) by spin coating and then subjecting the applied layer to heat treatment, A ceramic insulating layer formed by applying a sesquioxane resin by a spin coating method and then heat-treating the applied layer can be used.

As another example of the insulating layer 22, a silicon oxide (SiO ₂ ) layer, a silicon oxynitride (SiON) layer, a silicon nitride (SiN) layer, or the like formed by a vapor deposition method may be used. A SiO ₂ layer, a SiON layer, or a SiN layer made from (Tetra Ethyl Ortho Silicate) is preferable because it has good flatness and coverage.

  As the insulating layer 22, a doped silicon oxide film may be formed by a CVD method such as an atmospheric pressure CVD method or a low pressure CVD method. As doped silicon oxide films, BSG (boron silicate glass) film, PSG (phosphosilicate glass) film, BPSG (boron phosphosilicate glass) film, Ge-added BSG film, Ge-added PSG film, Ge-added BPSG film, etc. Can be used. In order to form this kind of silicon oxide film, a silane gas-based or TEOS-based atmospheric pressure CVD method can be used. According to such a method, a silicon oxide film with good coverage (coverability) can be obtained. Therefore, in the step of FIG. 6, the side spacer shape becomes smoother, and the stringer suppressing effect is increased.

  (6) The insulating layer 22 is dry-etched so that the portions 22a to 22f of the insulating layer 22 remain in contact with the insulating films 20a to 20f on the sides of the gate electrode layers 14a and 14b as shown in FIGS. Etching back is used to form side spacers 22a to 22f made of the remaining portion of the insulating layer 22. The side spacers 22a and 22b shown in FIG. 6 and the side spacers 22e and 22f shown in FIG. 12 are formed around the gate electrode layer 14a so as to surround the electrode layer 14a.

  (7) A resist layer 24 having a hole 24a exposing the shoulder portion of the insulating film 16a and a portion of the insulating film 20b and side spacer 22b in the vicinity thereof is formed on the upper surface of the substrate by photolithography.

  (8) The insulating films 16a and 20b and the side spacers 22b are selectively removed by a dry etching process using the resist layer 24 as a mask to form a connection hole 26 that exposes the shoulder of the gate electrode layer 14a.

  (9) After removing the resist layer 24 by ashing or the like, a low resistance polysilicon (doped polysilicon) layer 28 is formed on the upper surface of the substrate in the same manner as described above. The polysilicon layer 28 is connected to the gate electrode layer 14a through the connection hole 26. In the portions other than the connection portion, the substrate 10 is formed by the insulating films 16a, 16b, 20, 20a to 20f, and the side spacers 22a to 22f. Insulated from the gate electrode layers 14a and 14b.

  On the doped polysilicon layer 28, a refractory metal silicide layer such as Ti, W, Mo or the like is laminated to form a laminate (polycide layer), or a refractory metal layer such as Ti, W, Mo or the like is formed. It is also possible to form a stacked layer. Any of the laminated structures can form a low-resistance electrode layer, which is advantageous for improving element characteristics and miniaturization.

  (10) Resist layers 30A and 30B are formed on the polysilicon layer 28 by photolithography. The resist layer 30A is formed in a pattern corresponding to the gate electrode layer as a word line, and the resist layer 30B corresponds to the second gate electrode layer constituting the floating gate electrode together with the first gate electrode layer 14a. Form with a pattern.

  (11) The polysilicon layer 28 is selectively removed by anisotropic dry etching using the resist layers 30A and 30B as masks, leaving the polysilicon layers 28A and 28B as gate electrode layers. The gate electrode layer 28A is used as a word line. The gate electrode layer 28B is connected to the gate electrode layer 14a via the connection hole 26 (FIG. 8), and constitutes a floating gate electrode together with the gate electrode layer 14a. In the example shown in FIG. 11, the gate electrode layer 28B partially overlaps the insulating film 16a, and such an overlapping state is indicated by a broken line in FIG.

After forming the gate electrode layers 28A and 28B, a source region S and a drain region D are formed on the substrate surface by selective ion implantation. When the substrate 10 is P-type, the regions S and D are both N ⁺ type. The source region S and the drain region D are used as a ground line and a bit line, respectively. On the substrate surface under the gate electrode layer 14a is, for example, by selective ion implantation through the polysilicon layer 14 and the insulating film 12 before forming the insulating film 16 in the step of FIG. 1 N ^- -type capacitance formed Region C may be formed. The capacitance forming region C forms a coupling capacitance together with the insulating film 12a and the gate electrode layer 14a.

  Information is written by injecting electrons from the gate electrode layer 14b to the floating gate electrodes 14a and 28B by the tunnel effect, and the channel region below the gate electrode layer 28B is turned off. Information is erased by discharging electrons from the floating gate electrodes 14a and 28B to the gate electrode layer 28A by a tunnel effect, and the channel region below the gate electrode layer 28B is turned on. The reason why the corners are relaxed at the shoulders of the insulating films 16a and 16b is to facilitate the transfer of electrons based on the tunnel effect. The insulating film 16a has an advantage that the formation of the connection hole is facilitated by relaxing the corners of the shoulder. Note that details of the operation of the EEPROM as described above are described in Japanese Patent No. 2512181, and thus description thereof is omitted.

According to the above-described embodiment, as shown in FIG. 12, the side spacers 22e and 22f are formed on the side portions of the gate electrode layer 14a, so that the step is reduced on the side portions of the electrode layer 14a. For this reason, when the polysilicon layer 28 is formed so as to cover the side spacers 22e and 22f in the step of FIG. 9, the polysilicon layer 28 is deposited on the side spacers 22e and 22f as well as on the side spacer 22a shown in FIG. Thus, it is suppressed that the electrode layer 14a becomes thick at the side portion. After that, when the polysilicon layer 28 is patterned by selective etching in the step of FIG. 11, the side portion of the electrode layer 14a is easily etched because the step is relaxed, so that it contacts the side spacers 22e and 22f. There is no remaining polysilicon residue (etching residue). Accordingly, the parasitic capacitance of the gate electrode layer 28A or 28B is not increased, and the electrode layers 28A and 28B are not short-circuited, and the manufacturing yield of the EEPROM is improved. Further, when the side spacers 22a to 22c are made of SiON or SiN, the dielectric constant of SiON or SiN is 6 to 7 and about 1.5 to 1.7 times larger than that of SiO ₂ , so that channel control is performed by the gate potential. It can be performed efficiently. This is the same when the side spacers 22a to 22c are made of another high dielectric constant material such as tantalum oxide.

  FIGS. 13 to 16 show an EEPROM manufacturing method according to another embodiment of the present invention, and the same parts as those in FIGS.

  The process of FIG. 13 is an etch-back process following the process of FIG. In the process of FIG. 13, the insulating layer 22 is etched back by a dry etching process until the upper surfaces of the insulating films 16a and 16b are exposed, so that the insulating layer 22 remains thin on the upper surface of the substrate. Is substantially flat.

  In the step of FIG. 14, a resist layer 32 having a hole 32a corresponding to a desired connection hole is formed on the upper surface of the substrate by photolithography. At this time, since the flatness of the upper surface of the substrate is good, the position and size accuracy of the hole 32a in the resist layer 32 is good, and it is advantageous for forming a fine pattern. That is, since the resist thickness is uniform and the DOF (depth of focus) may be narrow, an exposure method with a narrow DOF such as excimer exposure can be employed.

  In the step of FIG. 15, the insulating films 16a and 20b and the insulating layer 22 are selectively removed by dry etching using the resist layer 32 as a mask to form a connection hole 34 exposing the shoulder of the gate electrode layer 14a. The connection hole 34 is formed with high precision corresponding to the hole 32 a of the resist layer 32.

  In the step of FIG. 16, the resist layer 32 is removed. Then, the insulating film 22 is dry-etched so that the portions 22a to 22f of the insulating layer 22 remain in contact with the insulating films 20a to 20f on the sides of the gate electrode layers 14a and 14b as shown in FIGS. Etching back forms side spacers 22a to 22f made of the remaining portion of the insulating layer 22. The side spacers 22a and 22b shown in FIG. 16 and the side spacers 22e and 22f shown in FIG. 12 are formed around the gate electrode layer 14a so as to surround the electrode layer 14a.

  After the process of FIG. 16, a polysilicon layer 28 is formed on the upper surface of the substrate as described above with reference to FIG. Then, after forming resist layers 30A and 30B on the polysilicon layer 28 in the same manner as described above with reference to FIG. 10, anisotropic dry etching using the resist layers 30A and 30B as a mask as described above with reference to FIG. The polysilicon layer 28 is patterned by processing to form gate electrode layers 28A and 28B. The gate electrode layer 28B is connected to the gate electrode layer 14a through the connection hole 34 (FIG. 15), and constitutes a floating gate electrode together with the gate electrode layer 14a.

  According to the embodiment described above with reference to FIGS. 13 to 16, the polysilicon residue (etching residue) remaining in contact with the side spacers 22 e and 22 f on the side of the gate electrode layer 14 a as in the embodiment described with reference to FIGS. Can be eliminated. Accordingly, the parasitic capacitance of the gate electrode layer 28A or 28B is not increased, and the electrode layers 28A and 28B are not short-circuited, so that the manufacturing yield of the EEPROM is improved.

  Next, a modified example of the steps of FIGS. 6 to 12 will be described with reference to FIGS. 17-20, the same code | symbol is attached | subjected to the part similar to FIGS. 6-12, and detailed description is abbreviate | omitted.

  FIG. 17 shows a dry etching process corresponding to FIG. In the process of FIG. 17, the insulating layer 22 covers the insulating film 20 and is thinned by etching back the insulating layer 22 so that it remains in contact with the insulating films 20a to 20d on the side of the gate electrode layers 14a and 14b. Insulating thin layers 22g, 22h, and 22i made of the remaining portions of the insulating layer 22 are formed. 20 shows a cross section corresponding to FIG. 12 at this time (corresponding to a cross section taken along the line YY ′ of FIG. 22). FIG. 20 shows the insulating thin layers 22j and 22k formed of the remaining portions of the insulating layer 22. A state is shown in which the insulating film 20 is formed in contact with the insulating films 20e and 20f on the side of the gate electrode layer 14a. The insulating thin layers 22g and 22h shown in FIG. 17 and the insulating thin layers 22j and 22k shown in FIG. 20 are formed around the gate electrode layer 14a so as to surround the gate electrode layer 14a.

  In the process of FIG. 18, the connection hole 26 exposing the shoulder of the gate electrode layer 14a is formed in the insulating films 16a and 20b and the insulating thin layer 22h in the same manner as described above with reference to FIGS. In the step of FIG. 19, gate electrode layers 28A and 28B are formed in the same manner as described above with reference to FIGS. The gate electrode layer 28A is formed so as to cover the insulating thin layer 22g while partially overlapping the gate electrode layer 14a via the insulating film 16a. The gate electrode layer 28B is formed so as to cover the insulating thin film 22h while being connected to the gate electrode layer 14a via the connection hole 26 (FIG. 18) and to partially overlap the gate electrode layer 14b via the insulating film 16b. Is done. In the example shown in FIG. 19, the gate electrode layer 28B partially overlaps the insulating film 16a, and such an overlapping state is indicated by a broken line in FIG.

  FIG. 21 shows a modification of the dry etching process of FIG. In FIG. 21, the same parts as those in FIG. 16 are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the step of FIG. 21, after removing the resist layer 32 shown in FIG. 15, the thinned insulating layer 22 (FIG. 15) covers the insulating film 20 and the insulating films 20 a to 20 d on the side of the gate electrode layers 14 a and 14 b. The insulating film 22 is etched back by a dry etching process so as to remain in contact with the insulating layer 22 and is further thinned to form insulating thin layers 22g, 22h, and 22i composed of the remaining portions of the insulating layer 22. At this time, insulating thin layers 22j and 22k made of the remaining portion of the insulating film 22 are formed on one and the other side of the gate electrode layer 14a shown in FIG. Thereafter, gate electrode layers 28A and 28B are formed on the upper surface of the substrate in the same manner as described above with reference to FIG.

  17-21, the steps are reduced and the flatness is improved by the insulating thin layers 22a-22k, so that etching of polysilicon or the like is performed when forming the gate electrode layers 28A, 28B. The remaining pattern disappears and the patterning accuracy improves. In addition, when a high dielectric constant material such as silicon oxynitride, silicon nitride, or tantalum oxide is used as the material of the insulating thin layers 22a to 22k, the device characteristics can be improved.

It is board | substrate sectional drawing which shows the resist layer formation process in the manufacturing method of EEPROM which concerns on one Embodiment of this invention. FIG. 2 is a cross-sectional view of the substrate showing a step of selectively etching the insulating film following the step of FIG. 1. FIG. 3 is a substrate cross-sectional view showing a polysilicon layer selective etching step following the step of FIG. 2. FIG. 4 is a substrate cross-sectional view showing a resist layer removing process and a silicon oxidation process following the process of FIG. 3. FIG. 5 is a cross-sectional view of a substrate showing an insulating layer forming step subsequent to the step of FIG. 4. FIG. 6 is a substrate cross-sectional view showing an etch-back process following the process of FIG. 5. FIG. 7 is a substrate cross-sectional view showing a resist layer forming step that follows the step of FIG. 6. FIG. 8 is a substrate cross-sectional view showing a connection hole forming step subsequent to the step of FIG. 7. FIG. 9 is a cross-sectional view of a substrate showing a resist layer removing step and a polysilicon layer forming step following the step of FIG. 8. FIG. 10 is a substrate cross-sectional view showing a resist layer forming step that follows the step of FIG. 9. FIG. 11 is a cross-sectional view of the substrate illustrating a polysilicon layer selective etching step following the step of FIG. 10. It is a board | substrate sectional drawing which shows the formation condition of the side spacer in the side part of a gate electrode layer. It is board | substrate sectional drawing which shows the 1st etch back process in the manufacturing method of EEPROM which concerns on other embodiment of this invention. FIG. 14 is a cross-sectional view of a substrate showing a resist layer forming step subsequent to the step of FIG. 13. FIG. 15 is a substrate cross-sectional view showing a connection hole forming step subsequent to the step of FIG. 14. FIG. 16 is a substrate cross-sectional view showing a second etchback step following the step of FIG. 15. FIG. 7 is a substrate cross-sectional view showing a modified example of the step of FIG. 6. FIG. 18 is a substrate cross-sectional view showing a connection hole forming step subsequent to the step of FIG. 17. FIG. 19 is a substrate cross-sectional view showing a gate electrode layer forming step following the step of FIG. 18. FIG. 18 is a cross-sectional view of a substrate showing a state of forming an insulating thin layer on the side of the gate electrode layer in the modification of FIG. FIG. 17 is a substrate cross-sectional view illustrating a modified example of the process in FIG. 16. It is a top view which shows the MOS type transistor part of the conventional EEPROM. It is sectional drawing which follows the X-X 'line | wire of FIG. It is sectional drawing which follows the Y-Y 'line | wire of FIG. It is board | substrate sectional drawing which shows the resist layer formation process in the manufacturing method of the MOS type transistor part of the conventional EEPROM. FIG. 26 is a substrate cross-sectional view showing a step of selectively etching the insulating film subsequent to the step of FIG. 25. FIG. 27 is a substrate cross-sectional view showing a polysilicon layer selective etching step following the step of FIG. 26. FIG. 28 is a cross-sectional view of a substrate showing a resist layer removal step and a silicon oxidation step following the step of FIG. 27. FIG. 29 is a cross-sectional view of the substrate showing a half etching step or a half ashing step following the step of FIG. 28. FIG. 30 is a substrate cross-sectional view showing a resist layer forming step that follows the step of FIG. 29. FIG. 31 is a substrate cross-sectional view showing a connection hole forming step following the step of FIG. 30. FIG. 32 is a substrate cross-sectional view showing a resist layer removing step that follows the step of FIG. 31. FIG. 33 is a substrate cross-sectional view showing a polysilicon layer forming process and a resist layer forming process following the process in FIG. 32.

Explanation of symbols

  10: Semiconductor substrate, 12, 16, 20, 20a to 20f: Insulating film, 12a, 12b: Gate insulating film, 14, 28: Polysilicon layer, 14a, 14b, 28A, 28B: Gate electrode layer, 16a, 16b: Interlayer insulating film, 18A, 18B, 24, 30A, 30B, 32: resist layer, 22: insulating layer, 22a to 22f: side spacer, 22g to 22k: insulating thin layer, 26, 34: connection hole.

Claims (4)

A semiconductor substrate is prepared in which a first gate electrode layer is formed on a first insulating film covering one main surface, and an upper surface and sidewalls of the first gate electrode layer are covered with a second insulating film. And a process of
Forming an insulating layer that covers the first and second insulating films and is thicker than the thickness of the first gate electrode layer and the second insulating film;
The insulating layer is thinned around the first gate electrode layer by etching back the insulating layer until the second insulating film is exposed above the first gate electrode layer. The process of remaining in
Selectively etching the second insulating film and the thinned insulating layer to form a connection hole exposing a shoulder of the first gate electrode layer;
Etching back the insulating layer so that a part of the thinned insulating layer remains in contact with the second insulating film on the side of the first gate electrode layer, thereby removing the remaining portion of the insulating layer. Forming a side spacer,
Forming an electrode material layer covering the first and second insulating films and the side spacers;
By patterning the electrode material layer by a selective etching process, the electrode material that remains in a state of being overlapped with the first gate electrode layer and the side spacer and connected to the first gate electrode layer through the connection hole look including a step of forming a second gate electrode layer comprising a layer, the first gate electrode layer and the second gate electrode layer, preparation of EEPROM that constitutes the floating gate electrode. A semiconductor substrate is prepared in which a first gate electrode layer is formed on a first insulating film covering one main surface, and an upper surface and sidewalls of the first gate electrode layer are covered with a second insulating film. And a process of
Forming an insulating layer that covers the first and second insulating films and is thicker than the thickness of the first gate electrode layer and the second insulating film;
The insulating layer is thinned around the first gate electrode layer by etching back the insulating layer until the second insulating film is exposed above the first gate electrode layer. The process of remaining in
Selectively etching the second insulating film and the thinned insulating layer to form a connection hole exposing a shoulder of the first gate electrode layer;
The insulating layer is etched back so that the thinned insulating layer covers the first insulating film and remains in contact with the second insulating film on the side of the first gate electrode layer. Forming an insulating thin layer consisting of the remaining portion of the insulating layer by:
Forming an electrode material layer covering the first and second insulating films and the insulating thin layer;
The electrode material layer is patterned by a selective etching process so as to overlap the first gate electrode layer and the insulating thin layer and remain in a state of being connected to the first gate electrode layer through the connection hole look including a step of forming a second gate electrode layer made of wood layer, the first gate electrode layer and the second gate electrode layer, preparation of EEPROM that constitutes the floating gate electrode. In the step of forming the second gate electrode layer, the electrode material layer is patterned by the selective etching process so as to overlap the first gate electrode layer and the side spacer and to approach the second gate electrode layer. 2. The method of manufacturing an EEPROM according to claim 1 , wherein a third gate electrode layer made of the electrode material layer remaining in the disposed state is formed , and the third gate electrode layer constitutes a word line . In the step of forming the second gate electrode layer, the electrode material layer is patterned by the selective etching process so as to overlap the first gate electrode layer and the insulating thin layer and to the second gate electrode layer. 3. The method of manufacturing an EEPROM according to claim 2 , wherein a third gate electrode layer made of the electrode material layer remaining in a close-up state is formed , and the third gate electrode layer constitutes a word line .

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