JP4701375B2 - Crystal growth method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a crystal growth technique, and particularly to a high-quality heteroepitaxial crystal growth technique that can be controlled at the atomic layer level.
[0002]
[Prior art]
With the miniaturization of electronic devices and optical devices, the importance of crystal growth technology that can be controlled at the atomic layer level is increasing. For example, when the MBE method or the MOCVD method is used, the film thickness can be controlled at the level of several atomic layers.
[0003]
On the other hand, since film thickness control at the atomic layer level has become possible, so-called quantum effect devices that actively utilize quantum effects have been actively studied (for example, see Non-Patent Document 1).
[0004]
[Non-Patent Document 1]
Application of quantum effect devices to digital circuits, P. Mazumder, S. Kulkarni, M. Bhattacharya, JP Sun, and GI Haddad, "Digital circuit applications of resonant tunneling devices", Proc. IEEE, vol.86, pp.664-686 , 1998.
[0005]
[Non-Patent Document 2]
Review of quantum cascade lasers, Federico Capasso, Claire Gmachl, Roberto Paiella, Alessandro Tredicucci, Albert L. Hutchinson, Deborah L. Sivco, JN Baillargeon, Alfred Y. Cho, and HC Liu, "New Frontiers in Quantum Cascade Lasers and Applications, "IEEE J. Selected Topics in Quantum Electron., Millennium Issue, vol.06, no. 06, pp.948, November / December 2000.
[0006]
[Problems to be solved by the invention]
The conventional technique is a technique for forming crystals uniformly over the entire substrate surface. Even if the actual substrate surface is mirror-finished using a general polishing method or the like, there is a step (atomic step position) in the atomic layer order. In practice, it has been found that such steps exist in the submicron order within the substrate plane. Therefore, in the case of a combination of materials in which a fatal stacking fault is generated at the atomic step position, it is difficult to obtain a high-quality thin film over a wide range (micron order) in the substrate surface.
[0007]
When crystal growth proceeds coherently with the crystal structure of the substrate material at the atomic step position, a good stacked crystal can be realized. However, such crystal growth can be realized only with a limited combination of materials, which has been a serious limitation that narrows the room for device material selection. For example, the above-described restriction has been one cause that cannot achieve a room temperature operable quantum effect device formed on a silicon substrate. Hereinafter, two crystal growth techniques related to the present technique will be described with reference to the drawings.
[0008]
The first related technique is a general selective growth technique, which will be described with reference to FIG. As shown in FIG. 12, for example, a mask pattern 103 is formed on a silicon substrate 101 by using a mask material such as silicon oxide. An opening 105 that exposes the surface of the silicon substrate 101 is formed in the mask pattern 103. When crystal growth using the same material or different material 107 is performed under appropriate conditions using the mask pattern 103, no crystal is deposited on the mask pattern 103, and only in the opening 105 where the surface of the silicon substrate 101 is exposed. The crystal 107a can be selectively grown.
[0009]
However, the selective growth technique is such that the same or different material 107 incident on the mask pattern 103 is transported onto the silicon substrate 101 with almost no adhesion on the mask pattern 103, that is, crystal growth. The main purpose is to control the position where the crystallizing is performed. In principle, improvement in crystal quality cannot be expected.
[0010]
The second related technology is called microchannel epitaxy technology. The microchannel epitaxy technique will be described with reference to FIG. In hetero-epitaxy technology between different materials, if a mask with an appropriate pattern and size is formed as the mask pattern in the selective growth, high quality crystals can be obtained even if the material is different in type and crystal structure / lattice constant from the substrate. May grow.
[0011]
As shown in FIG. 13, the present invention is applied to crystal growth of gallium nitride (GaN) on a sapphire substrate 201 or gallium arsenide (GaAs) on a silicon substrate. The principle of obtaining a good quality crystal by microchannel epitaxy is that the mask pattern 203 is formed between the mask patterns 203 using the crystal of the substrate portion 201a exposed from the opening of the mask pattern 203 such as silicon oxide formed on the substrate 201 as a scaffold (seed crystal). A crystal layer 207 is grown on the substrate, and a non-epitaxial lateral growth (horizontal crystal growth unrelated to underlying information) layer 211 is formed thereon as indicated by an arrow.
[0012]
Non-epitaxial lateral growth can realize crystal growth that is not affected by the mismatch of the lattice constant with the underlying substrate, so that a relatively high quality thick film crystal can be formed in the mask pattern 203 even in a system having a large lattice strain. Obtained at the top. However, in principle, a high density crystal defect 215 is inevitably generated at a place where islands grown in the lateral direction collide with each other because there is no mechanism for lattice matching.
[0013]
In other words, the microchannel epitaxy technique is a technique in which a crystal defect is generated locally and a defect is present at a high density, and a high quality part with few defects is formed, and the high quality part is applied to a device. . Since lateral growth is essential, high-quality crystals are not grown in the mask hole in principle, and high-quality crystals are obtained above the mask. In order to achieve lateral growth, a certain amount of thickness (mask thickness + lateral growth film thickness) is required, so it is difficult to apply this method to heterocrystal growth with a thickness of 2 to 3 atomic layers. .
[0014]
In short, the first and second techniques are techniques for controlling the position where a crystal is grown or a position where a crystal defect is generated. The technique for controlling the position of a crystal is not a technique for improving crystallinity. Absent.
[0015]
An object of the present invention is to provide a crystal growth technique capable of controlling the film thickness on the atomic layer order.
[0016]
[Means for Solving the Problems]
According to one aspect of the present invention, there is provided a method for crystal growth of a material different from a substrate on a substrate, the step of forming a minute region with reduced atomic step density on the substrate, and the step of forming the minute region on the minute region. There is provided a crystal growth method including a step of crystal growth of a material different from a substrate. According to the crystal growth method, since the material different from the substrate is crystal-grown on the minute region where the atomic step density is reduced, the probability that the grown crystal is applied to the boundary of the underlying atomic step is reduced, and the atomic layer It is possible to control the film thickness on the order (flattening the film).
[0017]
Further, a method for crystal growth of a material different from the substrate on the substrate, the step of forming a micro region having a size not more than a substantial diffusion length of atoms constituting the different material on the substrate, There is provided a crystal growth method including a step of crystal growth of a material different from the substrate in a micro region. According to the above crystal growth method, since different types of atoms are grown in the migration region of the substrate in which the migration region and the non-migration region are defined by forming a microregion, the film thickness control (film Flattening).
[0018]
The crystal growth step is preferably performed under the condition that the diffusion length of atoms constituting a material different from that of the substrate is substantially larger than the size of the minute region. This reduces the probability that the grown crystal will fall on the boundary of the underlying atomic step.
[0019]
And a step of performing a heat treatment under a condition in which a diffusion length of atoms constituting the substrate is substantially larger than a size of the minute region between the step of forming the minute region and the step of growing the crystal. It is preferable to include. Thereby, since the density of atomic steps in the smile region is reduced before crystal growth, film thickness controllability (film flatness) is further improved.
[0020]
The minute region is preferably a concave or convex region formed on the substrate. The minute region is preferably a region exposed from an opening formed in an insulator formed on the substrate. Growth can be performed simply by forming a concave or convex minute region or a region exposed in the opening on the substrate.
[0021]
According to another aspect of the present invention, a substrate, a minute convex region or a minute concave region formed on the substrate, and a material different from the substrate formed on the minute convex region or the minute concave region. And a quantum device characterized in that a size of the micro convex region or micro concave region is substantially smaller than a diffusion length of a material different from that of the substrate. .
[0022]
DETAILED DESCRIPTION OF THE INVENTION
Before describing embodiments of the present invention, considerations made by the inventors will be described first. The inventor controls the atomic step density on the surface of the substrate when a control of several atomic layers is required, and further restricts the size of the crystal growth region to a migration length (diffusion length) or less to directly above the substrate. I came up with a technique to artificially control the crystal growth process itself of several atomic layer thickness. In this way, high quality epitaxial growth can be realized.
[0023]
Based on the above considerations, the crystal growth method according to the first embodiment of the present invention will be described below with reference to the drawings.
[0024]
FIG. 1 ((1) to (4)) is a process diagram showing a crystal growth process according to the first embodiment of the present invention. FIG. 2 is a perspective view showing the structure of FIG. 1 in which a minute region is formed. As shown in FIG. 1, a thin film of a mask material 3 is formed on a substrate material 1. Next, a window in the crystal growth region is formed in the mask material 3 (formation of the opening 3a) to expose the surface of the substrate material 1 (see FIG. 2). Crystal growth of the heteroatom layer 5 is performed in the opening 3a. Electrical contacts (electrodes) 7 are formed on the grown heteroatom layer 5. By forming the lead wire 7 a on the electrode 7, electrical evaluation of the heteroatom layer 5 is possible. Through the above steps, a device using only the electrical or optical characteristics of the high quality portion formed in the opening 3a can be formed automatically.
[0025]
Hereinafter, specific examples of the crystal growth technique using the above method will be described with reference to the drawings. FIG. 3 is a surface AFM image obtained when epitaxial growth of a triatomic CaF ₂ layer 27 is performed on a minute opening 25 having a size of 500 nm, and FIG. 4A is an enlarged view thereof. As shown in FIGS. 3 and 4A, the opening 25 has a substantially triangular shape with one side of about 500 nm. FIG. 4B is a view showing a cross section taken along the line AB of FIG. 4A, and it can be seen that a favorable opening is formed. More specifically, as shown in FIG. 4C, a mask pattern 23 having an opening 25 made of SiO ₂ is formed on a Si (111) substrate 21. A CaF ₂ -based heterogeneous crystal layer 27 is formed on the Si (111) substrate 21 (small region) exposed through the opening 25. As is apparent from the figure, no abnormal growth or the like is observed at the boundary, and good epitaxial growth is confirmed.
[0026]
Using the crystal growth technique, resonant tunneling diodes shown in FIGS. 5A to 5C were manufactured and their characteristics were evaluated. FIG. 5A shows the surface of the substrate. As shown in FIG. 5A, on the surface of the substrate 51, a micro-region forming portion 53 in which a large number of micro-opening patterns defining the micro-region 55 are formed, and a pattern non-forming portion in which the micro-region 55 is not formed. 57. As shown in FIG. 5B, the minute region 55 has a substantially equilateral triangular shape with L on one side. As shown in FIG. 5C, on the n-type silicon substrate (111) surface 51, a CaF ₂ barrier layer 61 (growth temperature 750 ° C.) having a thickness of 0.9 nm and a CdF ₂ well having a thickness of 6.5 nm are formed. A layer 63 (growth temperature 60 ° C.) and a 0.9 nm thick CaF ₂ barrier layer 65 (growth temperature 60 ° C.) were grown. Thus, a cadmium fluoride / calcium fluoride double barrier resonant tunnel diode structure can be grown.
[0027]
The first calcium fluoride CaF ₂ layer stacked immediately above the silicon substrate is grown at about 650 ° C., whereas the second cadmium fluoride CdF ₂ layer grown thereon is grown at a growth temperature. Epitaxial growth with good flatness can be performed between 60 ° C. and 200 ° C. The temperature of the uppermost calcium fluoride CaF ₂ layer cannot be raised because the CdF ₂ layer is formed thereunder. Therefore, instead of lowering the growth temperature of the uppermost calcium fluoride to 60 ° C., ionization acceleration is performed at about 1 kV to provide migration energy and promote crystallization. Calcium fluoride is usually difficult to epitaxially grow at 60 ° C., but flat epitaxial growth is possible even at 60 ° C. by combining ionization acceleration treatment under appropriate conditions (reference: M. Watanabe, et al., "Low temperature epitaxial growth of CaF ₂ / Si (111) by Ionized-Cluster-Beam technique", Jpn. J. Appl. Phys., 29 [9], pp. 1803-1804, 1990.)
[0028]
FIGS. 6 to 9 show the size (L) dependence of the electrical characteristics in the cadmium fluoride / calcium fluoride double barrier resonant tunneling diode structure. The micro-region size (L) was compared in terms of current-voltage characteristics at room temperature for four types: no patterning (FIG. 6), 400 nm (FIG. 7), 200 nm (FIG. 8), and 100 nm (FIG. 9). .
[0029]
As a result, when the size L is larger than 400 nm, the peak-to-valley current ratio (P / V ratio) of the differential negative resistance itself is as small as 2 or less, and the peak shape itself may be broad. all right. On the other hand, when the micro region size L is smaller than 200 nm, the P / V ratio R exceeds 6, the peak shape becomes sharp, and the uniformity and reproducibility of the IV characteristics for each element. Significant improvement was also seen in the breakdown voltage.
[0030]
In consideration of the fact that the critical size of L of 200 nm corresponds to the atomic terrace width of the silicon substrate 51 (FIG. 5) used in the experiment, as the nano-area / local epitaxy technology intended, the device has an atomic step ( This is considered to be because the deterioration of the device characteristics due to straddling the boundary) is less likely to occur, and the characteristics of the electronic device are improved due to the high quality of the crystal layer. As a result, for the first time in this material system, we were able to demonstrate a systematic change in characteristics due to the quantum well thickness.
[0031]
Next, a crystal growth method according to a second embodiment of the present invention will be described with reference to the drawings. FIG. 10 (from (1) to (4)) shows a crystal growth process according to the present embodiment, and FIG. 11 is a perspective view of the main part of the crystal growth process.
[0032]
As shown in FIG. 10, first, a concavo-convex shape is formed on the surface of the substrate 71 by using a lithography technique (see FIG. 11A). A smooth surface (atomic step) at the atomic level is formed on the upper surface portion (top portion) 75a of the convex portion (mesa portion) 75 or the exposed surface (bottom portion) 73a of the concave portion 73 by a heat treatment process or a buffer layer crystal growth process. A low density surface). Next, different atomic layers 77 and 81 are grown on the entire surface of the substrate 71 (see FIG. 11B).
[0033]
After forming a thin film of the insulating film 83 which is a mask material, it is formed on the upper surface portion (top portion) 75a of the convex portion (mesa portion) or the exposed surface (bottom portion) 73a of the concave portion 73 by using a lithography technique. A contact hole 85 exposing a high quality crystal region (for example, a resonant tunnel diode structure) is formed, and an electrode layer 87 is formed thereon. Thereby, a device utilizing the characteristics of the high quality crystal region can be formed.
[0034]
The crystal growth method has the following advantages. 1) A step-free area can be artificially defined. 2) Since the width of the atomic terrace can be artificially enlarged, the degree of freedom in selecting the substrate tilt angle and device size is great. 3) Since the outer peripheral portion of the crystal can be removed by lithography, a higher quality device can be expected. In this method, since a minute region can be defined by forming a convex portion or a concave portion, a device can be easily formed, which is considered to be close to the ideal form of local epitaxy.
[0035]
As described above, it is possible to remarkably suppress the generation of defects that occur when different materials are grown in a stacked crystal with a thickness of several atomic layers. In particular, in calcium fluoride crystal growth on a silicon substrate, fatal stacking faults can be reduced in the vicinity of atomic steps preliminarily existing on the substrate.
[0036]
By using the crystal growth technique according to the present embodiment, for example, an extremely high quality calcium fluoride-cadmium fluoride laminated crystal can be formed on a silicon substrate, and a quantum effect device that exhibits a remarkable quantum effect at room temperature is obtained. It can be formed on the same substrate as the silicon integrated circuit.
[0037]
As mentioned above, although demonstrated along this Embodiment, it cannot be overemphasized that this invention is not limited to these examples, and various deformation | transformation are possible. Excellent current-voltage characteristics even at room temperature, realizing high-quality quantum effect devices with high reproducibility and uniformity, enabling integrated memory, ultra-high-frequency oscillation circuits, ultra-high-speed logic circuits, and between quantum subbands Electronic devices that fuse light and electrons, such as transition lasers and ultrafast optical switches, can be realized.
[0038]
【The invention's effect】
As described above, when the crystal growth technique of the present invention is used, it is possible to remarkably suppress the generation of defects that occur when different types of materials are stacked and grown with a thickness of several atomic layers.
[Brief description of the drawings]
FIG. 1 (1) to (4) are process diagrams of a crystal growth method according to a first embodiment of the present invention.
FIG. 2 is a perspective view corresponding to FIG.
FIG. 3 is a diagram corresponding to FIG. 2, and is a surface AFM image when a CaF ₂ epitaxial growth of a triatomic layer is performed on a minute opening having a size of 500 nm.
4A is an enlarged view of FIG. 3. FIG. FIG. 4B is a view showing a cross section taken along the line AB of FIG. FIG. 4C is a cross-sectional view showing FIG. 4B in more detail.
FIG. 5A is a diagram showing a surface of a substrate. FIG. 5B is an enlarged view of FIG. FIG. 5C shows a cross-sectional structure of the grown crystal.
6 is a diagram illustrating IV characteristics of the double-barrier resonant tunneling diode illustrated in FIGS. 4 and 5, and is a diagram illustrating characteristics in the case of a pattern without a fine region. FIG.
7 is a diagram illustrating IV characteristics of the double-barrier resonant tunneling diode illustrated in FIGS. 4 and 5, and is a diagram illustrating characteristics when the length L of one side of a fine region is 400 nm. FIG.
8 is a diagram showing IV characteristics of the double-barrier resonant tunneling diode shown in FIGS. 4 and 5, and is a diagram showing characteristics when the length L of one side of a fine region is 200 nm. FIG.
9 is a diagram showing IV characteristics of the double-barrier resonant tunneling diode shown in FIGS. 4 and 5, and showing the characteristics when the length L of one side of a fine region is 100 nm. FIG.
FIG. 10 ((1) to (4)) is a process diagram of the crystal growth method according to the second embodiment of the present invention.
11 (A) and 11 (B) are perspective views corresponding to FIGS. 10 (1) and 10 (3).
FIG. 12 is a diagram showing an example of a conventional selective growth technique.
FIG. 13 is a diagram showing an example of a conventional crystal growth technique.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Substrate material, 3 ... Mask material, 3a ... Opening part, 5 ... Heterogeneous atom layer, 7 ... Electrical contact, 25 ... Opening part, 51 ... Substrate, 53 ... Micro area formation part, 55 ... Micro area | region, 61 ... CaF ₂ barrier layer, 63 ... CdF ₂ well layer, 65 ... CaF ₂ barrier layer, 71 ... substrate, 73 ... concave portion, 75 ... convex portion, 77, 81 ... heteroatom layer.

Claims (4)

A method for crystal growth of a material different from the substrate on a substrate,
Forming a minute region having a size smaller than the terrace width of the substrate on the substrate;
A step of crystal-growing a material different from the substrate in the minute region,
The crystal growth step is performed under the condition that the diffusion length of atoms constituting a material different from that of the substrate is larger than the size of the microregion,
Further, between the step of forming the microregion and the step of crystal growth,
A crystal growth method comprising a step of performing a heat treatment under a condition that a diffusion length of atoms constituting the substrate is larger than a size of the minute region.   The crystal growth method according to claim 1, wherein the minute region is a concave or convex region formed on the substrate.   The crystal growth method according to claim 1, wherein the minute region is a region exposed from an opening formed in an insulator formed on the substrate. A substrate,
At least one of a minute convex region or a minute concave region formed on the substrate, and
A quantum structure formed on the minute convex region or the minute concave region and formed of a material different from the substrate;
A quantum device in which the size of the micro convex region or micro concave region is smaller than the terrace width of the substrate ,
The quantum structure differs from the substrate after heat treatment of the substrate under a condition that the diffusion length width of atoms constituting the substrate is larger than the size of the minute convex region or the minute concave region. It is a quantum structure formed by growing a material different from that of the substrate under the condition that the diffusion length of atoms constituting the material is larger than the size of the minute convex region or the minute concave region. Characteristic quantum device.

Images