JP4704153B2 - Solid-state imaging device - Google Patents

Description

  The present invention relates to a solid-state imaging device including a light-receiving unit that includes two-dimensionally arranged pixel units each having a photodiode that generates an amount of electric charge according to the amount of incident light.

  The solid-state imaging device includes a light receiving unit including a plurality of pixel units that are two-dimensionally arranged, and each pixel unit includes a photodiode that generates an amount of charge corresponding to the amount of incident light. Such a solid-state imaging device is required to have an improved dynamic range. For example, Patent Document 1 discloses an invention intended to do so.

In the solid-state imaging device described in Patent Document 1, a voltage value corresponding to the amount of charge generated in each photodiode of all the pixel units included in the light receiving unit can be obtained in response to light incidence over a certain period. The voltage value (analog value) is converted into a digital value, and the digital value is stored in the frame memory. Next, a voltage value corresponding to the amount of charge generated in each of the photodiodes of all the pixel units included in the light receiving unit in response to light incidence over a longer period including the above period is obtained. For each of the plurality of pixel units, if the incident light amount is relatively small and the latter voltage value is not saturated, the latter voltage value is selected, while the incident light amount is relatively large and the latter voltage value is saturated. If so, the former value stored in the frame memory is selected. In this way, the dynamic range is expanded for each of the plurality of pixel portions.
Japanese Patent No. 2966977

  However, since the solid-state imaging device described in the above document requires a frame memory, the device becomes large and expensive. The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a solid-state imaging device that can expand the dynamic range of each of a plurality of pixel portions and can be downsized. .

The solid-state imaging device according to the present invention includes: (1) pixel units P _{1,1 to} P _{M, N} each having two-dimensionally arranged in M rows and N columns, each having a photodiode that generates an amount of charge corresponding to the amount of incident light. And (2) a voltage value corresponding to the amount of charge generated in each of _{the N} pixel units P _{m, 1 to} P _{m, N} in any m-th row in the light receiving unit. A first hold unit that holds and outputs values V1 _{m, 1 to} V1 _{m, N} , and (3) each of the N pixel units P _{m, 1 to} P _{m, N} in any m-th row in the light receiving unit. A second hold unit that holds and outputs a voltage value corresponding to the amount of charge generated in the photodiode as a voltage value V2 _{m, 1 to} V2 _{m, N} ; and (4) N in any m-th row in the light receiving unit. pixel units P _{m, 1} ~P _{m, N} voltage value V3 m a voltage value corresponding to the amount of charges generated in the respective _photodiodes, To V3 _m, and a third holding portion for holding the _N output, (5) the N voltage values output from the first holding portion or the second holding portion V1 _m, 1 ~V1 _{m, N} or the N voltage V2 _m, 1 ~V2 _{m, n} and, n-number of voltage values output from the third holding portion V3 _m, 1 ~V3 _m, inputs the _n, the voltage value V1 _{m, n} or voltage value V2 _{m, n} and the reference voltage value Vsat are compared in magnitude, and a signal indicating the comparison result is output. When the voltage value V1 _{m, n} or the voltage value V2 _{m, n} is less than the reference voltage value Vsat, the voltage value An output selection unit that selectively outputs V1 _{m, n} or voltage value V2 _{m, n} , and otherwise outputs voltage value V3 _{m, n} ; and (6) a light receiving unit, a first hold unit, A control unit that controls the operation of each of the 2 hold unit, the third hold unit, and the output selection unit. And wherein the Rukoto. In addition, it is preferable that the light receiving unit, the first hold unit, the second hold unit, the third hold unit, and the output selection unit are monolithically formed on a common substrate.

Further, the control unit included in the solid-state imaging device according to the present invention is configured so that each of the first row to the M-th row in the light-receiving unit is sequentially (a) each pixel in the m-th row according to the light incidence over the first period The voltage value corresponding to the amount of charge generated in the photodiode of the part P _{m, n} is held by the first holding part as the voltage value V1 _{m, n} when the m value is odd, and the voltage value when the m value is even V2 _{m, n} is held by the second hold unit, (b) each pixel unit P _{m, n} in the m-th row is initialized after the first period, and (c) shorter than the first period after the initialization. A voltage value corresponding to the amount of charge generated in the photodiode of each pixel unit P _{m, n in} the _m-th row in response to light incidence over the second period is held as a voltage value V3 _{m, n by} the third hold unit. (D) When the m value is an odd number, the voltage value V1 held by the first hold unit _{m, n} and the voltage value V3 _{m, n} held by the third hold unit are input to the output selection unit, and the voltage value V1 _{m, n} or the voltage value V3 _{m, n} is selectively output from the output selection unit. When the m value is an even number, the voltage value V2 _{m, n} held by the second hold unit and the voltage value V3 _{m, n} held by the third hold unit are input to the output selection unit, and the voltage value V2 _{m , n} or voltage value V3 _{m, n} is selectively output from the output selection unit .

The solid-state imaging device according to the present invention sequentially operates as follows for each of the first to Mth rows in the light receiving unit. The voltage value corresponding to the amount of charge generated in the photodiode of each pixel unit P _{m, n in} the _m-th row in response to light incidence over the first period is the voltage value V1 _{m, n} or the voltage value V2 _{m, n} Are alternately held by the first hold unit or the second hold unit. After the first period, each pixel unit P _{m, n} in the m-th row is initialized. After this initialization, the voltage value corresponding to the amount of charge generated in the photodiode of each pixel unit P _{m, n in} the _m-th row in response to the light incidence over the second period shorter than the first period is the voltage value V3 _{m, n} is held by the third hold unit. The voltage value V1 _{m, n} or the voltage value V2 _{m, n} held by the first hold unit or the second hold unit and the voltage value V3 _{m, n} held by the third hold unit are the output selection unit The voltage value V1 _{m, n} or the voltage value V2 _{m, n} or the voltage value V3 _{m, n} is selectively output from the output selection unit. In this output selection unit, the voltage value V1 _{m, n} or the voltage value V2 _{m, n} is compared with the reference voltage value Vsat, a signal indicating the comparison result is output, and the voltage value V1 _{m, n} Alternatively, when the voltage value V2 _{m, n} is less than the reference voltage value Vsat, the voltage value V1 _{m, n} or the voltage value V2 _{m, n} is selectively output, otherwise the voltage value V3 _{m, n} is selectively output. Is done.

  In the operation of the solid-state imaging device according to the present invention, the first period for a certain row and the first period for another certain row may partially overlap each other. In addition, a first period for a certain row and a second period for another certain row may partially overlap each other. Further, the second period for a certain row may be part of the first period for another certain row. Rather, in order to increase the frame rate, it is preferable that some or all of these overlap each other. Further, the present invention can be applied to any of an APS (Active Pixel Sensor) system and a PPS (Passive Pixel Sensor) system.

  The solid-state imaging device according to the present invention can be downsized and inexpensive.

  The best mode for carrying out the present invention will be described below in detail with reference to the accompanying drawings. In the description of the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted.

(First embodiment)
First, a first embodiment of a solid-state imaging device according to the present invention will be described. FIG. 1 is a schematic configuration diagram of a solid-state imaging device 1 according to the first embodiment. The solid-state imaging device 1 shown in this figure is of the APS system, and includes a light receiving unit 11, a first hold unit 21, a second hold unit 22, an output selection unit 31, an AD conversion unit 40, a bias unit 50, and a control. The unit 61 is provided. These are preferably formed monolithically on a common substrate, and an example of the arrangement on the substrate in that case is as shown in the figure.

The light receiving unit 11 includes APS pixel units P _{1,1 to} P _{M, N} that are two-dimensionally arranged in M rows and N columns. Each pixel unit P _{m, n} includes a photodiode that generates an amount of charge corresponding to the amount of incident light. Here, M and N are integers of 2 or more, m is an arbitrary integer of 1 to M, and n is an arbitrary integer of 1 to N.

The first hold unit 21 inputs a voltage value corresponding to the amount of charge generated in each of _{the N} pixel units P _{m, 1 to} P _{m, N} in any m-th row in the light receiving unit 11. These are held and output as voltage values V1 _{m, 1 to} V1 _{m, N.} Similarly, the second hold unit 22 has a voltage value corresponding to the amount of charge generated in each of _{the N} pixel units P _{m, 1 to} P _{m, N} in any m-th row in the light receiving unit 11. These are held and output as voltage values V2 _{m, 1 to} V2 _{m, N.}

The output selection unit 31 inputs _N voltage values V1 _{m, 1 to} V1 _m, N output from the first hold unit 21 _{and N} voltage values V2 _m output from the second hold unit 22. _{, 1 to} V2 _{m, N} are also input. The output selection unit 31 compares the voltage value V1 _{m, n} with the reference voltage value Vsat, outputs a mode_out signal indicating the comparison result, and the voltage value V1 _{m, n} is less than the reference voltage value Vsat. When it is, the voltage value V1 _{m, n} is selectively output, and when not, the voltage value V2 _{m, n} is selectively output.

  The AD conversion unit 40 receives the voltage value output from the output selection unit 31, converts the voltage value (analog value) into a digital value, and outputs the digital value video_data. The bias unit 50 supplies a reference voltage to each of the light receiving unit 11, the output selection unit 31, and the AD conversion unit 40. The control unit 61 controls the operations of the light receiving unit 11, the first hold unit 21, the second hold unit 22, the output selection unit 31, and the AD conversion unit 40 based on the CLK signal and ST signal input from the outside. Control signals for generating and outputting the control signals, and includes a logic circuit such as a shift register.

FIG. 2 is a configuration diagram of the light receiving unit 11, the first hold unit 21, and the second hold unit 22 included in the solid-state imaging device 1 according to the first embodiment. In the light receiving unit 11, M × N pixel units P _{1,1 to} P _{M, N} having a common configuration are two-dimensionally arranged, and the pixel unit P _{m, n} is positioned in the _m- th row and the n-th column. is doing. The first hold unit 21 includes N hold circuits H _{1,1 to} H _{1, N.} The second hold unit 22 includes N hold circuits H _{2, 1 to} H _{2, N.} The N hold circuits H _{1,1 to} H _{1, N} and the N hold circuits H _{2,1 to} H _{2, N} have a common configuration.

The output ends of the _M pixel units P _{1, n to} P _{M, n in} the n-th column included in the light receiving unit 11, the input ends of the hold circuits H _{1, n} included in the first hold unit 21, and the first The input terminals of the hold circuits H2 _{, n} included in the 2-hold unit 22 are connected by a common wiring Vline (n). The output terminals of the _N hold circuits H _{1,1 to} H _{1, N} included in the first hold unit 21 are connected by a common wiring. The output terminals of the _N hold circuits H _{2, 1 to} H _{2, N} included in the second hold unit 22 are connected by a common wiring.

FIG. 3 is a circuit diagram of the pixel unit P _{m, n} , the hold circuit H _{1, n} and the hold circuit H _{2, n} included in the solid-state imaging device 1 according to the first embodiment. Each APS pixel portion _{Pm, n} includes a photodiode PD and four transistors T1 to T4. As shown in this figure, the transistor T1, the transistor T2, and the photodiode PD are connected in series in order, and the reference voltage Vb1 supplied from the bias unit 50 is input to the drain terminal of the transistor T1, and the photodiode PD The anode terminal is grounded. The transistors T3 and T4 are connected in series, the reference voltage Vb2 supplied from the bias unit 50 is input to the drain terminal of the transistor T3, and the source terminal of the transistor T4 is connected to the wiring Vline (n). . A connection point between the transistor T1 and the transistor T2 is connected to the gate terminal of the transistor T3. A constant current source is connected to the wiring Vline (n).

The Vreset (m) signal supplied from the control unit 61 is input to the gate terminal of the transistor T1, and the Vtrans (m) signal supplied from the control unit 61 is input to the gate terminal of the transistor T2 and supplied from the control unit 61. Vaddress (m) signal is input to the gate terminal of the transistor T4. These Vreset (m) signal, Vtrans (m) signal and Vaddress (m) signal are input in common to _{the N} pixel portions P _{m, 1 to} P _{m, N} in the m-th row. When the Vreset (m) signal and the Vtrans (m) signal are at a high level, the junction capacitance portion of the photodiode PD is discharged. When the Vaddress (m) signal is further set to the high level in the discharged state, a noise component is output from the pixel portion Pm _{, n} to the wiring Vline (n). When the Vreset (m) signal is at a low level and the Vtrans (m) signal and the Vaddress (m) signal are at a high level, a voltage value corresponding to the amount of charge accumulated in the junction capacitance portion of the photodiode PD Is output as a signal component to the wiring Vline (n).

Each hold circuit H1 _{, n} included in the first hold unit 21 includes two capacitive elements C1, C2 and four switches SW11, SW12, SW21, SW22. In the hold circuit H1 _{, n} , the switch SW11 and the switch SW12 are connected in series and provided between the wiring Vline (n) and the wiring Hline_s1, and one end of the capacitor C1 is connected to the switch SW11 and the switch SW12. The other end of the capacitive element C1 is grounded. The switch SW21 and the switch SW22 are connected in series and provided between the wiring Vline (n) and the wiring Hline_n1, and one end of the capacitor C2 is connected to a connection point between the switch SW21 and the switch SW22. The other end of the capacitive element C2 is grounded.

In the hold circuit H1 _{, n} , the switch SW11 opens and closes according to the level of the set_s1 signal supplied from the control unit 61. The switch SW21 opens and closes according to the level of the set_n1 signal supplied from the control unit 61. The set_s1 signal and the set_n1 signal are input in common to _{the N} hold circuits H _{1,1 to} H _{1, N} included in the first hold unit 21. The switches SW12 and SW22 open and close according to the level of the hshiht (n) signal supplied from the control unit 61.

In the hold circuit H1 _{, n} , the noise component output from the pixel unit Pm _{, n} to the wiring Vline (n) when the set_n1 signal changes from the high level to the low level is subsequently applied to the voltage by the capacitive element C2. Stored as value out_n1 (n). The signal component output from the pixel unit P _{m, n} to the wiring Vline (n) when the set_s1 signal changes from the high level to the low level is thereafter held as the voltage value out_s1 (n) by the capacitive element C1. . When the hshiht (n) signal becomes high level, the voltage value out_s1 (n) held by the capacitive element C1 is output to the wiring Hline_s1, and the voltage value out_n1 (n) held by the capacitive element C2 is wired. Output to Hline_n1. The difference between the voltage value out_s1 (n) and the voltage value out_n1 (n) represents the voltage value V1m _{, n} corresponding to the amount of charge generated in the photodiode PD of the pixel portion Pm _{, n} .

Each hold circuit H2 _{, n} included in the second hold unit 22 includes two capacitive elements C1, C2 and four switches SW11, SW12, SW21, SW22. In the hold circuit H2 _{, n} , the switch SW11 and the switch SW12 are connected in series and provided between the wiring Vline (n) and the wiring Hline_s2, and one end of the capacitor C1 is connected to the switch SW11 and the switch SW12. The other end of the capacitive element C1 is grounded. The switch SW21 and the switch SW22 are connected in series and provided between the wiring Vline (n) and the wiring Hline_n2, and one end of the capacitor C2 is connected to a connection point between the switch SW21 and the switch SW22. The other end of the capacitive element C2 is grounded.

In the hold circuit H2 _{, n} , the switch SW11 opens and closes according to the level of the set_s2 signal supplied from the control unit 61. The switch SW21 opens and closes according to the level of the set_n2 signal supplied from the control unit 61. The set_s2 signal and the set_n2 signal are input in common to _{the N} hold circuits H _{2, 1 to} H _{2, N} included in the second hold unit 22. The switches SW12 and SW22 open and close according to the level of the hshiht (n) signal supplied from the control unit 61.

In the hold circuit H2 _{, n} , the noise component output from the pixel unit Pm _{, n} to the wiring Vline (n) when the set_n2 signal changes from the high level to the low level is subsequently applied to the voltage by the capacitive element C2. Stored as value out_n2 (n). The signal component output from the pixel portion P _{m, n} to the wiring Vline (n) when the set_s2 signal changes from the high level to the low level is thereafter held as the voltage value out_s2 (n) by the capacitive element C1. . When the hshiht (n) signal becomes high level, the voltage value out_s2 (n) held by the capacitive element C1 is output to the wiring Hline_s2, and the voltage value out_n2 (n) held by the capacitive element C2 is wired. Output to Hline_n2. The difference between the voltage value out_s2 (n) and the voltage value out_n2 (n) represents the voltage value V2m _{, n} corresponding to the amount of charge generated in the photodiode PD of the pixel portion Pm _{, n} .

  FIG. 4 is a configuration diagram of the output selection unit 31 included in the solid-state imaging device 1 according to the first embodiment. The output selection unit 31 includes a difference calculation circuit 311, a difference calculation circuit 312, a comparison circuit 313, a latch circuit 314, a logic inversion circuit 315, switches SW30 to SW32, and switches SW40 to SW42.

The first input terminal of the difference calculation circuit 311 is connected to the wiring Hline_s1 through the buffer amplifier, and receives the voltage value out_s1 (n) output from the hold circuits H1 _{, n} to the wiring Hline_s1. The second input terminal of the difference calculation circuit 311 is connected to the wiring Hline_n1 via the buffer amplifier, and receives the voltage value out_n1 (n) output from the hold circuits H1 _{, n} to the wiring Hline_n1. Then, the difference calculation circuit 311 outputs a voltage value V1 _{m, n} representing the difference between the voltage value out_s1 (n) and the voltage value out_n1 (n).

The first input terminal of the difference calculation circuit 312 is connected to the wiring Hline_s2 via the buffer amplifier, and receives the voltage value out_s2 (n) output from the hold circuit H2 _{, n} to the wiring Hline_s2. The second input terminal of the difference calculation circuit 312 is connected to the wiring Hline_n2 via the buffer amplifier, and receives the voltage value out_n2 (n) output from the hold circuits H2 _{, n} to the wiring Hline_n2. Then, the difference calculation circuit 312 outputs a voltage value V2 _{m, n} representing the difference between the voltage value out_s2 (n) and the voltage value out_n2 (n).

  The wiring Hline_s1 is grounded via the switch SW31, and the input voltage value to the first input terminal of the difference calculation circuit 311 is initialized by closing the switch SW31. The wiring Hline_n1 is grounded via the switch SW32, and the input voltage value to the second input terminal of the difference calculation circuit 311 is initialized by closing the switch SW32. The wiring Hline_s2 is grounded via the switch SW41, and the input voltage value to the first input terminal of the difference calculation circuit 312 is initialized by closing the switch SW41. The wiring Hline_n2 is grounded via the switch SW42, and the input voltage value to the second input terminal of the difference calculation circuit 312 is initialized by closing the switch SW42. The opening / closing operations of these switches SW31, SW32, SW41, SW42 are controlled by an hreset signal supplied from the control unit 61.

The comparison circuit 313 compares the voltage value V1 _{m, n} output from the difference calculation circuit 311 with the reference voltage value Vsat, and outputs a mode_out signal indicating the comparison result. The latch circuit 314 receives the mode_out signal output from the comparison circuit 313, holds the mode_out signal for a certain period, and outputs it. The logic inversion circuit 315 receives the mode_out signal output from the latch circuit 314, inverts the logic, and outputs the inverted signal.

One end of the switch SW30 is connected to the output terminal of the difference calculation circuit 311 and opens and closes based on the mode_out signal output from the latch circuit 314. One end of the switch SW40 is connected to the output terminal of the difference calculation circuit 312, and opens and closes based on a signal (inverted signal of the mode_out signal) output from the logic inverting circuit 315. When one of the switch SW30 and the switch SW40 is open, the other is closed, the other end of the switch SW30 and the other end of the switch SW40 are connected to each other, and the video_a signal output from the connection point is The voltage value V1 _{m, n is one} of the voltage value V2 _{m, n} .

Therefore, Video_a signal outputted from the output selection unit 31, the voltage value V1 _{m, n} becomes when the voltage value V1 _{m, n} is less than the reference voltage value Vsat, a voltage value V2 _{m, n} otherwise. Here, the reference voltage value Vsat is set to an appropriate value so that the comparison circuit 313 can determine whether or not the voltage value V1 _{m, n} is saturated. The AD conversion unit 40 receives the video_a signal output from the output selection unit 31, converts the voltage value (analog value) of this signal into a digital value, and outputs the digital value video_data.

  FIG. 5 is a circuit diagram of the difference calculation circuits 311 and 312 included in the output selection unit 31. The difference calculation circuits 311 and 312 have a common configuration and include a differential amplifier A and resistors R1 to R4. The inverting input terminal of the differential amplifier A receives the voltage value v1 through the resistor R1, and is connected to the output terminal of the differential amplifier A through the resistor R2. The non-inverting input terminal of the differential amplifier A receives the voltage value v2 through the resistor R3 and is grounded through the resistor R4. When the resistance values of the resistors R1 to R4 are equal, the voltage value vd output from the output terminal of the differential amplifier A is the difference between the two input voltage values v1 and v2.

  Next, the operation of the solid-state imaging device 1 according to the first embodiment will be described. FIG. 6 is a timing chart for explaining the level change of each signal in the solid-state imaging device 1 according to the first embodiment. Each signal shown in this timing chart will be described in order from the top as follows.

  The CLK signal is a signal input from the outside to the control unit 61 and is a master clock signal for operating the entire solid-state imaging device 1. The ST signal is a signal that is input from the outside to the control unit 61 and is a master start signal that instructs the start of reading. The Vst signal is a signal generated by the control unit 61 and is a start signal that instructs the start of the operation of sequentially selecting the first to Mth rows of the light receiving unit 11. The Vclk signal is a signal generated by the control unit 61 and is a clock signal for instructing to sequentially select each row of the light receiving unit 11, and the Vshift signal changes based on this.

  The Vreset signal is a signal created by the control unit 61, and is a signal for instructing resetting of the pixel units in the row selected by the Vshift signal. The Vtrans signal is a signal generated by the control unit 61 and is a signal that instructs pixel data transfer of the pixel unit in the row selected by the Vshift signal. The Vaddress signal is a signal created by the control unit 61 and is a signal that instructs reading of pixel data of the pixel portion in the row selected by the Vshift signal. The Vshift signal is a signal created by the control unit 61 based on the Vclk signal and the Vst signal, and is a signal for instructing selection of a row of the light receiving unit 11.

  The set_n1 signal is a signal created by the control unit 61 and is a signal for instructing the first hold circuit 21 to hold the long-term accumulation data (noise component) output from the pixel unit. The set_s1 signal is a signal created by the control unit 61 and is a signal for instructing the first hold circuit 21 to hold the long-term accumulated data (signal component) output from the pixel unit. The set_n2 signal is a signal created by the control unit 61 and is a signal for instructing the second hold circuit 22 to hold the short-term accumulation data (noise component) output from the pixel unit. The set_s2 signal is a signal created by the control unit 61 and is a signal for instructing the second hold circuit 22 to hold the short-term accumulation data (signal component) output from the pixel unit.

  The Hst signal is a signal generated by the control unit 61 and is a start signal that instructs the start of data reading from each of the first hold circuit 21 and the second hold circuit 22. The Hclk signal is a signal generated by the control unit 61 and is a clock signal instructing sequential reading of data from each of the first hold circuit 21 and the second hold circuit 22. The Hshift signal is a signal created by the control unit 61 based on the Hclk signal and the Hst signal, and is a signal instructing data reading from each of the first hold circuit 21 and the second hold circuit 22. The video_a signal is a signal output from the output selection unit 31 and is a value corresponding to the amount of light incident on the photodiode included in the pixel unit.

  FIG. 7 is a timing chart for explaining the operation of the solid-state imaging device 1 according to the first embodiment. This figure shows the timing of charge accumulation in the photodiode of each pixel unit of the light receiving unit 11, the timing at which the voltage value output from the light receiving unit 11 is held by each of the first hold unit 21 and the second hold unit 22, and The timing at which the voltage value held by each of the first hold unit 21 and the second hold unit 22 is output to the output selection unit 31 is shown. This operation is performed based on each control signal output from the control unit 61 as shown in FIG. Here, for the sake of simplicity of illustration, the M value is 4 and the N value is 4.

In this timing chart, in order from the top, the charge accumulation operation in the photodiodes of the pixel portions P _{1,1 to} P _1,4 in the first row, the pixel portions P _{2,1 to} P _2,4 in the second row, respectively. Charge accumulation operation in the photodiodes of the third row, charge accumulation operations in the photodiode portions of the pixel portions P _{3,1 to} P _3,4 in the third row, and the respective photos of the pixel portions P _{4,1 to} P _4,4 in the fourth row. Charge accumulation operation in the diode, voltage value holding operation by each of the hold circuits H _{1,1 to} H _1,4 included in the first hold unit 21, and hold circuits H _{2,1 to} H _2, included in the second hold unit 22 ₄ shows a voltage value holding operation and a video_a signal output operation from the output selection unit 31.

  In the light receiving unit 11, the N pixel units in each row operate at the same timing, but operate at different timings for each fixed time between rows. Then, the following operation is sequentially performed for each of the first to Mth rows in the light receiving unit 11.

The photodiode of each pixel unit P _{m, n in} the m-th row has a charge accumulation operation corresponding to light incidence over the first period T1, an initialization operation after the first period T1, and light incidence over the second period T2. The charge accumulation operation according to the above and the initialization operation after the second period T2 are repeated. However, the second period T2 is shorter than the first period T1. T1 and T2 shown in the upper part of FIG. 7 indicate the pixel portions P _{1, n} (n = 1 to 4) in the first row.

The voltage value corresponding to the amount of charge generated in the photodiode of each pixel unit P _{m, n in} the _m-th row in response to the light incidence over the first period T1 passes through the wiring Vline (n), and the first hold unit 21 It is input to and held by the holding circuit H _{1, n} of the first holding portion 21 as a voltage value V1 _{m, n.} At this time, the hold circuit H1 _{, n} holds the signal component out_s1 (n) and the noise component out_n1 (n), and the difference between the signal component out_s1 (n) and the noise component out_n1 (n) is a voltage value V1. _{m and n} are represented. After the first period T1, each pixel unit P _{m, n} in the m-th row is initialized.
After this initialization, the voltage value corresponding to the amount of charge generated in the photodiodes of the pixel units P _{m, n in} the _m-th row in response to light incidence over the second period T2 shorter than the first period T1 is: The voltage is input to the second hold unit 22 via the wiring Vline (n), and is held by the hold circuit H2 _{, n} of the second hold unit 22 as the voltage value V2m _{, n} . At this time, the hold circuit H2 _{, n} holds the signal component out_s2 (n) and the noise component out_n2 (n), and the difference between the signal component out_s2 (n) and the noise component out_n2 (n) is a voltage value V2. _{m and n} are represented. After the second period T2, each pixel unit P _{m, n} in the m-th row is initialized.
The voltage value V1 _{m, n} held by the first hold unit 21 is input to the output selection unit 31 via the wirings Hline_s1 and Hline_n1. The voltage value V2 _{m, n} held by the second hold unit 22 is input to the output selection unit 31 via the wirings Hline_s2 and Hline_n2. First, the voltage value V1 _{m, 1} and the voltage value V2 _{m, 1} are input to the output selection unit 31, then the voltage value V1 _{m, 2} and the voltage value V2 _{m, 2} are input, and then the voltage value V1. _{m, 3} and voltage value V2 _{m, 3} are input, and so on, voltage values V1 _{m, n} , V2 _{m, n} are input in order from the first column to the Nth column. The voltage value V1 _{m, n} or the voltage value V2 _{m, n} is selectively output from the output selection unit 31.

The value of the video_a signal output from the output selection unit 31 is the voltage value V1 _{m, n} when the voltage value V1 _{m, n} is less than the reference voltage value Vsat (that is, when the voltage value V1 _{m, n} is not saturated) _{. n} , otherwise the voltage value V2 _{m, n} . As described above, the voltage value V1 _{m, n} is a voltage value corresponding to the amount of charge generated in the photodiode of the pixel unit P _{m, n} in response to light incidence over a relatively long first period T1, The voltage value V2 _{m, n} is a voltage value corresponding to the amount of charge generated in the photodiode of the pixel unit P _{m, n} in response to light incidence over a relatively short second period T2.

When the light incident intensity is relatively small, the voltage value V1 _{m, n} is not saturated even if the charge accumulation time is relatively long, so this voltage value V1 _{m, n} is selected. When the light incident intensity is relatively high, the voltage value V1 _{m, n} is saturated, so the voltage value V2 _{m, n} is selected. Therefore, in the solid-state imaging device 1, the dynamic range is expanded for each of the plurality of pixel units. In addition, the solid-state imaging device 1 does not require a frame memory, and only a small circuit is added. Therefore, the solid-state imaging device 1 can be reduced in size and can be inexpensive.

  Further, in the solid-state imaging device 1, the first hold unit 21 and the second hold are performed by accumulating charges over a relatively short second period T 2 after accumulating charges over a relatively long first period T 1. The difference in the voltage value holding timing of each unit 22 is small. In addition, after that, until the processing by the output selection unit 31 is completed, the time during which each of the first hold unit 21 and the second hold unit 22 holds the voltage value is short. Therefore, the scale of the additional circuit can be reduced also in this respect.

(Second Embodiment)
Next, a second embodiment of the solid-state imaging device according to the present invention will be described. FIG. 8 is a schematic configuration diagram of the solid-state imaging device 2 according to the second embodiment. The solid-state imaging device 2 shown in this figure is of the APS system, and includes a light receiving unit 11, a first hold unit 21, a second hold unit 22, a third hold unit 23, an output selection unit 32, and an AD conversion unit 40. , A bias unit 50 and a control unit 62 are provided. These are preferably formed monolithically on a common substrate, and an example of the arrangement on the substrate in that case is as shown in the figure.

  Compared with the configuration of the solid-state imaging device 1 according to the previous first embodiment, the solid-state imaging device 2 according to the second embodiment is further provided with a third hold unit 23, and is an output selection instead of the output selection unit 31. The difference is that the unit 32 is provided, and the control unit 62 is provided instead of the control unit 61.

The third hold unit 23 has the same configuration as each of the first hold unit 21 and the second hold unit 22, and the N pixel units P _{m, 1} to n in any m-th row in the light receiving unit 11. A voltage value corresponding to the amount of charge generated in each photodiode of P _{m, N} is input, and these are held and output as voltage values V3 _{m, 1 to} V3 _{m, N.}

The output selection unit 32 inputs _N voltage values V1 _{m, 1 to} V1 _m, N output from the first hold unit 21 _{, and N} voltage values V2 _m, N output from the second hold unit 22 _{. 1} to V2 _m, type the _N, also, N pieces of the voltage values output from the third holding portion 23 V3 _m, 1 ~V3 _m, also inputs the _N. The output selection unit 32 compares the voltage value V1 _{m, n} or the voltage value V2 _{m, n} with the reference voltage value Vsat, outputs a mode_out signal indicating the comparison result, and outputs the voltage value V1 _{m, n When n} or voltage value V2 _{m, n} is less than reference voltage value Vsat, voltage value V1 _{m, n} or voltage value V2 _{m, n} is selectively output, otherwise voltage value V3 _{m, n} is selectively output. Output.

  The AD conversion unit 40 receives the voltage value output from the output selection unit 32, converts the voltage value (analog value) into a digital value, and outputs the digital value video_data. The bias unit 50 supplies a reference voltage to each of the light receiving unit 11, the output selection unit 32, and the AD conversion unit 40. Based on the CLK signal and ST signal input from the outside, the control unit 62 receives the light receiving unit 11, the first hold unit 21, the second hold unit 22, the third hold unit 23, the output selection unit 32, and the AD conversion unit 40. It generates and outputs a control signal for controlling each operation, and includes a logic circuit such as a shift register.

FIG. 9 is a configuration diagram of the light receiving unit 11, the first hold unit 21, the second hold unit 22, and the third hold unit 23 included in the solid-state imaging device 2 according to the second embodiment. In the light receiving unit 11, M × N pixel units P _{1,1 to} P _{M, N} having a common configuration are two-dimensionally arranged, and the pixel unit P _{m, n} is positioned in the _m- th row and the n-th column. is doing. The first hold unit 21 includes N hold circuits H _{1,1 to} H _{1, N.} The second holding portion 22 includes N holding circuits _{H 2,1} to H _{2, N.} The third hold unit 23 includes N hold circuits H _{3,1 to} H _{3, N.} N hold circuits H _{1,1 to} H _{1, N} , N hold circuits H _{2,1 to} H _{2, N} and N hold circuits H _{3,1 to} H _{3, N} have a common configuration. .

The output ends of the _M pixel units P _{1, n to} P _{M, n in} the n-th column included in the light receiving unit 11, the input ends of the hold circuits H _{1, n} included in the first hold unit 21, and the second hold The input terminal of the hold circuit H2 _{, n} included in the unit 22 and the input terminal of the hold circuit H3 _{, n} included in the third hold unit 23 are connected by a common wiring Vline (n). The output terminals of the _N hold circuits H _{1,1 to} H _{1, N} included in the first hold unit 21 are connected by a common wiring. The output terminals of the _N hold circuits H _{2, 1 to} H _{2, N} included in the second hold unit 22 are connected by a common wiring. The output terminals of the _N hold circuits H _{3,1 to} H _{3, N} included in the third hold unit 23 are connected by a common wiring.

FIG. 10 is a circuit diagram of a pixel unit P _{m, n} , a hold circuit H _{1, n} , a hold circuit H _{2, n} and a hold circuit H _{3, n} included in the solid-state imaging device 2 according to the second embodiment. Each pixel unit P _{m, n} , each hold circuit H _{1, n} included in the first hold unit 21 and each hold circuit H _{2, n} included in the second hold unit 22 are shown in FIG. The configuration is the same as that described above.

Each hold circuit H _{3, n} included in the third hold unit 23 includes two capacitive elements C1, C2, and four switches SW11, SW12, SW21, SW22. In the hold circuit H3 _{, n} , the switch SW11 and the switch SW12 are connected in series and provided between the wiring Vline (n) and the wiring Hline_s3, and one end of the capacitor C1 is connected to the switch SW11 and the switch SW12. The other end of the capacitive element C1 is grounded. The switches SW21 and SW22 are connected in series and provided between the wiring Vline (n) and the wiring Hline_n3, and one end of the capacitor C2 is connected to a connection point between the switch SW21 and the switch SW22. The other end of the capacitive element C2 is grounded.

In the hold circuit H _{3, n} , the switch SW11 opens and closes according to the level of the set_s3 signal supplied from the control unit 62. The switch SW21 opens and closes according to the level of the set_n3 signal supplied from the control unit 62. The set_s3 signal and the set_n3 signal are input in common to _{the N} hold circuits H _{3,1 to} H _{3, N} included in the third hold unit 23. The switches SW12 and SW22 open and close according to the level of the hshiht (n) signal supplied from the control unit 62.

In the hold circuit H3 _{, n} , the noise component output from the pixel unit Pm _{, n} to the wiring Vline (n) when the set_n3 signal changes from the high level to the low level is subsequently applied to the voltage by the capacitive element C2. Stored as value out_n3 (n). The signal component output from the pixel portion P _{m, n} to the wiring Vline (n) when the set_s3 signal changes from the high level to the low level is thereafter held as the voltage value out_s3 (n) by the capacitive element C1. . When the hshiht (n) signal becomes high level, the voltage value out_s3 (n) held by the capacitive element C1 is output to the wiring Hline_s3, and the voltage value out_n3 (n) held by the capacitive element C2 is output to the wiring. Output to Hline_n3. The difference between the voltage value out_s3 (n) and the voltage value out_n3 (n) represents the voltage value V3m _{, n} corresponding to the amount of charge generated in the photodiode PD of the pixel portion Pm _{, n} .

  FIG. 11 is a configuration diagram of the output selection unit 32 included in the solid-state imaging device 2 according to the second embodiment. The output selection unit 32 includes a difference calculation circuit 311, a difference calculation circuit 312, a comparison circuit 313, a latch circuit 314, a logic inversion circuit 315, switches SW30 to SW34, switches SW41 to SW44, and switches SW50 to SW52.

The first input terminal of the difference calculation circuit 311 is connected to the wiring Hline_s1 through the switch SW33 and the buffer amplifier, and is connected to the wiring Hline_s2 through the switch SW43 and the buffer amplifier. When the switch SW33 is closed, the voltage value out_s1 (n) output from the hold circuit H1 _{, n} to the wiring Hline_s1 is input. On the other hand, when the switch SW43 is closed, from the hold circuit H2 _{, n.} The voltage value out_s2 (n) output to the wiring Hline_s2 is input.

The second input terminal of the difference calculation circuit 311 is connected to the wiring Hline_n1 through the switch SW34 and the buffer amplifier, and is connected to the wiring Hline_n2 through the switch SW44 and the buffer amplifier. The second input terminal receives a voltage value out_n1 (n) output from the hold circuit H1 _{, n} to the wiring Hline_n1 when the switch SW34 is closed, and on the other hand, when the switch SW44 is closed, the hold circuit The voltage value out_n2 (n) output from H2 _{, n} to the wiring Hline_n2 is input.

The switches SW33 and SW34 open and close at the same timing. Further, the switch SW43 and the switch SW44 also open and close at the same timing. When one of the switch SW33 and switch SW34 and the switch SW43 and switch SW44 is open, the other is closed. Therefore, when the switch SW33 and the switch SW34 are closed, the difference calculation circuit 311 outputs the voltage value V1 _{m, n} representing the difference between the voltage value out_s1 (n) and the voltage value out_n1 (n), while the switch SW33 and the switch SW34 are closed. when SW43 and the switch SW44 is closed, the voltage value V2 m representing the difference between the voltage value out_s2 (n) and the voltage value Out_n2 _(n), and outputs the _n.

The first input terminal of the difference calculation circuit 312 is connected to the wiring Hline_s3 via the buffer amplifier, and receives the voltage value out_s3 (n) output from the hold circuit H3 _{, n} to the wiring Hline_s3. The second input terminal of the difference calculation circuit 312 is connected to the wiring Hline_n3 via the buffer amplifier, and receives the voltage value out_n3 (n) output from the hold circuit H3 _{, n} to the wiring Hline_n3. Then, the difference calculation circuit 312 outputs a voltage value V3 _{m, n} representing the difference between the voltage value out_s3 (n) and the voltage value out_n3 (n).

  The wiring Hline_s1 is grounded via the switch SW31, and the input voltage value to the first input terminal of the difference calculation circuit 311 is initialized by closing the switch SW31. The wiring Hline_n1 is grounded via the switch SW32, and the input voltage value to the second input terminal of the difference calculation circuit 311 is initialized by closing the switch SW32. The wiring Hline_s2 is grounded via the switch SW41, and the input voltage value to the first input terminal of the difference calculation circuit 312 is initialized by closing the switch SW41. The wiring Hline_n2 is grounded via the switch SW42, and the input voltage value to the second input terminal of the difference calculation circuit 312 is initialized by closing the switch SW42. The wiring Hline_s3 is grounded via the switch SW51, and the input voltage value to the first input terminal of the difference calculation circuit 312 is initialized by closing the switch SW51. The wiring Hline_n3 is grounded via the switch SW52, and the input voltage value to the second input terminal of the difference calculation circuit 312 is initialized by closing the switch SW52. The opening / closing operations of these switches SW31, SW32, SW41, SW42, SW51, SW52 are controlled by an hreset signal supplied from the control unit 62.

The comparison circuit 313 compares the voltage value V1 _{m, n} or V2 _{m, n} output from the difference calculation circuit 311 with the reference voltage value Vsat, and outputs a mode_out signal indicating the comparison result. The latch circuit 314 receives the mode_out signal output from the comparison circuit 313, holds the mode_out signal for a certain period, and outputs it. The logic inversion circuit 315 receives the mode_out signal output from the latch circuit 314, inverts the logic, and outputs the inverted signal.

One end of the switch SW30 is connected to the output terminal of the difference calculation circuit 311 and opens and closes based on the mode_out signal output from the latch circuit 314. One end of the switch SW50 is connected to the output terminal of the difference calculation circuit 312, and opens and closes based on a signal (inverted signal of the mode_out signal) output from the logic inverting circuit 315. When one of the switch SW30 and the switch SW50 is open, the other is closed. The other end of the switch SW30 and the other end of the switch SW50 are connected to each other, and the video_a signal output from the connection point is , Voltage value V1 _{m, n,} voltage value V2 _{m, n,} or voltage value V3 _{m, n} .

Therefore, Video_a signal outputted from the output selection unit 32, the voltage value V1 _{m, n} becomes when the switch SW33 and the switch SW34 is closed the voltage value V1 _{m, n} is less than the reference voltage value Vsat, switches SW43 and When the switch SW44 is closed and the voltage value V2 _{m, n} is less than the reference voltage value Vsat, the voltage value V2 _{m, n is obtained} , and when it is not any of these, the voltage value V3 _{m, n} is obtained. Here, the reference voltage value Vsat is set to an appropriate value so that the comparison circuit 313 can determine whether or not the voltage value V1 _{m, n} or the voltage value V2 _{m, n} is saturated. The AD conversion unit 40 receives the video_a signal output from the output selection unit 32, converts the voltage value (analog value) of this signal into a digital value, and outputs the digital value video_data.

  Next, the operation of the solid-state imaging device 2 according to the second embodiment will be described. FIG. 12 is a timing chart for explaining the operation of the solid-state imaging device 2 according to the second embodiment. In this figure, the timing of charge accumulation in the photodiode of each pixel unit of the light receiving unit 11 and the voltage value output from the light receiving unit 11 are held by the first hold unit 21, the second hold unit 22, and the third hold unit 23, respectively. And the timing at which the voltage values held by the first hold unit 21, the second hold unit 22, and the third hold unit 23 are output to the output selection unit 32, respectively. This operation is performed based on each control signal output from the control unit 62. Here, for the sake of simplicity of illustration, the M value is 4 and the N value is 4.

In this timing chart, in order from the top, the charge accumulation operation in the photodiodes of the pixel portions P _{1,1 to} P _1,4 in the first row, the pixel portions P _{2,1 to} P _2,4 in the second row, respectively. Charge accumulation operation in the photodiodes of the third row, charge accumulation operations in the photodiode portions of the pixel portions P _{3,1 to} P _3,4 in the third row, and the respective photos of the pixel portions P _{4,1 to} P _4,4 in the fourth row. Charge accumulation operation in the diode, voltage value holding operation by each of the hold circuits H _{1,1 to} H _1,4 included in the first hold unit 21, and hold circuits H _{2,1 to} H _2, included in the second hold unit 22 ₄ voltage value holding operation by each of the voltage value holding operation by the holding circuit H _{3, 1} to H _{3, 4} respectively included in the third holding portion 23, and, Video_a signal output operation from the output selection unit 32 It is shown.

  In the light receiving unit 11, the N pixel units in each row operate at the same timing, but operate at different timings for each fixed time between rows. Then, the following operation is sequentially performed for each of the first to Mth rows in the light receiving unit 11.

The photodiode of each pixel unit P _{m, n in} the m-th row has a charge accumulation operation corresponding to light incidence over the first period T1, an initialization operation after the first period T1, and light incidence over the second period T2. The charge accumulation operation according to the above and the initialization operation after the second period T2 are repeated. However, the second period T2 is shorter than the first period T1. T1 and T2 shown in the upper part of FIG. 12 indicate the pixel portions P _{1, n} (n = 1 to 4) in the first row.

The voltage value corresponding to the amount of charge generated in the photodiode of each pixel unit P _{m, n in} the _m-th row in response to light incidence over the first period T1 is an odd m value via the wiring Vline (n). Is input to the first hold unit 21 and is held by the hold circuit H _{1, n} as the voltage value V1 _{m, n} . When the m value is even, it is input to the second hold unit 22 as the voltage value V2 _{m, n.} It is held by the hold circuit H _{2, n} . At this time, the hold circuit H1 _{, n} holds the signal component out_s1 (n) and the noise component out_n1 (n), and the difference between the signal component out_s1 (n) and the noise component out_n1 (n) is a voltage value V1. _{m and n} are represented. The hold circuit H2 _{, n} holds the signal component out_s2 (n) and the noise component out_n2 (n), and the difference between the signal component out_s2 (n) and the noise component out_n2 (n) is a voltage value V2m _{, n.} Represents. After the first period T1, each pixel unit P _{m, n} in the m-th row is initialized.

After this initialization, the voltage value corresponding to the amount of charge generated in the photodiodes of the pixel units P _{m, n in} the _m-th row in response to light incidence over the second period T2 shorter than the first period T1 is: The voltage is input to the third hold unit 23 via the wiring Vline (n), and is held as the voltage value V3 _{m, n by} the hold circuit H _{3, n} of the third hold unit 23. At this time, the hold circuit H3 _{, n} holds the signal component out_s3 (n) and the noise component out_n3 (n), and the difference between the signal component out_s3 (n) and the noise component out_n3 (n) is a voltage value V3. _{m and n} are represented. After the second period T2, each pixel unit P _{m, n} in the m-th row is initialized.
When the m value is an odd number, the output selection unit 32 receives the voltage value V1 _{m, n} held by the first hold unit 21 via the wirings Hline_s1 and Hline_n1, and when the m value is an even number, the second hold unit. The voltage value V2 _{m, n} held by the line 22 is input via the wirings Hline_s2 and Hline_n2, and the voltage value V3 _{m, n} held by the third hold unit 23 is changed to the lines Hline_s3 and Hline_n3 regardless of the m value. It is input after.

When the m value is an odd number, first, the voltage value V1 _{m, 1} and the voltage value V3 _{m, 1} are input to the output selection unit 32, and then the voltage value V1 _{m, 2} and the voltage value V3 _{m, 2} are input. Next, the voltage value V1 _{m, 3} and the voltage value V3 _{m, 3} are input, and so on, and so on, in order from the first column to the Nth column, the voltage value V1 _{m, n} and the voltage value V3 _{m, n} Is entered. When the m value is an even number, the voltage value V2 _{m, 1} and the voltage value V3 _{m, 1} are _first input to the output selection unit 32, and then the voltage value V2 _{m, 2} and the voltage value V3 _{m, 2} are input. Next, the voltage value V2 _{m, 3} and the voltage value V3 _{m, 3} are input, and so on, and so on, in order from the first column to the Nth column, the voltage value V2 _{m, n} and the voltage value V3 _{m, n} Is entered. When the m value is an odd number, the voltage value V1 _{m, n} or the voltage value V3 _{m, n} is selectively output from the output selection unit 32. When the m value is an even number, the voltage value V2 _{m, n} or the voltage value V3 _{m, n} is selectively output from the output selector 32.

The value of the video_a signal output from the output selection unit 32 is when the m value is an odd number and the voltage value V1 _{m, n} is less than the reference voltage value Vsat (that is, the voltage value V1 _{m, n} is not saturated). Voltage value V1 _{m, n} , when the m value is an even number and the voltage value V2 _{m, n} is less than the reference voltage value Vsat (that is, when the voltage value V2 _{m, n} is not saturated). V2 _{m, n} , and when none of these, the voltage value V3 _{m, n} . As described above, each of the voltage value V1 _{m, n} and the voltage value V2 _{m, n} is the amount of charge generated in the photodiode of the pixel unit P _{m, n} in response to light incidence over a relatively long first period T1. The voltage value V3 _{m, n} is a voltage value corresponding to the amount of charge generated in the photodiode of the pixel portion P _{m, n} in response to light incidence over a relatively short second period T2. It is.

When the light incident intensity is relatively small, the voltage value V1 _{m, n} or the voltage value V2 _{m, n} is not saturated even if the charge accumulation time is relatively long. Therefore, the voltage value V1 _{m, n} or the voltage value V2 _{m and n} are selected. When the light incident intensity is relatively high, the voltage value V1 _{m, n} or the voltage value V2 _{m, n} is saturated, so the voltage value V3 _{m, n} is selected. Therefore, in the solid-state imaging device 2, the dynamic range is expanded for each of the plurality of pixel units. Further, the solid-state imaging device 2 does not require a frame memory, and only a small circuit is added, so that it can be downsized and can be made inexpensive.

  Further, in this solid-state imaging device 2, the charge is accumulated over a relatively long first period T1, and then the charge is accumulated over a relatively short second period T2, whereby the first hold unit 21 and the second hold unit 21. The difference in the voltage value holding timing of each unit 22 is small. In addition, after that, until the processing by the output selection unit 32 is completed, the time during which each of the first hold unit 21 and the second hold unit 22 holds the voltage value is short. Therefore, the scale of the additional circuit can be reduced also in this respect.

  Further, since the solid-state imaging device 2 uses the first hold circuit 21 and the second hold circuit 22 alternately, for example, during a period in which a voltage value is read for a certain row from the first hold circuit 21. The second hold circuit 22 can hold the voltage value for the next row. As a result, while the processing by the output selection unit 32 is being performed for a certain row, charge accumulation in the second period of the next row becomes possible. Therefore, in the solid-state imaging device 2 of the second embodiment, the degree of freedom of setting of each of the first period T1 and the second period T2 is high, and the frame rate is made higher than the solid-state imaging device 1 of the first embodiment. It is possible.

(Third embodiment)
Next, a third embodiment of the solid-state imaging device according to the present invention will be described. FIG. 13 is a schematic configuration diagram of a solid-state imaging device 3 according to the third embodiment. The solid-state imaging device 3 shown in this figure is of the PPS system, and includes a light receiving unit 13, an integrating unit 20, a first holding unit 24, a second holding unit 25, an output selecting unit 33, an AD converting unit 40, a bias. Unit 50 and control unit 63. These are preferably formed monolithically on a common substrate, and an example of the arrangement on the substrate in that case is as shown in the figure.

The light receiving unit 13 includes PPS pixel units P _{1,1 to} P _{M, N} two-dimensionally arranged in M rows and N columns. Each pixel unit P _{m, n} includes a photodiode that generates an amount of charge corresponding to the amount of incident light. Here, M and N are integers of 2 or more, m is an arbitrary integer of 1 to M, and n is an arbitrary integer of 1 to N.

The integrating unit 20 inputs charges generated in the photodiodes of the _N pixel units P _{m, 1 to} P _{m, N} in any m-th row in the light receiving unit 13, and a voltage corresponding to the amount of the charges. Output the value. The first hold unit 24 receives the voltage values output from the integration unit 20, holds these as voltage values V1 _{m, 1 to} V1 _{m, N} , and outputs them. Similarly, the second hold unit 25 receives the voltage values output from the integrating unit 20, holds these as voltage values V2m _{, 1 to} V2m _{, N} , and outputs them.

The output selection unit 33 inputs _N voltage values V1 _{m, 1 to} V1 _m, N output from the first hold unit 24 _{and N} voltage values V2 _m output from the second hold unit 25. _{, 1 to} V2 _{m, N} are also input. The output selection unit 33 compares the voltage value V1 _{m, n} with the reference voltage value Vsat, outputs a mode_out signal indicating the comparison result, and the voltage value V1 _{m, n} is less than the reference voltage value Vsat. When it is, the voltage value V1 _{m, n} is selectively output, and when not, the voltage value V2 _{m, n} is selectively output.

  The AD conversion unit 40 receives the voltage value output from the output selection unit 33, converts the voltage value (analog value) into a digital value, and outputs the digital value video_data. The bias unit 50 supplies a reference voltage to each of the integration unit 20, the output selection unit 33, and the AD conversion unit 40. Based on the CLK signal and the ST signal input from the outside, the control unit 63 receives the light receiving unit 13, the integrating unit 20, the first holding unit 24, the second holding unit 25, the output selecting unit 33, and the AD converting unit 40, respectively. It generates and outputs a control signal for controlling the operation, and includes a logic circuit such as a shift register.

FIG. 14 is a configuration diagram of the light receiving unit 13, the integrating unit 20, the first hold unit 24, and the second hold unit 25 included in the solid-state imaging device 3 according to the third embodiment. In the light receiving unit 13, M × N pixel units P _{1,1 to} P _{M, N} having a common configuration are two-dimensionally arranged, and the pixel unit P _{m, n} is positioned in the _m- th row and the n-th column. is doing. The integrating unit 20 includes N integrating circuits I _{1 to} I _N having a common configuration. The first hold unit 24 includes N hold circuits H _{1,1 to} H _{1, N.} The second holding portion 25 includes N holding circuits _{H 2,1} to H _{2, N.} The N hold circuits H _{1,1 to} H _{1, N} and the N hold circuits H _{2,1 to} H _{2, N} have a common configuration.

The n M pixel units P ₁ of the _{column, n} to P _{M, n} respective output terminals included in the light receiving unit 13, and an input terminal of the integrating circuit I _n included in the integrating portion 20, a common wiring Vline Connected by (n). The output terminal of the integrating circuit I _n included in the integrating portion 20, the hold circuit H _{1, n} input terminals included in the first holding portion 24, and, of the hold circuit H _{2, n} included in the second holding portion 25 The input ends are connected by a common wiring. The output terminals of the _N hold circuits H _{1,1 to} H _{1, N} included in the first hold unit 24 are connected by a common wiring. The output terminals of the _N hold circuits H _{2, 1 to} H _{2, N} included in the second hold unit 25 are connected by a common wiring.

FIG. 15 is a circuit diagram of a pixel unit P _{m, n} , an integration circuit I _n , a hold circuit H _{1, n} and a hold circuit H _{2, n} included in the solid-state imaging device 3 according to the third embodiment. Each PPS pixel portion P _{m, n} includes a photodiode PD and a switch SW. The anode terminal of the photodiode PD is grounded, and the cathode terminal of the photodiode PD is connected to the wiring Vline (n) via the switch SW. This switch SW opens and closes according to the level of the Vaddress (m) signal supplied from the control unit 63, and when it is closed, the switch SW transfers the charge accumulated in the junction capacitance part of the photodiode PD to the wiring Vline (n). ).

Each integrating circuit I _n included in the integrating portion 20, parallel amplifier A, the capacitor C and the switch SW is provided between and its input and output terminals. Input terminals of the integrating circuit I _n is connected to the wiring Vline (n), inputs one line of the pixel section P _{m charges is} output from the _n. The switch SW opens and closes according to the level of the Reset1 signal supplied from the control unit 63. Integrating circuit I _n, when the switch SW is closed, and discharging the capacitive element C, and initializes the voltage value outputted from the output terminal. On the other hand, the integrating circuit I _n, when open switch SW accumulates charges input to the input terminal to the capacitor C, and outputs a voltage value according to the amount of the accumulated charge from the output terminal.

Each hold circuit H1 _{, n} included in the first hold unit 24 includes a capacitive element C and two switches SW1, SW2. In the hold circuit H _{1, n,} the switch SW1 and the switch SW2 is provided between the in series connected to the output terminal of the integrating circuit I _n and the wiring Hline_s1, one end of the capacitor C, the switch SW1 and the switch The other end of the capacitive element C is connected to a connection point between the capacitor SW2 and the SW2. The switch SW1 opens and closes according to the level of the set_s1 signal supplied from the control unit 63. The set_s1 signal is input in common to _{the N} hold circuits H _{1,1 to} H _{1, N} included in the first hold unit 24. The switch SW2 opens and closes according to the level of the hshiht (n) signal supplied from the control unit 63. voltage value set_s1 signal has been output from the integrating circuit I _n when switches from high level to low level is, thereafter, is held as a voltage value out_s1 (n) by the capacitance element C. When the hshiht (n) signal becomes high level, the voltage value out_s1 (n) held by the capacitor C is output to the wiring Hline_s1. This voltage value out_s1 (n) represents a voltage value V1 _{m, n} corresponding to the amount of charge generated in the photodiode PD of the pixel portion P _{m, n} .

Each hold circuit H2 _{, n} included in the second hold unit 25 includes a capacitive element C and two switches SW1, SW2. In the hold circuit H _{2, n,} the switch SW1 and the switch SW2 is provided between the in series connected to the output terminal of the integrating circuit I _n and the wiring Hline_s2, one end of the capacitor C, the switch SW1 and the switch The other end of the capacitive element C is connected to a connection point between the capacitor SW2 and the SW2. The switch SW1 opens and closes according to the level of the set_s2 signal supplied from the control unit 63. The set_s2 signal is input in common to _{the N} hold circuits H _{2,1 to} H _{2, N} included in the second hold unit 25. The switch SW2 opens and closes according to the level of the hshiht (n) signal supplied from the control unit 63. voltage value set_s2 signal has been output from the integrating circuit I _n when switches from high level to low level is, thereafter, is held as a voltage value out_s2 (n) by the capacitance element C. When the hshiht (n) signal becomes high level, the voltage value out_s2 (n) held by the capacitor C is output to the wiring Hline_s2. This voltage value out_s2 (n) represents a voltage value V2m _{, n} corresponding to the amount of charge generated in the photodiode PD of the pixel portion Pm _{, n} .

  FIG. 16 is a configuration diagram of the output selection unit 33 included in the solid-state imaging device 3 according to the third embodiment. The output selection unit 33 includes an integration circuit 331, an integration circuit 332, a comparison circuit 333, a latch circuit 334, a logic inversion circuit 335, a switch SW30, and a switch SW40.

Each integrating circuit 331 and the integrating circuit 332 has the same circuit configuration as the integrating circuit I _n in FIG. The input terminal of the integration circuit 331 is connected to the wiring Hline_s1, and receives the voltage value out_s1 (n) output from the hold circuit H1 _{, n} to the wiring Hline_s1, and outputs the voltage value V1 _{m, n} . The input terminal of the integration circuit 332 is connected to the wiring Hline_s2, and receives the voltage value out_s2 (n) output from the hold circuit H2 _{, n} to the wiring Hline_s2, and outputs the voltage value V2m _{, n} .

The comparison circuit 333 compares the voltage value V1 _{m, n} output from the integration circuit 331 with the reference voltage value Vsat, and outputs a mode_out signal indicating the comparison result. The latch circuit 334 receives the mode_out signal output from the comparison circuit 333, holds the mode_out signal for a certain period, and outputs it. The logic inversion circuit 335 receives the mode_out signal output from the latch circuit 334, inverts the logic, and outputs the inverted signal.

One end of the switch SW30 is connected to the output terminal of the integrating circuit 331, and opens and closes based on the mode_out signal output from the latch circuit 334. One end of the switch SW40 is connected to the output terminal of the integrating circuit 332, and opens and closes based on a signal (an inverted signal of the mode_out signal) output from the logic inverting circuit 335. When one of the switch SW30 and the switch SW40 is open, the other is closed, the other end of the switch SW30 and the other end of the switch SW40 are connected to each other, and the video_a signal output from the connection point is The voltage value V1 _{m, n is one} of the voltage value V2 _{m, n} .

Therefore, Video_a signal outputted from the output selection unit 33, the voltage value V1 _{m, n} becomes when the voltage value V1 _{m, n} is less than the reference voltage value Vsat, a voltage value V2 _{m, n} otherwise. Here, the reference voltage value Vsat is set to an appropriate value so that the comparison circuit 333 can determine whether or not the voltage value V1 _{m, n} is saturated. The AD conversion unit 40 receives the video_a signal output from the output selection unit 33, converts the voltage value (analog value) of this signal into a digital value, and outputs the digital value video_data.

  Next, the operation of the solid-state imaging device 3 according to the third embodiment will be described. The timing chart for explaining the operation of the solid-state imaging device 3 according to the third embodiment is the same as the timing chart shown in FIG.

  In the light receiving unit 13, the N pixel units in each row operate at the same timing, but operate at different timings for each fixed time between rows. Then, the following operation is sequentially performed for each of the first to Mth rows in the light receiving unit 13.

The photodiode of each pixel unit P _{m, n in} the m-th row has a charge accumulation operation corresponding to light incidence over the first period T1, an initialization operation after the first period T1, and light incidence over the second period T2. The charge accumulation operation according to the above and the initialization operation after the second period T2 are repeated. However, the second period T2 is shorter than the first period T1.

Each pixel portion P _m of the m-th row in response to light incident over a first period _T1, the charge generated in the _n photodiode is input to the integrating circuit I _n via the wiring Vline (n), to the amount of charge depending voltage value is output from the integrating circuit I _n. Voltage value output from the integrating circuit I _n is input to the first holding portion 24 is held by the hold circuit H _{1, n} of the voltage value _{V1 m, n (out_s1 (n} )) as a first holding portion 24 The After the first period T1, each pixel unit P _{m, n} in the m-th row is initialized.
After this initialization, the charges generated in the photodiodes of the pixel portions P _{m, n in} the _m-th row in response to light incidence over the second period T2 shorter than the first period T1 are integrated via the wiring Vline (n). is input to the circuit I _n, the voltage value corresponding to the electric charge amount is output from the integrating circuit I _n. Voltage value output from the integrating circuit I _n is input to the second hold portion 25 is held by the hold circuit H _{2, n} of the voltage value V2 _{m, n} as (out_s2 (n)) second holding portion 25 The After the second period T2, each pixel unit P _{m, n} in the m-th row is initialized.
The voltage value V1 _{m, n} held by the first hold unit 24 is input to the output selection unit 33 via the wiring Hline_s1. The voltage value V2 _{m, n} held by the second hold unit 25 is input to the output selection unit 33 via the wiring Hline_s2. First, the voltage value V1 _{m, 1} and the voltage value V2 _{m, 1} are input to the output selection unit 33, then the voltage value V1 _{m, 2} and the voltage value V2 _{m, 2} are input, and then the voltage value V1. _{m, 3} and the voltage value V2 _{m, 3} is entered, so that ..., n-th voltage value in order to train the first column _{V1 m, n, V2 m,} n are input. The voltage value V1 _{m, n} or the voltage value V2 _{m, n} is selectively output from the output selection unit 33.

The value of the video_a signal output from the output selection unit 33 is the voltage value V1 _{m, n} when the voltage value V1 _{m, n} is less than the reference voltage value Vsat (that is, when the voltage value V1 _{m, n} is not saturated) _{. n} , otherwise the voltage value V2 _{m, n} . As described above, the voltage value V1 _{m, n} is a voltage value corresponding to the amount of charge generated in the photodiode of the pixel unit P _{m, n} in response to light incidence over a relatively long first period T1, The voltage value V2 _{m, n} is a voltage value corresponding to the amount of charge generated in the photodiode of the pixel unit P _{m, n} in response to light incidence over a relatively short second period T2.

When the light incident intensity is relatively small, the voltage value V1 _{m, n} is not saturated even if the charge accumulation time is relatively long, so this voltage value V1 _{m, n} is selected. When the light incident intensity is relatively high, the voltage value V1 _{m, n} is saturated, so the voltage value V2 _{m, n} is selected. Therefore, in the solid-state imaging device 3, the dynamic range is expanded for each of the plurality of pixel units. Further, the solid-state imaging device 3 does not require a frame memory and only a small circuit is added, so that it can be reduced in size and can be inexpensive.

  Further, in the solid-state imaging device 3, the charge is accumulated over a relatively long first period T1, and then the charge is accumulated over a relatively short second period T2. The difference in the voltage value holding timing of each unit 25 is small. Further, after that, the time for which the first hold unit 24 and the second hold unit 25 hold the voltage values is short until the processing by the output selection unit 33 is completed. Therefore, the scale of the additional circuit can be reduced also in this respect.

(Modification)
The solid-state imaging device 1 according to the first embodiment is of an APS method including two hold units, and the solid-state imaging device 2 according to the second embodiment is of an APS method including three hold units, The solid-state imaging device 3 according to the third embodiment is of a PPS system including two hold units. The solid-state imaging device according to the present invention may be of a PPS system including three hold units.

1 is a schematic configuration diagram of a solid-state imaging device 1 according to a first embodiment. 2 is a configuration diagram of a light receiving unit 11, a first hold unit 21, and a second hold unit 22 included in the solid-state imaging device 1 according to the first embodiment. FIG. ₂ is a circuit diagram of a pixel unit P _{m, n} , a hold circuit H _{1, n} and a hold circuit H _{2, n} included in the solid-state imaging device 1 according to the first embodiment. FIG. It is a block diagram of the output selection part 31 contained in the solid-state imaging device 1 which concerns on 1st Embodiment. 4 is a circuit diagram of difference calculation circuits 311 and 312 included in an output selection unit 31. FIG. It is a timing chart explaining the level change of each signal in the solid-state imaging device 1 which concerns on 1st Embodiment. 3 is a timing chart for explaining the operation of the solid-state imaging device 1 according to the first embodiment. It is a schematic block diagram of the solid-state imaging device 2 which concerns on 2nd Embodiment. It is a block diagram of the light-receiving part 11, the 1st hold part 21, the 2nd hold part 22, and the 3rd hold part 23 which are included in the solid-state imaging device 2 which concerns on 2nd Embodiment. It is a circuit diagram of pixel part _{Pm, n} , hold circuit H1 _{, n} , hold circuit H2 _{, n,} and hold circuit H3 _{, n} included in the solid-state imaging device 2 according to the second embodiment. It is a block diagram of the output selection part 32 contained in the solid-state imaging device 2 which concerns on 2nd Embodiment. It is a timing chart explaining operation of solid imaging device 2 concerning a 2nd embodiment. It is a schematic block diagram of the solid-state imaging device 3 which concerns on 3rd Embodiment. It is a block diagram of the light-receiving part 13, the integration part 20, the 1st hold part 24, and the 2nd hold part 25 which are included in the solid-state imaging device 3 which concerns on 3rd Embodiment. Pixel unit P _m included in the solid-state imaging device 3 according to the third _{embodiment, n,} is a circuit diagram of the integrating circuit I _n, hold circuit H _{1, n} and hold circuit H _{2, n.} It is a block diagram of the output selection part 33 contained in the solid-state imaging device 3 which concerns on 3rd Embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1-3 ... Solid-state imaging device 11, 13 ... Light-receiving part, 20 ... Integration part, 21 ... 1st hold part, 22 ... 2nd hold part, 23 ... 3rd hold part, 24 ... 1st hold part, 25 ... 2nd hold part, 31-33 ... output selection part, 40 ... AD conversion part, 50 ... bias part, 61-63 ... control part.

Claims (2)

A light-receiving unit including pixel units P _{1,1 to} P _{M, N} each having two-dimensionally arranged in M rows and N columns, each having a photodiode that generates an amount of charge corresponding to the amount of incident light;
N pixel portions P _m of the m-th row of one of the light receiving _{unit, 1} to P _m, the voltage value a voltage value corresponding to the amount of charges generated in the _N respective photodiodes V1 _{m, 1} ~V1 m _{, N} to hold and output, and
N pixel portions P _m of one of the m-th row in the light receiving _{unit, 1} to P _m, the voltage value a voltage value corresponding to the amount of charges generated in the _N respective photodiodes V2 _{m, 1} to V2 _{m , N} , and a second hold unit for outputting as _N
N pixel portions P _m of the m-th row of one of the light receiving _{unit, 1} to P _m, the voltage value a voltage value corresponding to the amount of charges generated in the _N respective photodiodes V3 _{m, 1} to V3 _{m , N} , and a third hold unit that outputs as _N
N voltage values V1 _{m, 1 to} V1 _{m, N} or N voltage values V2 _{m, 1 to} V2 _m, N output from the first hold unit or the second hold unit _, and the third hold n voltage value output from the section V3 _m, 1 to V3 _m, inputs the _n, the voltage value V1 _{m, n} or voltage value V2 _m, and _n and the reference voltage value Vsat and compares its A signal indicating the comparison result is output, and when the voltage value V1 _{m, n} or the voltage value V2 _{m, n} is less than the reference voltage value Vsat, the voltage value V1 _{m, n} or the voltage value V2 _{m, n} is selectively output. Otherwise, an output selection unit that selectively outputs the voltage value V3 _{m, n} ;
A control unit that controls operations of the light receiving unit, the first hold unit, the second hold unit, the third hold unit, and the output selection unit;
With
The control unit sequentially for each of the first to Mth rows in the light receiving unit,
Each pixel portion P _m of the m-th row in response to light incident over a first _period, a voltage value corresponding to the amount of charges generated in the _n photodiode, the voltage value when m value is an odd number V1 _m, as _n Held by the first hold unit, and when the m value is an even number, the voltage value V2 _{m, n} is held by the second hold unit,
After this first period, each pixel unit P _{m, n} in the m-th row is initialized,
After this initialization, a voltage value corresponding to the amount of electric charge generated in the photodiode of each pixel unit P _{m, n in} the _m-th row in response to light incidence over a second period shorter than the first period is a voltage value V3. _{m, n} are held by the third hold unit,
When the m value is an odd number, the voltage value V1 _{m, n} held by the first hold unit and the voltage value V3 _{m, n} held by the third hold unit are input to the output selection unit, and the voltage value V1 _{m, n} or voltage value V3 _{m, n} is selectively output from the output selection unit. When the m value is an even number, the voltage value V2 _{m, n} held by the second hold unit and the third hold The voltage value V3 _{m, n} held by the unit is input to the output selection unit, and the voltage value V2 _{m, n} or the voltage value V3 _{m, n} is selectively output from the output selection unit,
(M and N are integers greater than or equal to 2, m is an arbitrary integer between 1 and M, and n is an arbitrary integer between 1 and N). The light receiving portion, said first holding portion, the second holding portion, the third holding section and the output selection portion is formed monolithically on a common substrate, according to claim 1, wherein the Solid-state imaging device.

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