JP4710304B2 - Data transfer control device - Google Patents

Description

  The present invention relates to a data transfer control device, and in particular, a data transfer control device that performs control related to data transfer between a processor and additional hardware, a computer system using the same, a processing method therefor, and the method in a computer. It relates to the program to be executed.

  In recent years, an increasing number of computer systems provide higher functions by adding dedicated hardware to processors having general functions. An example of such dedicated hardware is a graphic accelerator provided exclusively for graphic processing. The graphic accelerator receives image data on the main memory from the processor, performs predetermined processing, and draws on the display unit.

  Although a large amount of data may be transferred between such additional hardware and the processor, the data transfer speed is not sufficient compared to the arithmetic processing speed of a processor that has recently been remarkably increased in speed.

In contrast, when data for drawing a window of a workstation or personal computer (hereinafter referred to as window information) is transferred to the graphic accelerator, if the amount of data is large, the window information itself is transferred to the graphic accelerator one by one. Instead of transferring, a transfer method has been proposed in which the address in the processor is notified and the window information is transferred by DMA (Direct Memory Access) (see, for example, Patent Document 1).
JP-A-10-187125 (FIG. 1)

  However, in the above-described prior art, when a certain process is sequentially performed on a plurality of sets of data, the sets are transferred one by one from the main memory on the processor side to a dedicated memory of additional hardware. At this time, when the data overlap each other, the overlapped portion is transferred in duplicate, so that the same data may be wasted a plurality of times.

  Therefore, when transferring a plurality of sets of data from the processor to the additional hardware, if the data overlap each other, the present invention transfers the area including the data in a lump to efficiently transfer the data. The purpose is to realize the transfer.

  The present invention has been made to solve the above-mentioned problems, and a first aspect thereof performs transfer control when transferring element data having a predetermined structure from the first memory to the second memory. A data transfer control device comprising: a comprehensive area calculating means for calculating a comprehensive area including at least one of the element data in the first memory; and the entire comprehensive area from the first memory to the second A data transfer control device comprising: batch transfer control means for transferring data to the memory. As a result, the entire inclusion area including at least one element data having a predetermined structure is collectively transferred. In other words, even when element data overlap each other, efficient data transfer is performed without duplication, and data transfer by burst transfer and original processing other than data transfer are performed in parallel. Bring.

  The second aspect of the present invention is a data transfer control device that performs transfer control when transferring element data having a rectangular structure in a predetermined two-dimensional area from the first memory to the second memory, A comprehensive area calculating means for calculating a comprehensive area including at least two element data in the first memory; and batch transfer control for transferring the entire comprehensive area from the first memory to the second memory in a lump. And a data transfer control device. This brings about the effect that the entire inclusion area including at least two element data having a rectangular structure is collectively transferred.

  In the second aspect, the comprehensive area calculation means compares the coordinates of the element data in the predetermined direction in the two-dimensional area to obtain the maximum value and the minimum value of the coordinates in the element data. A comprehensive area can be calculated.

  The third aspect of the present invention is a data transfer control device that performs transfer control when transferring element data having a rectangular structure in a predetermined two-dimensional area from the first memory to the second memory, A comprehensive area calculating means for calculating a comprehensive area including at least two element data in the first memory; a transfer method specifying means for specifying whether the entire comprehensive area should be transferred in a batch or sequentially; Based on the transfer method defining means, transfer method determining means for determining whether to transfer the entire inclusion area at once or sequentially, and transferring the element data from the first memory by the transfer method A data transfer control device comprising batch transfer control means for transferring data to the second memory. As a result, when transferring element data having a rectangular structure, it is determined whether the element data should be transferred sequentially or the entire inclusion area including the element data should be transferred at once, and the transfer can be performed by an optimal transfer method. Bring.

  Further, in the third aspect, the transfer method defining means can be realized by a transfer method defining table that holds values each positioned by a predetermined index corresponding to the number of element data included in the inclusion area. . At that time, the value held there can define whether the entire inclusion area should be transferred in a batch or sequentially. The index may depend on the size of the inclusion area.

  Further, in the third aspect, when the entire inclusion area is transferred in a lump, transfer destination address generation means for generating an address in the second memory of each of the element data is further provided. Also good. This brings about the effect | action of performing appropriately the process of the element data transferred to the 2nd memory.

  The fourth aspect of the present invention is instructed by a first processing means for performing a predetermined process, a first memory for holding a work area by the first processing means, and the first processing means. A data transfer system comprising: a second processing unit that performs the above-described processing; and a second memory that holds a work area by the second processing unit, wherein the second processing unit includes the first processing unit A comprehensive area calculating means for calculating a comprehensive area including at least two element data having a rectangular structure in a predetermined two-dimensional area in the memory; and the entire comprehensive area is collectively transferred from the first memory to the second memory. A data transfer system comprising batch transfer control means for transferring data. This brings about the effect that the entire inclusion area including at least two element data having a rectangular structure is transferred from the first memory to the second memory in a lump.

  The fifth aspect of the present invention provides a processor that performs a predetermined process, a main memory that holds a work area by the processor, a graphic accelerator that performs a process instructed by the processor, and a work area by the graphic accelerator. And a local memory that holds a local memory, wherein the graphic accelerator calculates a comprehensive area including at least two image data having a rectangular structure in a predetermined image area in the main memory And a collective transfer control means for collectively transferring the entire inclusion area from the main memory to the local memory. As a result, the entire inclusion area including at least two pieces of image data having a rectangular structure is collectively transferred from the main memory on the processor side to the local memory on the graphic accelerator side.

  According to a sixth aspect of the present invention, there is provided a data transfer control method for transferring element data having a rectangular structure in a predetermined two-dimensional area from a first memory to a second memory. A procedure for calculating a comprehensive area including at least two of the element data in the memory; a procedure for determining whether to transfer the entire comprehensive area in a batch or sequentially according to the size of the comprehensive area; A data transfer control method comprising: transferring the element data from the first memory to the second memory by the transfer method. As a result, the element data having the rectangular structure is transferred by the optimum transfer method.

  According to a seventh aspect of the present invention, there is provided a procedure for calculating a comprehensive area including at least two element data having a rectangular structure in a predetermined two-dimensional area in the first memory, and transferring the entire comprehensive area in a lump. The computer executes a procedure for determining whether to transfer according to the size of the comprehensive area and a procedure for transferring the element data from the first memory to the second memory by the transfer method. It is a program characterized by making it carry out. As a result, the element data having the rectangular structure is transferred by the optimum transfer method.

  According to the present invention, when a plurality of sets of data are transferred from the processor to the additional hardware, if the data overlap each other, efficient data can be transferred by transferring the area including the data all at once. An excellent effect of realizing the transfer can be achieved.

  Next, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a diagram illustrating an example of a computer system 100 that realizes a data transfer control device according to an embodiment of the present invention. The computer system 100 includes a processor 110, a main memory 120 thereof, and a graphic accelerator 130 as additional hardware.

  The graphic accelerator 130 includes a computing unit 140 that performs computation for graphic processing, a local memory 150 that stores image data, and a control unit 160 that controls these. The graphic accelerator 130 is configured such that the computing unit group 140 processes the image data held in the local memory 150. Therefore, when processing the image data held in the main memory 120, it is necessary to transfer the data from the main memory 120 to the local memory 150 once.

  When processing the graphic accelerator 130, the processor 110 first transfers image data from the main memory 120 to the local memory 150. Thereafter, the processor 110 converts the image data in the local memory 150 to a predetermined value. Instruct to perform the process. The control unit 160 controls the flow of image data in the series of processes.

  FIG. 2 is a diagram illustrating an internal configuration example of the control unit 160 in the embodiment of the present invention. The control unit 160 includes a batch transfer control block 170, a batch transfer processing unit 180, an internal register 190, and a batch transfer control register 400.

  The batch transfer control block 170 serves as an interface with the processor 110 side, and controls DMA transfer between the main memory 120 and the local memory 150 as necessary. At this time, the batch transfer control register 400 is used when exchanging necessary control information with the processor 110. Details of the batch transfer control register 400 will be described later.

  The batch transfer processing unit 180 performs processing necessary for batch transfer, and includes a comprehensive area calculation unit 181, a transfer method determination unit 182, and a transfer destination address generation unit 183. The comprehensive region calculation unit 181 calculates a region that includes a plurality of sets of image data (hereinafter referred to as a comprehensive region). The transfer method determination unit 182 determines a transfer method as to whether image data in the comprehensive area should be transferred at once or sequentially. The transfer destination address generation unit 183 generates a transfer destination address in the local memory 150 for each piece of image data transferred in a batch.

  The processing of each unit in the batch transfer processing unit 180 is performed using the internal register 190. Further, the comprehensive area calculation unit 181 calculates a comprehensive area using the batch transfer information 500 (FIG. 6) held in the main memory 120 and generates transfer method determination information 610 in the local memory 150. The transfer method determination unit 182 uses the transfer method determination information 610 and the transfer method definition table 620 in the local memory 150 to determine the transfer method. Further, the transfer destination address generation unit 183 writes the generated transfer destination address of the local memory 150 in the batch transfer information 500 (FIG. 6) in the main memory 120.

  FIG. 3 is a diagram showing an example of a memory map viewed from the processor 110 according to the embodiment of the present invention. In addition to image data, the main memory 120 holds batch transfer information 500 for exchanging information regarding batch transfer between the processor 110 and the graphic accelerator 130. The start address of the batch transfer information 500 is held in an information start address register 420 described later as an information start address.

  A batch transfer control register 400 is allocated as a batch transfer control interface to a predetermined region on the memory map (for example, a region starting from 0xffff0000). The batch transfer control register 400 may include four registers: an instruction register 410, an information start address register 420, a status register 430, and a transfer size register 440.

  For example, an interface with a peripheral device can be assigned to another area on the memory map as another interface.

  FIG. 4 is a diagram showing a configuration example of the batch transfer control register 400 in the embodiment of the present invention. Each register included in the batch transfer control register 400 may be configured as a 32-bit width register, for example.

  FIG. 4A is a diagram illustrating a configuration example of the instruction register 410. The instruction register 410 includes fields for a transfer start instruction 411, an end report mode 412, and a maximum burst length 413. The transfer start instruction 411 is a field for transmitting a data transfer start instruction from the processor 110 to the graphic accelerator 130. For example, when the processor 110 sets the least significant 1 bit out of 6 bits to "1" Then, the data transfer process in the graphic accelerator 130 starts.

  The end report mode 412 is a field that defines a report method from the graphic accelerator 130 to the processor 110 when the data transfer ends. For example, if the least significant bit of 10 bits is “1”, the polling mode is set, and the processor 110 detects the end of the transfer by checking the status register 430. On the other hand, for example, if the least significant 1 bit among the 10 bits is “0”, it is an interrupt mode, and an interrupt signal to the processor 110 is generated at the end of transfer.

  The maximum burst length 413 is a field indicating the number of data that can be input / output continuously. For example, a definition in units of words is performed by a 16-bit value. The maximum burst length 413 is a value depending on the system, and is used to determine whether or not the data amount limit is exceeded when starting batch transfer.

  FIG. 4B is a diagram illustrating a configuration example of the information start address register 420. The information start address register 420 holds an information start address 421. This information start address 421 indicates the start address of the batch transfer information 500 in the main memory 120. This information start address 421 is set by the processor 110.

  FIG. 4C is a diagram illustrating a configuration example of the status register 430. The status register 430 includes fields for a transfer mode 431 and a transfer status 432. The transfer mode 431 is a field indicating whether the transfer method of the data transfer performed immediately before was batch transfer or sequential transfer. For example, if the least significant bit of 16 bits is “1”, it means batch transfer, and if it is “0”, it means sequential transfer. Since the processing contents in the processor 110 change depending on this transfer method, the result is used to provide the processor 110 with the result.

  The transfer state 432 is a field indicating whether or not data transfer is being executed. For example, if the least significant bit of 16 bits is “1”, it can indicate that the transfer is in progress, and if it is “0”, it indicates that the transfer is not in progress. The transfer state 432 is read by the processor 110 for determining the transfer end when the end report mode 412 is the polling mode.

  FIG. 4D is a diagram illustrating a configuration example of the transfer size register 440. The transfer size register 440 includes fields of a maximum horizontal width 441, a maximum vertical width 442, a transfer horizontal width 443, and a transfer vertical width 444. The maximum horizontal width 441 and the maximum vertical width 442 are fields indicating the maximum sizes of the horizontal width and the vertical width when batch transfer is performed. For example, the maximum size is indicated in units of bytes by a field of 8 bytes width. These maximum horizontal width 441 and maximum vertical width 442 are system-dependent values, and define the size of the transfer method definition table 620 (FIG. 9).

  The transfer horizontal width 443 and the transfer vertical width 444 are fields indicating the sizes of the horizontal width and the vertical width of the transfer that is actually performed. That is, the transfer horizontal width 443 and the transfer vertical width 444 indicate the sizes of the image data.

  FIG. 5 is a diagram showing an arrangement example of image data in the embodiment of the present invention. FIG. 5A shows an arrangement example of image data in the image area. Here, a two-dimensional area of k × l bytes having a width of k bytes and a height of 1 byte is assumed as the image area. The horizontal width k and vertical width l of this image area are included in the batch transfer information 500.

  In this image area, the image data is assumed to be rectangular structure data that occupies a two-dimensional area of m × n bytes having a width of m bytes and a height of n bytes. Data having such a structure is called element data. The horizontal width m and vertical width n of the element data are included in the batch transfer information 500. In the figure, the coordinates of the start position of the upper left image area are represented as (0, 0), and the coordinates of the start position of element data are represented as position information (i, j). The position information of each element data is included in the batch transfer information 500.

  FIG. 5B is an example of image data arrangement in the main memory 120. In the main memory 120, the image area is secured in an area of k × 1 bytes from a predetermined head address. The start address of this image area is included in the batch transfer information 500.

In the main memory 120, the element data is arranged with n pieces of continuous data of m bytes at a pitch of k bytes. Therefore, the address in the main memory 120 of the position information (i, j) corresponding to the head of the element data is
Address of position information (i, j) = start address of image area + k × j + i
Is represented by

  Here, although an example of arrangement of element data in the main memory 120 is shown in FIG. 5B, the element data is also held in the local memory 150 in the same arrangement.

  FIG. 6 is a diagram showing the contents of the batch transfer information 500 in the embodiment of the present invention. The batch transfer information 500 holds information necessary for calculating a comprehensive area for batch transfer and a calculation result thereof, and includes basic information 510, element data position information 520, element data transfer destination address. 530.

  The basic information 510 is basic information for calculating a comprehensive area, and includes an image area start address 511, a transfer destination start address 512, a maximum load size 513, an image area horizontal width 514, and an image area vertical width 515. Element data number 516, element data horizontal width 517, and element data vertical width 518. The image area start address 511 indicates the start address of the image area in the main memory 120 that is the transfer source (see FIG. 5B). The transfer destination start address 512 indicates the start address of the image area in the local memory 150 that is the transfer destination. The maximum load size 513 indicates the maximum size at which data can be transferred, and is used for a capacity check at the start of transfer.

  An image area horizontal width 514 and an image area vertical width 515 indicate the horizontal width and vertical width (see FIG. 5A) of the image area, respectively. The element data number 516 indicates the number of element data in the image area. The element data horizontal width 517 and the element data vertical width 518 respectively indicate the horizontal width and vertical width (see FIG. 5A) of each element data.

  Element data position information 520 indicates position information of each element data. Here, assuming that the number defined in the element data number 516 is N, the position information DB [0] to DB [N−1] is defined for each of the N element data. Each piece of position information is represented by an x coordinate 521 and a y coordinate 522 corresponding to the coordinates (x, y).

  Element data transfer destination address 530 indicates element data transfer destination addresses [0] to [N−1] for each of N element data. The basic information 510 and the element data position information 520 are information provided from the processor 110 to the graphic accelerator 130, whereas the element data transfer destination address 530 is a return value from the graphic accelerator 130 to the processor 110. Different. That is, the graphic accelerator 130 reports the transfer destination address of each element data to the processor 110 using this field (element data transfer destination address 530) as a result of the data transfer.

  Depending on the specifications of the graphic accelerator, when the data arrangement in the local memory 150 changes, the control for processing the data often changes. This element data transfer destination address 530 is required when the processor 110 is involved in this control.

  FIG. 7 is a diagram illustrating a method for calculating the comprehensive area of each element data by the comprehensive area calculating unit 181 according to the embodiment of the present invention. Here, it is assumed that a plurality of m × n bytes of element data exist in a k × l byte image area. The comprehensive area including the whole of the plurality of overlapping element data is obtained by the following procedure.

That is, the minimum value and the maximum value of the x coordinate and the y coordinate are obtained by comparing the position information of each element data. Thereby, the minimum value x _min and the maximum value x _max of the x coordinate, and the minimum value y _min and the maximum value y _{max of} the y coordinate are obtained. As a result, the coordinates of the four points surrounding the inclusive region are P ₀ (x _min , y _min ), P ₁ (x _max + m, y _min ), P ₂ (x _min , y _max + n), and P ₃ ( x _max + m, y _max + n).

At this time, the horizontal width x _range and the vertical width y _range of the inclusion area are
x _range = x _max -x _min + m
y _range = y _max -y _min + n
It is calculated by.

Also, using these results, the element data transfer destination address 530 of the position information (x, y) described above is obtained by the following equation.
Transfer destination address = transfer destination start address + x _range × (y− _{min min} ) + (xx _{min min} )

  FIG. 8 is a diagram showing the contents of the transfer method determination information 610 generated by the comprehensive area calculation unit 181 according to the embodiment of the present invention. This transfer method determination information 610 includes a transfer method definition table index 611, element data horizontal width 612, element data vertical width 613, and element data count 614.

  The transfer method definition table index 611 indicates an index in the transfer method definition table 620. The transfer method definition table 620 is a table held in the local memory 150, and can determine whether to perform sequential transfer or batch transfer based on the value at a predetermined position in the table.

  The element data horizontal width 612 and the element data vertical width 613 indicate the horizontal width m and the vertical width n of the element data, and the element data horizontal width 517 and the element data vertical width 518 in the batch transfer information 500 are used. The element data number 614 indicates the number N of element data, and the element data number 516 in the batch transfer information 500 is used.

  FIG. 9 is a diagram showing a configuration of the transfer method definition table 620 according to the embodiment of the present invention. The transfer method definition table 620 is a table held in the local memory 150 as described above, and can determine whether to perform sequential transfer or batch transfer based on a value at a predetermined position in this table. For example, a value of “0” or “1” is held at each position.

  The size of the transfer method definition table 620 is defined by the maximum size of the horizontal width and the vertical width when performing batch transfer. As the maximum size, the maximum horizontal width 441 and the maximum vertical width 442 of the transfer size register 440 can be used. That is, depending on which value is selected at the position selected within the range of the maximum horizontal width 441 and the range of the maximum vertical width 442, for example, “0” indicates that sequential transfer should be performed, and “1” indicates If there is, it shall indicate that batch transfer should be performed. This transfer method definition table 620 exists corresponding to the number of element data included in the comprehensive area, and corresponds to the number of element data included in the comprehensive area when determining whether or not to perform batch transfer. The transfer method definition table 620 is referred to.

Which position should be referred to in the transfer method definition table 620 is indicated in the transfer method definition table index 611 in the transfer method determination information 610. The comprehensive area calculation unit 181 generates the transfer method definition table index 611 by the following equation. Here, M _max represents the maximum horizontal width 441, x _range represents the width in the horizontal direction of the inclusion region, and y _range represents the width in the vertical direction of the inclusion region.
Index = M _max x y _range + x _range

  This transfer method definition table 620 needs to be set in the local memory 150 in advance. As guidelines for this setting, for example, the following items can be considered. (A) Difference in transfer time between batch transfer and sequential transfer, (b) Difference in processing time due to difference in arrangement in local memory 150, (c) Accelerator due to difference in arrangement in local memory 150 For example, (d) the time required to calculate the address in the local memory 150 when batch transfer is performed.

  In (a), the transfer time for sequential transfer is a value obtained by multiplying the time for transferring one element data by the number of element data, and the transfer time for batch transfer is the transfer time for the inclusion area. Examples of the difference in (b) include a change in the number of processing cycles due to a change in addressing in the local memory 150, for example. As the difference in (c), for example, the time required for processing necessary to absorb the difference in addressing in the local memory 150 can be cited. The address calculation of (d) will be described later.

  The difference in processing speed is calculated in advance for all combinations of the number of element data that can be generated and the distribution of possible inclusion areas, and based on the number of element data 614 in the transfer method determination information 610. The corresponding transfer method definition table 620 is selected. In the transfer method definition table 620, the transfer method can be determined by referring to the position indicated by the transfer method definition table index 611 in the transfer method determination information 610.

  Next, the operation of the data transfer control device according to the embodiment of the present invention will be described with reference to the drawings. Here, in describing the operation of the data transfer control device, the configuration of the registers used will be described.

FIG. 10 is a diagram showing the contents of the internal register 190 used in the control unit 160 in the embodiment of the present invention. X_MIN (191) and Y_MIN (192) are registers that hold the minimum values of the x coordinate and the y coordinate in the inclusion area. X_MAX (193) and Y_MAX (194) are registers that hold the maximum values of the x coordinate and the y coordinate in the inclusion area. These correspond to x _min , y _min , x _max , and y _max in FIG. 7, respectively.

X_LOAD_RANGE (195) and Y_LOAD_RANGE (1965) are registers for holding the horizontal and vertical widths of the inclusion area, respectively. These correspond to the x _range and y _range in FIG. 7, respectively.

  FIG. 11 is a flowchart showing an example of the entire procedure of the data transfer control method according to the embodiment of the present invention. When a data transfer request is generated from the processor 110 (step S911), the processing after step S912 is started. Specifically, the graphic accelerator 130 detects the occurrence of a data transfer request when the processor 110 validates a predetermined bit of the transfer start instruction 411 of the instruction register 410.

  In the batch transfer information 500 indicated by the information start address 421 held in the information start address register 420, if the number of element data 516 indicates 2 or more, the process proceeds to step S912 and subsequent steps (step S912). On the other hand, if the number of element data 516 is less than 2, the element data is sequentially transferred (step S952).

  The comprehensive area calculation unit 181 calculates a comprehensive area including the element data included in the batch transfer information 500 (step S920). As a result, predetermined contents are set in the internal register 190, and transfer method determination information 610 is generated. The detailed procedure of this calculation will be described later with reference to FIGS.

Based on the transfer method determination information 610 and the transfer method definition table 620, the transfer method determination unit 182 determines a transfer method as to whether the element data in the comprehensive area should be transferred in a batch or sequentially (step S941). When determining this transfer method, the value of the position indicated by the index 611 in the transfer method definition table is referred to in the transfer method definition table 620. If the size of the comprehensive area (x _range × y _range ) exceeds the maximum load size 513, batch transfer cannot be performed, and sequential transfer is selected.

  If it is determined in step S941 that batch transfer is to be performed, the element data in the comprehensive area is batch transferred by DMA transfer (step S951), and if it is determined that sequential transfer is to be performed, it is comprehensive. Each element data in the area is sequentially transferred (step S952).

  When the batch transfer is performed, the transfer destination address generation unit 183 generates a transfer destination address in the local memory 150 for each of the element data transferred in a batch (step S961). The contents of the generation of the transfer destination address are as described above, and the transfer destination start address 512 in the batch transfer information 500 and the value of the internal register 190 are used. As a result, the transfer destination address is set as the element data transfer destination address 530 in the batch transfer information 500.

  After the data transfer (step S951 or S952) is completed, the transfer method (batch transfer or sequential transfer) of the data transfer is recorded in the transfer mode 431 of the status register 430 (step S971). Further, as the transfer end process, the transfer state 432 of the state register 430 is set to a “not transferring” state, and if the end report mode 412 of the instruction register 410 indicates an interrupt mode, an interrupt to the processor 110 is performed. (Step S972).

  12 and 13 are flowcharts showing an example of the procedure of the comprehensive area calculation process in the embodiment of the present invention. Prior to the calculation of the comprehensive area, the internal register 190 is initialized (step S921). That is, “DB [0] .x” representing the horizontal width of the first element data is set in X_MIN and X_MAX, and “DB [0] .y” representing the vertical width of the first element data is set in X_MIN and Y_MAX, respectively. Further, “1” is set to the index variable i (step S922).

  Then, the maximum value and the minimum value are searched for the x coordinate value and the y coordinate value of the position information of each element data. That is, if the x coordinate value in the index variable i is smaller than the previous minimum value (step S923), the x coordinate value is held in X_MIN as a new minimum value (step S924). If the y coordinate value in the index variable i is smaller than the previous minimum value (step S925), the y coordinate value is held in Y_MIN as a new minimum value (step S926). If the x coordinate value in the index variable i is larger than the maximum value so far (step S927), the x coordinate value is held in X_MAX as a new maximum value (step S928). Furthermore, if the y coordinate value in the index variable i is larger than the maximum value so far (step S929), the y coordinate value is held in Y_MAX as a new maximum value (step S931).

  Thereafter, the index variable i is incremented by 1 (step S932), and if the value has not reached the number N of element data, the process returns to the process after step S923 (step S933), otherwise the process proceeds to the next step S934. .

  When the search for the maximum value and the minimum value for the position information is completed, the horizontal direction and the vertical report width of the comprehensive area are calculated using this (step S934). Also, an index in the transfer method definition table 620 is calculated and stored in the transfer method definition table index 611 in the transfer method determination information 610 (step S935). When the transfer method definition table 620 is accessed, the transfer method definition table index 611 and the number of element data 614 are used.

  FIG. 14 is a diagram showing an overall operation flow of the processor and the graphic accelerator according to the embodiment of the present invention. The processor 110 sets predetermined information in the batch transfer information 500 (step S991), and requests data transfer by enabling a predetermined bit of the transfer start instruction 411 in the instruction register 410 (step S992).

  The graphic accelerator 130 performs a comprehensive area calculation process (step S993) and a transfer method determination process (step S994) using the data transfer request from the processor 110 as a trigger. Based on the results of these processes, a data transfer process from the main memory 120 to the local memory 150 (step S995) is performed. At this time, when batch transfer is performed, transfer destination address generation of each element data in the local memory 150 is performed (step S996).

  While such data transfer is being performed, the processor 110 performs separate processing # 1 to #X (step S997) in parallel with this. The processor 110 detects the end of data transfer by interruption or polling, and performs subsequent data processing (step S998). For example, the processor 110 can issue a command to the graphic accelerator 130 to perform a predetermined operation on the data in the local memory 150.

  As described above, according to the embodiment of the present invention, when the element data in the main memory 120 is transferred to the local memory 150 of the graphic accelerator 130, the comprehensive area calculation unit is based on the batch transfer information 500 set by the processor 110. By calculating the comprehensive area 181 and transferring the entire comprehensive area 181, efficient data transfer can be performed without overlapping even when the element data overlap. This data transfer is independent of the processing in the processor 110 and can be performed in parallel with the processor 110. In addition, the transfer method determination unit 182 determines whether or not the element data should be collectively transferred as a comprehensive area, so that a transfer method that meets the conditions can be selected.

  The embodiment of the present invention is an example for embodying the present invention and has a corresponding relationship with the invention-specific matters in the claims as shown below, but is not limited thereto. However, various modifications can be made without departing from the scope of the present invention.

  The processing procedure described in the embodiment of the present invention may be regarded as a method having a series of these procedures, and a program for causing a computer to execute these series of procedures or a recording medium storing the program May be taken as

  As an application example of the present invention, for example, the present invention can be applied to data transfer control when a large amount of data is transferred between a processor and additional hardware (for example, a graphic accelerator).

It is a figure which shows an example of the computer system 100 which implement | achieves the data transfer control apparatus in embodiment of this invention. It is a figure which shows the internal structural example of the control part 160 in embodiment of this invention. It is a figure which shows an example of the memory map seen from the processor 110 in embodiment of this invention. It is a figure which shows the structural example of the batch transfer control register 400 in embodiment of this invention. It is a figure which shows the example of arrangement | positioning of the element data in embodiment of this invention. It is a figure which shows the content of the batch transfer information 500 in embodiment of this invention. It is a figure which shows the calculation method of the comprehensive area of each element data by the comprehensive area calculation part 181 in embodiment of this invention. It is a figure which shows the content of the transfer method judgment information 610 produced | generated by the comprehensive area | region calculation part 181 in embodiment of this invention. It is a figure which shows the structure of the transfer method prescription | regulation table 620 in embodiment of this invention. It is a figure which shows the content of the internal register 190 used in the control part 160 in embodiment of this invention. It is a flowchart which shows an example of the whole procedure of the data transfer control method in embodiment of this invention. It is a flowchart which shows the first half part of an example of the comprehensive area | region calculation processing procedure in embodiment of this invention. It is a flowchart which shows the second half part of an example of the comprehensive area | region calculation processing procedure in embodiment of this invention. It is a figure which shows the flow of the whole operation | movement of the processor and graphics accelerator in embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Computer system 110 Processor 120 Main memory 130 Graphic accelerator 140 Calculator group 150 Local memory 160 Control part 170 Batch transfer control block 180 Batch transfer process part 181 Comprehensive area calculation part 182 Transfer method judgment part 183 Transfer destination address generation part 190 Internal register 400 Batch transfer control register 410 Instruction register 420 Information start address register 430 Status register 440 Transfer size register 500 Batch transfer information 610 Transfer method determination information 620 Transfer method definition table

Claims (7)

A data transfer control device that performs transfer control when transferring element data having a rectangular structure in a predetermined two-dimensional area from a first memory to a second memory,
A comprehensive area calculating means for calculating a comprehensive area for at least two covering the element data in said first memory,
Transfer method specifying means for specifying whether the entire inclusion area should be transferred in a batch or sequentially; and
Transfer method determination means for determining a transfer method of whether to transfer the entire comprehensive area collectively or sequentially based on the transfer method defining means;
Batch transfer control means for transferring the element data from the first memory to the second memory by the transfer method ;
The transfer method defining means is a transfer method defining table that holds values each positioned by a predetermined index corresponding to the number of element data included in the comprehensive area, and the values collectively collect the entire comprehensive area. That should be transferred sequentially or sequentially.
The data transfer control device , wherein the index depends on the size of the comprehensive area . It said element data of each of said second data transfer control device 請 Motomeko 1, wherein you further comprising a forwarding address generating means for generating an address in the memory when the entire comprehensive areas are transferred collectively. The comprehensive area calculating means, 請 Motomeko you calculate the comprehensive area by comparing the predetermined direction of the coordinates of the element data in the two-dimensional region obtains the maximum and minimum values in the element data of the coordinates 1. Data transfer control device according to 1 First processing means for performing predetermined processing; first memory for holding a work area by the first processing means; second processing means for performing processing instructed by the first processing means; A data transfer system comprising: a second memory for holding a work area by the second processing means;
It said second processing means includes a comprehensive area calculation means for calculating at least two comprehensive comprehensive area element data having a rectangular structure in a predetermined two-dimensional region in the first memory, collectively entire comprehensive area Transfer method prescribing means for prescribing whether to transfer or sequentially transferring, and a transfer method for determining whether to transfer the entire comprehensive area at once or sequentially based on the transfer method prescribing means Determining means; and batch transfer control means for transferring the element data from the first memory to the second memory by the transfer method ;
The transfer method defining means is a transfer method defining table that holds values each positioned by a predetermined index corresponding to the number of element data included in the comprehensive area, and the values collectively collect the entire comprehensive area. That should be transferred sequentially or sequentially.
The index depends on the size of the inclusion area.
Data transfer system. Data transfer comprising a processor that performs a predetermined process, a main memory that holds a work area by the processor, a graphic accelerator that performs a process instructed by the processor, and a local memory that holds a work area by the graphic accelerator A system,
The graphic accelerator includes a comprehensive area calculation unit that calculates a comprehensive area that includes at least two image data having a rectangular structure in a predetermined image area in the main memory, and sequentially determines whether the entire comprehensive area should be transferred collectively. Transfer method defining means for defining whether to transfer, transfer method determining means for determining whether to transfer the entire comprehensive area in a batch or sequentially based on the transfer method defining means, and the transfer Batch transfer control means for transferring the element data from the main memory to the local memory by a method ,
The transfer method defining means is a transfer method defining table that holds values each positioned by a predetermined index corresponding to the number of element data included in the comprehensive area, and the values collectively collect the entire comprehensive area. That should be transferred sequentially or sequentially.
The index depends on the size of the inclusion area.
Data transfer system. A data transfer control method for transferring element data having a rectangular structure in a predetermined two-dimensional region from a first memory to a second memory,
A step of calculating a comprehensive area for at least two covering the element data in said first memory,
Procedure for judgment of the collective of should be forwarded or sequentially be transferred transfer method across the comprehensive area based on the transfer method defining means for defining whether to forward the entire comprehensive areas sequentially should be transferred collectively When,
Transferring the element data from the first memory to the second memory by the transfer method ,
The transfer method defining means is a transfer method defining table that holds values each positioned by a predetermined index corresponding to the number of element data included in the comprehensive area, and the values collectively collect the entire comprehensive area. That should be transferred sequentially or sequentially.
The data transfer control method , wherein the index depends on a size of the comprehensive area . A step of calculating at least two comprehensive comprehensive area element data having a rectangular structure in a predetermined two-dimensional region in the first memory,
Procedure for judgment of the collective of should be forwarded or sequentially be transferred transfer method across the comprehensive area based on the transfer method defining means for defining whether to forward the entire comprehensive areas sequentially should be transferred collectively When,
A program for causing a computer to execute a procedure for transferring the element data from the first memory to the second memory by the transfer method ,
The transfer method defining means is a transfer method defining table that holds values each positioned by a predetermined index corresponding to the number of element data included in the comprehensive area, and the values collectively collect the entire comprehensive area. That should be transferred sequentially or sequentially.
The index is a program that depends on the size of the inclusion area .

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