Deprecated: The each() function is deprecated. This message will be suppressed on further calls in /home/zhenxiangba/zhenxiangba.com/public_html/phproxy-improved-master/index.php on line 456
JP4721497B2 - Silicon wafer processing method and semiconductor strain sensor manufacturing method - Google Patents
[go: Go Back, main page]

JP4721497B2 - Silicon wafer processing method and semiconductor strain sensor manufacturing method - Google Patents

Silicon wafer processing method and semiconductor strain sensor manufacturing method Download PDF

Info

Publication number
JP4721497B2
JP4721497B2 JP2000285785A JP2000285785A JP4721497B2 JP 4721497 B2 JP4721497 B2 JP 4721497B2 JP 2000285785 A JP2000285785 A JP 2000285785A JP 2000285785 A JP2000285785 A JP 2000285785A JP 4721497 B2 JP4721497 B2 JP 4721497B2
Authority
JP
Japan
Prior art keywords
recess
silicon wafer
oxide film
back surface
strain sensor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2000285785A
Other languages
Japanese (ja)
Other versions
JP2002100601A (en
Inventor
豊 高木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujikura Ltd
Original Assignee
Fujikura Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujikura Ltd filed Critical Fujikura Ltd
Priority to JP2000285785A priority Critical patent/JP4721497B2/en
Publication of JP2002100601A publication Critical patent/JP2002100601A/en
Application granted granted Critical
Publication of JP4721497B2 publication Critical patent/JP4721497B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Landscapes

  • Measuring Fluid Pressure (AREA)
  • Pressure Sensors (AREA)
  • Weting (AREA)

Description

【0001】
【発明の属する技術分野】
この発明は、シリコンウェーハを直接ウエットエッチングする際に発生する微小欠陥の悪影響を改善するシリコンウェーハの加工方法、及び、例えばピエゾ抵抗式圧力センサの製造工程等において、シリコンウェーハにウエットエッチングにより凹所を形成して、その凹所の底部として薄肉部を形成する工程に適用して好適な半導体ひずみセンサの製造方法に関する。
【0002】
【従来の技術】
図2、図3に示すように、一般的なピエゾ抵抗式圧力センサ1は、シリコン基板2の裏面側(図2の下側)に凹所3を設けて、この凹所3の底部として例えば数μm程度の厚みのダイアフラム(薄肉部)4を形成し、その表面側にひずみ検出のための4つのピエゾ抵抗部5を形成した構成である。4つのピエゾ抵抗部5は、図3に示すように直交する2方向にそれぞれ1対を対向させた菱形配置とし、そのうちの1対のピエゾ抵抗部5はダイアフラム4の縁部にかかるように配置し、他の1対のピエゾ抵抗部5はダイアフラム4の中央寄りに配置する。なお、図2、図3では詳細構造は省略しているが、シリコン基板2の表面側には、4つのピエゾ抵抗部5をホイートストーンブリッジ回路を構成するように接続する配線等の圧力検出回路が形成されている。7はシリコン基板2の表面に検出回路を形成するための絶縁膜としての酸化膜(例えばSiO)である。
【0003】
上記のピエゾ抵抗式圧力センサ1は、ガラス製等の台8に接着固定して用いるが、凹所3を密閉したものは絶対圧(真空圧)を検出し、凹所3を外部と連通させたものは相対圧を検出する。このピエゾ抵抗式圧力センサ1おいて、ダイアフラム4部分に矢印のように圧力が作用すると、その圧力でダイアフラム4がへこんでダイアフラム4上のピエゾ抵抗部5に応力が生じ、ピエゾ抵抗効果によりピエゾ抵抗部5の抵抗が変化する。この抵抗の変化を、4つのピエゾ抵抗部5で構成するホイートストーンブリッジ回路の出力として電気的に取り出し、これを圧力に換算して、圧力の検出が行なわれる。
【0004】
上記ダイアフラム4を得るための凹所3は、図5(イ)に示すように、単結晶シリコンの薄い円板であるシリコンウェーハ2’を裏面側からエッチング液でエッチング(ウエットエッチング)して形成するが、従来は、単にシリコンウェーハ2’をエッチングしたままであり、凹所3の内面に特別な処理は施していない。
なお、個々のシリコン基板2は、シリコンウェーハ2’に多数の凹所3を形成した後、後工程で四角のチップに切断して得る。また、エッチング液としてはKOH等を用い、異方性エッチングにより所望のアスペクト比の凹所3を形成する。また、裏面側の酸化膜7は、ガラス台8に接着固定するために好ましくないので、後工程で薬液で除去する(図5(ロ))。
【0005】
【発明が解決しようとする課題】
シリコンウェーハ2’をエッチング液でエッチングして凹所3を形成する際、凹所3の内面には、通常、エッチピットのような微小欠陥が無数に生じる。したがって、エッチングにより得たダイアフラム4の裏面に無数の微小欠陥が存在し、その微小欠陥を起点としてシリコンの破壊が始まり易く、ダイアフラム4の破壊に至ってしまう。すなわち、エッチング時に形成された微小欠陥がダイアフラム4の破壊耐圧(破壊強度)を低下させるという問題がある。
この問題は、ピエゾ抵抗式圧力センサのダイアフラムの場合に限らず、シリコンウェーハを直接ウエットエッチングする種々の場合に生じ、エッチング面に微小欠陥が発生して強度が劣化する。
【0006】
本発明は上記欠点を解消するためになされたもので、予め、シリコンウェーハ表面に形成された回路を覆う絶縁膜としての酸化膜を表面に形成しかつ裏面にも酸化膜を形成したシリコンウェーハの裏面をウエットエッチングして凹所を形成する際に凹所内面に発生する微小欠陥の悪影響を改善することのできるシリコンウェーハの加工方法、及び、ピエゾ抵抗式圧力センサなどの半導体ひずみセンサの製造工程において、シリコンウェーハにウエットエッチングにより凹所を形成して、その凹所の底部として薄肉部を形成する場合に、薄肉部の破壊強度を向上させることのできる半導体ひずみセンサの製造方法を提供することを目的とする。
【0007】
【課題を解決するための手段】
上記課題を解決する本発明のシリコンウェーハの加工方法は、予め、シリコンウェーハ表面に形成された回路を覆う絶縁膜としての酸化膜を表面に形成しかつ裏面にも酸化膜を形成したシリコンウェーハの裏面に凹所を形成して、その凹所の底部として薄肉部を形成するシリコンウェーハの加工方法において、
予め、回路を形成するために必要な絶縁膜としての酸化膜を表面に形成しかつ裏面にも同じ酸化膜を形成した前記シリコンウェーハの裏面にウエットエッチングにより凹所を形成し、
次いで前記凹所の内面を酸化処理して凹所内面に酸化膜を形成し、
次いで、シリコンウェーハ裏面の前記予め形成した酸化膜及び前記凹所内面の酸化膜をエッチングにより除去することを特徴とする。
【0008】
請求項2は、請求項1記載のシリコーンウェーハの加工方法において、凹所の内面に酸化膜を形成する酸化処理が、高温の雰囲気中で酸素や水蒸気に晒す酸化処理であることを特徴とする。
【0009】
請求項3の発明は、シリコン基板の裏面側に設けた凹所の底部として形成された薄肉部の表面側にひずみ検出のためのピエゾ抵抗部を備えた半導体ひずみセンサを製造する半導体ひずみセンサの製造方法であって、
シリコンウェーハに前記薄肉部を形成するに際して、
予め、シリコンウェーハ表面に形成された回路を覆う酸化膜を表面に形成しかつ裏面にも酸化膜を形成したシリコンウェーハの裏面にウエットエッチングにより凹所を形成し、
次いで前記凹所の内面を酸化処理して凹所内面に酸化膜を形成し、
次いで、シリコンウェーハ裏面の前記予め形成した酸化膜及び前記凹所内面の酸化膜をエッチングにより除去することを特徴とする。
請求項4は、請求項3記載の半導体ひずみセンサの製造方法において、凹所の内面に酸化膜を形成する酸化処理が、高温の雰囲気中で酸素や水蒸気に晒す酸化処理であることを特徴とする。
【0010】
【発明の実施の形態】
以下、本発明の実施の形態を図1〜図4を参照して説明する。図1は本発明のシリコンウェーハの加工方法を説明する図であり、(イ)はシリコンウェーハ2’の裏面側(検出回路面側と反対側)にウエットエッチングにより凹所3を形成した段階のシリコンウェーハ断面図である。酸化膜(例えばSiO2)7は、圧力検出回路を形成するための絶縁膜として予め形成している。凹所3のエッチングに際しては、下面側の酸化膜7の外側に、凹所3に対応するパターンでシリコン窒化膜による図示略のマスクを形成(なお、表面側には保護膜として全体に形成)した後、エッチングを行なう。エッチング液としてはKOH等を用い、異方性エッチングにより所望のアスペクト比の凹所3を形成する。
次いで、図1(イ)のシリコンウェーハ2’を高温の雰囲気中で酸素や水蒸気に晒す酸化処理を行なって、図1(ロ)に示すように、シリコンウェーハ2’の凹所3の内面に酸化膜(例えばSiO)9を形成する。
次いで、図1(ハ)に示すように、シリコン基板2の裏面側をエッチング液でエッチングして、裏面側の酸化膜7、9の全体を除去する。
なお、酸化膜を除去する場合でも、工程の最後に酸化膜を除去する工程とすることで、他のエッチング工程における保護膜として利用することも可能である。
【0011】
前記図1(ロ)の凹所3の内面に酸化膜9を形成する工程において、従来、ウエットエッチングした面に無数に生じていた微小欠陥が酸化処理により取り除かれる。
このように、破壊の起点となる微小欠陥が取り除かれたことで、ダイアフラム4の破壊強度が大幅に向上する。圧力センサとしてパッケージ化した状態で、ダイアフラム4が破壊するまで空気圧を高める破壊耐圧試験を行なった結果によれば、酸化処理した本発明品では、酸化処理しない従来品と比べて破壊耐圧が約2倍であった。すなわち、本発明品では、従来品で破壊に至った空気圧の約2倍の空気圧を作用させるまで、ダイアフラム4の破壊に至らなかった。
【0012】
本発明は、上述の圧力センサ1に限らず、図4に示すように、加速度センサ11に適用することもできる。図4の加速度センサ11は簡略化して示したものであるが、シリコン基板12の裏面側(図4の下側)の中央部20の周囲にウエットエッチングによる凹所13を形成して、凹所13の底部として薄肉部14を形成し、中央部20にガラス製の錘21を固定し、周囲部を同じくガラス製の台22に接着固定した構成である。
【0013】
この加速度センサ11に加速度が作用すると、錘21の部分が振り子のように動き(加速度の方向に応じて図4の左右方向その他種々の方向に動く)、これにより薄肉部14にひずみ変形が生じて、シリコン基板12の上面(検出回路面)に形成されているピエゾ抵抗部5の抵抗値が変化し、この抵抗値の変化を電気的に取り出して、加わった加速度に変換する。
【0014】
上記の加速度センサ11の製造工程で、シリコンウェーハにウエットエッチングにより凹所13を形成して薄肉部14を形成する際に、前述と同様に、凹所13の内面に酸化膜(SiO)を形成して、凹所13の内面に発生している無数の微小欠陥を取り除く。
この加速度センサ11の場合も、薄肉部11にエッチング時の微小欠陥があると、薄肉部11の破壊強度が低下するが、微小欠陥が取り除かれているので、薄肉部14の破壊強度が向上する。
【0015】
本発明は、上述の圧力センサ1、加速度センサ11に限らず、シリコン基板の裏面側に設けた凹所の底部として形成された薄肉部の表面側にひずみ検出のための抵抗素子を備えた種々の半導体ひずみセンサを製造する場合に適用することができ、また、予め、シリコンウェーハ表面に形成された回路を覆う酸化膜を表面に形成しかつ裏面にも酸化膜を形成したシリコンウェーハの裏面に凹所を形成して、その凹所の底部として薄肉部を形成する場合に適用することができる。
【0016】
【発明の効果】
請求項1の発明のシリコンウェーハの加工方法によれば、予め、シリコンウェーハ表面に形成された回路を覆う酸化膜を表面に形成しかつ裏面にも酸化膜を形成したシリコンウェーハの裏面に凹所を形成して、その凹所の底部として薄肉部を形成するシリコンウェーハの加工方法において、予め、シリコンウェーハ表面に形成された回路を覆う絶縁膜としての酸化膜を表面に形成しかつ裏面にも酸化膜を形成した前記シリコンウェーハの裏面にウエットエッチングにより凹所を形成し、次いで前記凹所の内面を酸化処理して凹所内面に酸化膜を形成し、次いで、シリコンウェーハ裏面の前記予め形成した酸化膜及び前記凹所内面の酸化膜をエッチングにより除去するするので、凹所形成時のウエットエッチングにより凹所内面に生じた無数の微小欠陥が前記の酸化処理により取り除かれ、微小欠陥によるシリコンの強度低下を防止することができ、薄肉部の破壊強度を大幅に向上させることができた。
【0018】
半導体ひずみセンサである圧力センサや加速度センサ等におけるダイアフラムあるいは薄肉部は、厚みが極めて薄く微小欠陥の影響が大きいので、請求項3の発明のように半導体ひずみセンサの製造に適用して、特に効果的である。
【図面の簡単な説明】
【図1】本発明のシリコンウェーハの加工方法を説明する図であり、(イ)はシリコンウェーハの裏面側(検出回路面側と反対側)にウエットエッチングにより凹所を形成した段階のシリコンウェーハ断面図、(ロ)は凹所の内面に酸化膜を形成した段階のシリコンウェーハ断面図、(ハ)は裏面側の酸化膜全体を除去した段階のシリコンウェーハ断面図である。
【図2】本発明方法により製造しようとするピエゾ抵抗式圧力センサの模式的な断面図である。
【図3】図2の平面図である。
【図4】本発明方法により製造しようとする加速度センサの模式的な断面図である。
【図5】従来のシリコンウェーハの加工方法を説明する図であり、(イ)はシリコンウェーハの裏面側(検出回路面側と反対側)をエッチングして凹所を形成した段階のシリコンウェーハ断面図、(ロ)は裏面の酸化膜を除去した段階のシリコンウェーハ断面図である。
【符号の説明】
1 ピエゾ抵抗式圧力センサ
2、12 シリコン基板
2’ シリコンウェーハ
3、13 凹所
7 酸化膜
9 (凹所の内面に形成した)酸化膜
11 加速度センサ
14 薄肉部
21 錘
22 台
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for processing a silicon wafer that improves the adverse effects of microdefects that occur when a silicon wafer is directly wet etched , and, for example, in a manufacturing process of a piezoresistive pressure sensor. The present invention relates to a method for manufacturing a semiconductor strain sensor suitable for use in a process of forming a thin portion as the bottom of the recess .
[0002]
[Prior art]
As shown in FIGS. 2 and 3, a general piezoresistive pressure sensor 1 is provided with a recess 3 on the back side (lower side of FIG. 2) of a silicon substrate 2, and the bottom of the recess 3 is, for example, A diaphragm (thin wall portion) 4 having a thickness of about several μm is formed, and four piezoresistive portions 5 for strain detection are formed on the surface side. As shown in FIG. 3, the four piezoresistive portions 5 are arranged in a diamond shape in which two pairs are opposed to each other in two orthogonal directions, and one pair of the piezoresistive portions 5 is arranged so as to cover the edge of the diaphragm 4. The other pair of piezoresistive portions 5 are arranged near the center of the diaphragm 4. Although the detailed structure is omitted in FIGS. 2 and 3, pressure detection is performed on the surface of the silicon substrate 2 such as wiring that connects the four piezoresistors 5 so as to form a Wheatstone bridge circuit. A circuit is formed. Reference numeral 7 denotes an oxide film (for example, SiO 2 ) as an insulating film for forming a detection circuit on the surface of the silicon substrate 2.
[0003]
The piezoresistive pressure sensor 1 is used by being bonded and fixed to a table 8 made of glass or the like, but the one that seals the recess 3 detects absolute pressure (vacuum pressure) and makes the recess 3 communicate with the outside. The one detects the relative pressure. In the piezoresistive pressure sensor 1, when pressure acts on the diaphragm 4 as shown by an arrow, the diaphragm 4 is dented by the pressure, and stress is generated in the piezoresistive portion 5 on the diaphragm 4, and the piezoresistive effect causes piezoresistance. The resistance of the part 5 changes. This change in resistance is electrically taken out as an output of a Wheatstone bridge circuit composed of four piezoresistors 5 and is converted into pressure to detect the pressure.
[0004]
The recess 3 for obtaining the diaphragm 4 is formed by etching (wet etching) a silicon wafer 2 ′, which is a thin disc of single crystal silicon, from the back side with an etching solution as shown in FIG. However, conventionally, the silicon wafer 2 ′ is simply etched and no special treatment is applied to the inner surface of the recess 3.
Each silicon substrate 2 is obtained by forming a large number of recesses 3 in a silicon wafer 2 ′ and then cutting it into square chips in a later step. Further, KOH or the like is used as an etchant, and the recess 3 having a desired aspect ratio is formed by anisotropic etching. Moreover, since the oxide film 7 on the back surface side is not preferable because it is bonded and fixed to the glass table 8, it is removed with a chemical solution in a subsequent process (FIG. 5B).
[0005]
[Problems to be solved by the invention]
When the recess 3 is formed by etching the silicon wafer 2 ′ with an etching solution, innumerable micro defects such as etch pits are usually generated on the inner surface of the recess 3. Therefore, innumerable micro defects exist on the back surface of the diaphragm 4 obtained by etching, and silicon breakdown is easily started from the micro defects as a starting point, and the diaphragm 4 is destroyed. That is, there is a problem that the minute defect formed at the time of etching reduces the breakdown voltage (breakdown strength) of the diaphragm 4.
This problem occurs not only in the case of a piezoresistive pressure sensor diaphragm, but also in various cases in which a silicon wafer is directly wet-etched.
[0006]
The present invention has been made to solve the above drawbacks, in advance, a silicon wafer having an oxide film formed was formed on the surface and back surface to be oxidation film as an insulating film covering the circuit formed on the silicon wafer surface Silicon wafer processing method and semiconductor strain sensor such as piezoresistive pressure sensor that can improve the adverse effect of minute defects generated on the inner surface of the recess when wet etching is performed on the back surface of the substrate In the process, when a recess is formed in a silicon wafer by wet etching and a thin portion is formed as the bottom of the recess, a method for manufacturing a semiconductor strain sensor capable of improving the fracture strength of the thin portion is provided. For the purpose.
[0007]
[Means for Solving the Problems]
Processing method of a silicon wafer of the present invention, in advance, a silicon wafer having an oxide film formed was formed on the surface and back surface to be oxidation film as an insulating film covering the circuit formed on the silicon wafer surface to solve the above problems In the silicon wafer processing method of forming a recess on the back surface of the, and forming a thin portion as the bottom of the recess,
Form a recess by wet etching in advance on the back surface of the silicon wafer on which an oxide film as an insulating film necessary for forming a circuit is formed on the front surface and the same oxide film is formed on the back surface,
Next, the inner surface of the recess is oxidized to form an oxide film on the inner surface of the recess,
Next, the previously formed oxide film on the back surface of the silicon wafer and the oxide film on the inner surface of the recess are removed by etching.
[0008]
A second aspect of the present invention is the method for processing a silicon wafer according to the first aspect, wherein the oxidation treatment for forming an oxide film on the inner surface of the recess is an oxidation treatment that is exposed to oxygen or water vapor in a high-temperature atmosphere. .
[0009]
According to a third aspect of the present invention, there is provided a semiconductor strain sensor for manufacturing a semiconductor strain sensor having a piezoresistive portion for strain detection on a surface side of a thin portion formed as a bottom portion of a recess provided on a back surface side of a silicon substrate. A manufacturing method comprising:
When forming the thin portion on the silicon wafer,
Previously, to form a recess by wet etching the back surface of the silicon wafer to form an oxide film formed by and oxidation film on the back surface to the surface that covers the circuit formed on the silicon wafer surface,
Next, the inner surface of the recess is oxidized to form an oxide film on the inner surface of the recess,
Next, the previously formed oxide film on the back surface of the silicon wafer and the oxide film on the inner surface of the recess are removed by etching.
According to a fourth aspect of the present invention, in the method for manufacturing a semiconductor strain sensor according to the third aspect, the oxidation treatment for forming an oxide film on the inner surface of the recess is an oxidation treatment that is exposed to oxygen or water vapor in a high-temperature atmosphere. To do.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to FIGS. FIG. 1 is a view for explaining a silicon wafer processing method according to the present invention. FIG. 1A shows a state in which a recess 3 is formed by wet etching on the back surface side of the silicon wafer 2 ′ (opposite the detection circuit surface side). It is a silicon wafer sectional view. The oxide film (for example, SiO 2 ) 7 is formed in advance as an insulating film for forming a pressure detection circuit. When the recess 3 is etched, a mask (not shown) made of a silicon nitride film is formed outside the oxide film 7 on the lower surface side in a pattern corresponding to the recess 3 (the entire surface is formed as a protective film on the surface side). Then, etching is performed. As the etching solution, KOH or the like is used, and the recess 3 having a desired aspect ratio is formed by anisotropic etching.
Next, the silicon wafer 2 'shown in FIG. 1 (a) is subjected to an oxidation treatment by exposing it to oxygen or water vapor in a high-temperature atmosphere. As shown in FIG. 1 (b), the inner surface of the recess 3 of the silicon wafer 2' is formed. An oxide film (for example, SiO 2 ) 9 is formed.
Next, as shown in FIG. 1C, the back surface side of the silicon substrate 2 is etched with an etching solution to remove the entire oxide films 7 and 9 on the back surface side .
Even when the oxide film is removed, it can be used as a protective film in another etching process by removing the oxide film at the end of the process.
[0011]
In the step of forming the oxide film 9 on the inner surface of the recess 3 in FIG. 1 (b), innumerable micro defects conventionally generated on the wet-etched surface are removed by oxidation treatment.
As described above, since the micro defect that is the starting point of the destruction is removed, the breaking strength of the diaphragm 4 is greatly improved. According to the result of the destructive pressure test in which the air pressure is increased until the diaphragm 4 breaks in the packaged state as the pressure sensor, the oxidized product of the present invention has a breakdown voltage of about 2 as compared with the conventional product that is not oxidized. It was twice. That is, in the product of the present invention, the diaphragm 4 was not destroyed until an air pressure about twice as high as that of the conventional product was applied.
[0012]
The present invention can be applied not only to the pressure sensor 1 described above but also to an acceleration sensor 11 as shown in FIG. Although the acceleration sensor 11 of FIG. 4 is shown in a simplified manner, a recess 13 is formed by wet etching around the central portion 20 on the back surface side (lower side of FIG. 4) of the silicon substrate 12. The thin-walled portion 14 is formed as the bottom portion of the glass 13, the glass weight 21 is fixed to the central portion 20, and the peripheral portion is similarly bonded and fixed to the glass base 22.
[0013]
When acceleration acts on the acceleration sensor 11, the portion of the weight 21 moves like a pendulum (moves in the left-right direction and other various directions in FIG. 4 in accordance with the direction of acceleration), thereby causing distortion in the thin-walled portion 14. Thus, the resistance value of the piezoresistive portion 5 formed on the upper surface (detection circuit surface) of the silicon substrate 12 changes, and this change in resistance value is electrically extracted and converted into an applied acceleration.
[0014]
In the manufacturing process of the acceleration sensor 11 described above, when the recess 13 is formed on the silicon wafer by wet etching to form the thin portion 14, an oxide film (SiO 2 ) is formed on the inner surface of the recess 13 as described above. The countless minute defects generated on the inner surface of the recess 13 are removed.
In the case of the acceleration sensor 11 as well, if the thin portion 11 has a minute defect at the time of etching, the breaking strength of the thin portion 11 is reduced. However, since the minute defect is removed, the breaking strength of the thin portion 14 is improved. .
[0015]
The present invention is not limited to the pressure sensor 1 and the acceleration sensor 11 described above, and various types of resistance elements for strain detection are provided on the surface side of the thin portion formed as the bottom of the recess provided on the back surface side of the silicon substrate. can be applied to a case of manufacturing a semiconductor strain sensor, also in advance, the back surface of the silicon wafer to form an oxide film formed by and oxidation film on the back surface to the surface that covers the circuit formed on the silicon wafer surface The present invention can be applied to a case where a recess is formed in the bottom and a thin portion is formed as the bottom of the recess.
[0016]
【The invention's effect】
According to the processing method of a silicon wafer of the invention of claim 1, advance, concave to the rear surface of a silicon wafer to form an oxide film on the surface and was also form acid monolayer on the back surface for covering the circuit formed on the silicon wafer surface forming a Tokoro, in the processing method of a silicon wafer to form a thin portion as the bottom of the recess, in advance, the oxide film as an insulating film covering the circuit formed on the silicon wafer surface is formed on the surface and the back surface forming a recess by wet etching the back surface of the silicon wafer was also form acid monolayer, followed by oxidizing the inner surface of the recess to form an oxide film in the recess inner surface, then the silicon wafer back surface Since the oxide film formed in advance and the oxide film on the inner surface of the recess are removed by etching, the countless number generated on the inner surface of the recess by wet etching at the time of forming the recess Small defects are removed by oxidation of the can prevent strength reduction of the silicon by the minute defect, it was possible to significantly improve the fracture strength of the thin portion.
[0018]
Semiconductor strain diaphragm or thin wall portion of the pressure sensor, an acceleration sensor or the like is a sensor, since the influence of the very thin micro-defects is large thickness, it applied to the manufacture of semiconductor strain sensor as in the invention of claim 3, especially effective Is.
[Brief description of the drawings]
FIGS. 1A and 1B are diagrams for explaining a silicon wafer processing method according to the present invention, in which FIG. 1A shows a silicon wafer in which a recess is formed by wet etching on the back side of the silicon wafer (opposite to the detection circuit side). Sectional drawing, (B) is a sectional view of the silicon wafer at the stage where an oxide film is formed on the inner surface of the recess, and (C) is a sectional view of the silicon wafer at the stage where the entire oxide film on the back side is removed.
FIG. 2 is a schematic cross-sectional view of a piezoresistive pressure sensor to be manufactured by the method of the present invention.
FIG. 3 is a plan view of FIG. 2;
FIG. 4 is a schematic cross-sectional view of an acceleration sensor to be manufactured by the method of the present invention.
FIGS. 5A and 5B are diagrams for explaining a conventional silicon wafer processing method, wherein FIG. 5A is a cross-sectional view of a silicon wafer at a stage where a recess is formed by etching the back surface side (opposite the detection circuit surface side) of the silicon wafer. FIG. 4B is a cross-sectional view of the silicon wafer at the stage where the oxide film on the back surface is removed.
[Explanation of symbols]
1 Piezoresistive pressure sensor 2, 12 Silicon substrate 2 'Silicon wafer 3, 13 Recess 7 Oxide film 9 Oxide film 11 (formed on the inner surface of the recess) Acceleration sensor 14 Thin portion 21 Weight 22

Claims (4)

予め、シリコンウェーハ表面に形成された回路を覆う絶縁膜としての酸化膜を表面に形成しかつ裏面にも酸化膜を形成したシリコンウェーハの裏面に凹所を形成して、その凹所の底部として薄肉部を形成するシリコンウェーハの加工方法において、
予め、シリコンウェーハ表面に形成された回路を覆う絶縁膜としての酸化膜を表面に形成しかつ裏面にも酸化膜を形成した前記シリコンウェーハの裏面にウエットエッチングにより凹所を形成し、
次いで前記凹所の内面を酸化処理して凹所内面に酸化膜を形成し、
次いで、シリコンウェーハ裏面の前記予め形成した酸化膜及び前記凹所内面の酸化膜をエッチングにより除去することを特徴とするシリコンウェーハの加工方法。
Previously, by forming a recess on the back surface of a silicon wafer to form an oxide film formed on the surface and back surface to be oxidation film as an insulating film covering the circuit formed on the silicon wafer surface, the bottom of the recess In the silicon wafer processing method for forming a thin portion as
Previously, to form a recess by wet etching the back surface of the silicon wafer to form an oxide film formed on the surface and back surface to be oxidation film as an insulating film covering the circuit formed on the silicon wafer surface,
Next, the inner surface of the recess is oxidized to form an oxide film on the inner surface of the recess,
Next, the silicon wafer processing method, wherein the previously formed oxide film on the back surface of the silicon wafer and the oxide film on the inner surface of the recess are removed by etching.
前記凹所の内面に酸化膜を形成する酸化処理は、高温の雰囲気中で酸素や水蒸気に晒す酸化処理であることを特徴とする請求項1記載のシリコーンウェーハの加工方法。  The method for processing a silicon wafer according to claim 1, wherein the oxidation treatment for forming an oxide film on the inner surface of the recess is an oxidation treatment in which the oxide film is exposed to oxygen or water vapor in a high-temperature atmosphere. シリコン基板の裏面側に設けた凹所の底部として形成された薄肉部の表面側にひずみ検出のためのピエゾ抵抗部を備えた半導体ひずみセンサを製造する半導体ひずみセンサの製造方法であって、
シリコンウェーハに前記薄肉部を形成するに際して、
予め、シリコンウェーハ表面に形成された回路を覆う絶縁膜としての酸化膜を表面に形成しかつ裏面にも酸化膜を形成したシリコンウェーハの裏面にウエットエッチングにより凹所を形成し、
次いで前記凹所の内面を酸化処理して凹所内面に酸化膜を形成し、
次いで、シリコンウェーハ裏面の前記予め形成した酸化膜及び前記凹所内面の酸化膜をエッチングにより除去することを特徴とする半導体ひずみセンサの製造方法。
A semiconductor strain sensor manufacturing method for manufacturing a semiconductor strain sensor including a piezoresistive portion for strain detection on a surface side of a thin portion formed as a bottom portion of a recess provided on a back surface side of a silicon substrate,
When forming the thin portion on the silicon wafer,
Previously, to form a recess by wet etching the back surface of the silicon wafer having an oxide film formed was formed on the surface and back surface to be oxidation film as an insulating film covering the circuit formed on the silicon wafer surface,
Next, the inner surface of the recess is oxidized to form an oxide film on the inner surface of the recess,
Next, the semiconductor strain sensor manufacturing method, wherein the pre-formed oxide film on the back surface of the silicon wafer and the oxide film on the inner surface of the recess are removed by etching.
前記凹所の内面に酸化膜を形成する酸化処理は、高温の雰囲気中で酸素や水蒸気に晒す酸化処理であることを特徴とする請求項3記載の半導体ひずみセンサの製造方法。  4. The method of manufacturing a semiconductor strain sensor according to claim 3, wherein the oxidation treatment for forming an oxide film on the inner surface of the recess is an oxidation treatment which is exposed to oxygen or water vapor in a high temperature atmosphere.
JP2000285785A 2000-09-20 2000-09-20 Silicon wafer processing method and semiconductor strain sensor manufacturing method Expired - Lifetime JP4721497B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000285785A JP4721497B2 (en) 2000-09-20 2000-09-20 Silicon wafer processing method and semiconductor strain sensor manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000285785A JP4721497B2 (en) 2000-09-20 2000-09-20 Silicon wafer processing method and semiconductor strain sensor manufacturing method

Publications (2)

Publication Number Publication Date
JP2002100601A JP2002100601A (en) 2002-04-05
JP4721497B2 true JP4721497B2 (en) 2011-07-13

Family

ID=18769795

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000285785A Expired - Lifetime JP4721497B2 (en) 2000-09-20 2000-09-20 Silicon wafer processing method and semiconductor strain sensor manufacturing method

Country Status (1)

Country Link
JP (1) JP4721497B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5374716B2 (en) * 2008-03-18 2013-12-25 エプコス アクチエンゲゼルシャフト Microphone and manufacturing method thereof

Also Published As

Publication number Publication date
JP2002100601A (en) 2002-04-05

Similar Documents

Publication Publication Date Title
JP3506932B2 (en) Semiconductor pressure sensor and method of manufacturing the same
JPH0897439A (en) One-chip integrated sensor
JPH10135487A (en) Integrated piezoresistive pressure sensor and method of manufacturing the same
JP3994531B2 (en) Manufacturing method of semiconductor pressure sensor
JP4721497B2 (en) Silicon wafer processing method and semiconductor strain sensor manufacturing method
JP4161432B2 (en) Semiconductor pressure sensor and manufacturing method thereof
US6718824B2 (en) Semiconductor dynamic quantity detecting sensor and manufacturing method of the same
JP4258100B2 (en) Manufacturing method of semiconductor pressure sensor
JP2000022168A (en) Semiconductor acceleration sensor and manufacture thereof
JP2002323513A (en) Semiconductor device and method of manufacturing the same
JPH11220137A (en) Semiconductor pressure sensor and method of manufacturing the same
CN210559358U (en) Pressure sensor
JP3492673B1 (en) Manufacturing method of capacitance type acceleration sensor
JPH09113390A (en) Semiconductor pressure measuring device and manufacturing method thereof
JPH11340189A (en) Method for forming recess or through hole in micromachine production
JPH05167083A (en) Cavity region built-in semiconductor substrate and manufacturing method thereof
JPH06203712A (en) Absolute pressure type semiconductor pressure sensor
JP3942474B2 (en) Method for forming a diaphragm on a semiconductor substrate
JPH0636980A (en) Manufacture of thin film
JPH10284737A (en) Manufacturing method of capacitance type semiconductor sensor
JP3831650B2 (en) Pressure sensor and manufacturing method thereof
JP2006086318A (en) Electromechanical transducer and manufacturing method therefor
JP3055508B2 (en) Manufacturing method of pressure detector
JP2004125616A (en) Manufacturing method of semiconductor acceleration sensor
JP3405222B2 (en) Semiconductor acceleration sensor element and method of manufacturing the same

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20070529

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20090612

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090616

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20090817

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090924

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20091119

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20091215

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100215

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20100309

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20110405

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140415

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140415

Year of fee payment: 3

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250