JP4729072B2 - Echo erasing device, echo erasing method, echo erasing program, and recording medium - Google Patents

Description

  The present invention relates to an echo erasing apparatus, an echo erasing method, an echo erasing program, and a recording medium that are applied to, for example, a communication conference system having an acoustic reproduction system and erase acoustic echoes that cause acoustic feedback and cause hearing problems.

  FIG. 1 shows a functional configuration example of a sound reproduction system using a conventional echo canceling apparatus. The sound reproduction system includes a first serial / parallel conversion unit 910, a first parallel / serial conversion unit 920, an acoustic signal reproduction unit (speaker) 930, an acoustic signal sound collection unit (microphone) 950, and a second serial / parallel conversion unit. 960, a second parallel / serial converter 970, and an echo canceller 800. The acoustic signal reproduced by the acoustic signal reproducing unit 930 is picked up by the acoustic signal collecting unit 950 via the echo path 940 and becomes an echo. The echo canceller 800 is a device for generating a signal that cancels the echo. As the conventional echo canceller 800, there is an example described in Non-Patent Document 1. The echo canceller 800 calculates the frequency characteristics of a pseudo echo path having a length L (that is, the number of taps, for example, L = 1664) having the impulse response of the echo path 940 as an element. Here, n is a number (sample point number) indicating discrete time at a predetermined interval. Sampling is performed, for example, at a sampling frequency of 16 kHz (16000 times per second) by replacing a value in a certain section of a variable with one representative value in order to convert an analog audio signal into a digital signal.

The first serial / parallel converter 910 includes N (where N is an integer equal to or greater than 2) time-series reproduction signals x (1),..., X (N) (one frame has N reproduction signals x ( The reproduction signal vector x _N (k) having n) as an element is generated. Here, k is a number indicating a frame number. The first parallel / serial converter 920 converts the reproduction signal vector x _N (k) into reproduction signals x (1),..., X (N).

  The acoustic signal reproducing unit 930 converts the reproduction signal x (n), which is a digital signal, into an analog signal and reproduces it. The acoustic signal collecting unit 950 collects an analog signal and converts it into a collected sound signal y (n) that is a digital signal. As described above, the output signal of the first parallel / serial conversion unit 920 and the input signal of the second serial / parallel conversion unit 960 are digital signals, but the signal reproduced by the acoustic signal reproduction unit 930 and the acoustic signal sound collection unit 950 are. The signal collected by is an analog signal. In the following description, it is not specifically mentioned whether the signal is a digital signal or an analog signal, and in which component the analog signal and the digital signal are converted, but the signal processing target is the digital signal. And the signal in the echo path 940 is an analog signal. In addition, it is naturally determined from the above relationship which component unit converts the analog signal and the digital signal.

The second serial / parallel converter 960 generates a collected sound signal vector y _N (k) having _N time-series collected sound signals y (1),..., Y (N) as elements. The echo cancellation apparatus 800 includes a first vector increasing unit 810, a first frequency analyzing unit 820, an integrating unit 830, a frequency synthesizing unit 840, a vector decreasing unit 850, a subtracting unit 860, a second vector increasing unit 870, and a second frequency analyzing unit. 880, a filter update unit 890, and by calculating the frequency characteristics of the pseudo echo path, a residual echo vector in which echo components are eliminated from the reproduction signal vector x _N (k) and the collected sound signal vector y _N (k) e _N (k) is obtained. The second parallel / serial converter 970 converts the residual echo vector e _N (k) into residual echo signals e (1),..., E (N).
G. Clark, S. Parker, and S. Mitra, “A unified approach to time- and frequency- domain realization of FIR adaptive digital filters,” IEEE Trans. Acoustics, Speech, and Signal Processing, vol. ASSP-31, no .5, pp.1073-1083, Oct. 1983.

  The echo canceller 800 has a long frequency of N + L for each frame in frequency analysis (processing by the first frequency analysis unit 820 and second frequency analysis unit 880) and frequency synthesis (processing by the frequency synthesis unit 840) with a large amount of calculation. Processing of analysis points was necessary. For this reason, the conventional echo canceller requires a huge calculation cost. An object of the present invention is to provide an echo canceller that reduces the amount of calculation per frame.

  The echo cancellation apparatus of the present invention includes a first vector increasing unit, a first frequency analyzing unit, an integrating unit, a frequency synthesizing unit, a vector reducing unit, a subtracting unit, a second vector increasing unit, a second frequency analyzing unit, and a filter updating unit. Prepare. The first vector increasing unit inputs a reproduction signal vector having N (where N is an integer of 2 or more) time-series reproduction signals (1 frame) as elements, and K (where K is 2 or more). A reproduction signal increase vector consisting of M elements (where M is an integer equal to or greater than KN) including each element of the (integral) reproduction signal vector is output. The first frequency analysis unit frequency-converts the reproduction signal increase vector and outputs a frequency domain reproduction signal. The integrating unit integrates the frequency domain reproduction signal and the frequency domain filter coefficient, and outputs a frequency domain pseudo echo. The frequency synthesizer converts the frequency domain pseudo echo into the time domain, and outputs a pseudo echo increase vector composed of M elements. The vector reduction unit generates K pseudo echo vectors including N elements from the pseudo echo increase vector, and a sound collection signal vector having N time series sound collection signals (one frame) as elements is input. One pseudo echo vector is output at each timing. The subtracting unit performs subtraction between the collected sound signal vector and the pseudo echo vector and outputs a residual echo vector. The second vector increasing unit outputs a residual echo increase vector composed of M elements including each element of K residual echo vectors. The second frequency analysis unit frequency-converts the residual echo increase vector and outputs a frequency domain residual echo. The filter updating unit updates the frequency domain filter coefficient using the product of each of the complex conjugate of the frequency domain reproduction signal and the frequency domain residual echo.

  In other words, the echo canceller of the present invention has a playback signal vector having N (where N is an integer equal to or greater than 2) time series playback signals (one frame) and N time series sound pickups. An echo canceling apparatus that receives a sound collection signal vector having a signal (one frame) as an input and cancels an echo component of the reproduction signal vector included in the sound collection signal vector using a pseudo echo vector generated from the reproduction signal vector The first vector increasing unit, the pseudo echo increasing vector calculating unit, the vector decreasing unit, and the subtracting unit are provided as follows. The first vector increase unit obtains a reproduction signal increase vector composed of M (where M is an integer equal to or greater than KN) elements including K elements (where K is an integer equal to or greater than 2). . The pseudo echo increase vector calculation unit obtains a pseudo echo increase vector composed of M elements by performing a calculation in the frequency domain on the reproduction signal increase vector. The vector reduction unit generates K pseudo echo vectors including N elements from the pseudo echo increase vector. The subtracting unit performs subtraction between the sound collection signal vector and the pseudo echo vector, and outputs a residual echo vector from which the echo component of the reproduction signal vector included in the sound collection signal vector is eliminated.

  According to the echo canceling apparatus of the present invention, the frequency analysis points per K frame are set to M while the delay is suppressed by performing frequency analysis and frequency synthesis for K frames collectively. Here, when M = KN + L (where L is the number of taps), the number of frequency analysis points per frame is N + L / K. For example, when N = 128, L = 1664, and K = 2, in the present invention, N + L / K = 960 compared to the conventional N + L = 1789. That is, the calculation amount can be reduced to about ½. That is, the echo canceller of the present invention can reduce the amount of calculation while suppressing delay (or the same as the conventional one).

[analysis]
First, processing of the conventional echo canceller 800 is analyzed. FIG. 2 shows an algorithm delay (delay in the first serial / parallel converter 910 and second serial / parallel converter 960) in the sound reproduction system of FIG. 1 for one frame, and an implementation delay (first parallel / parallel). The time chart when the delay in the serial conversion unit 920 and the second parallel / serial conversion unit 970) can be ignored is shown. Also, FIG. 3 shows that the algorithm delay (the delay in the first serial / parallel converter 910 and the second serial / parallel converter 960) in the sound reproduction system in FIG. The time chart when the delay in the parallel / serial conversion unit 920 and the second parallel / serial conversion unit 970) corresponds to one frame is shown. In the figure, the algorithm delay is represented by a two-dot chain line, and the implementation delay is represented by a one-dot chain line.

The first serial / parallel converter 910 includes N time-series reproduction signals x (kN−N + 1),..., X (kN) (one frame is composed of N reproduction signals x (n)). , X (kN)} ^T is generated, with the reproduction signal vector x _N (k) = {x (kN−N + 1),. However, N is an integer greater than or equal to 2, for example 128. At this time, an algorithm delay of one frame always occurs. The first vector increasing unit 810 receives the reproduction signal vector x _N (k) as an input, and a reproduction signal increase vector x _{M ′} (k) composed of M ′ elements including each element of the reproduction signal vector x _N (k). Is output. For example, by discarding N pieces of data in the order of the oldest time of x _{M ′} (k−1) and connecting to x _N (k), x _{M ′} (k) is obtained. Further, M ′ = N + L. However, L is the filter length (the number of taps) of the time domain corresponding filter, for example, 1664. The first frequency analysis unit 820 performs frequency conversion on the reproduction signal increase vector x _{M ′} (k) and has M ′ frequency components X _{m ′} (k) (where m ′ = 1,..., M ′). The frequency domain reproduction signal X ′ (k) is output. The integrating unit 830 integrates each element of the frequency domain reproduction signal X ′ (k) and the frequency domain filter coefficient W ′, and outputs a frequency domain pseudo echo D ^ ′ (k). In particular,

Calculate as follows. The frequency synthesizer 840 converts the frequency domain pseudo echo D ^ '(k) into the time domain, and outputs a pseudo echo increase vector d ^ _M' (k) composed of M 'elements. The vector reduction unit 850 generates a pseudo echo vector d _N (k) composed of N elements from the pseudo echo increase vector d _M (k). For example, in the case where the pseudo echo increase vector d ^ _{M ′} (k) is a vector in which the data of the oldest time is arranged in chronological order, N pieces of data are selected later and the pseudo echo vector d ^ _N (k ).

The first parallel / serial converter 920 converts the reproduction signal vector x _N (k) into reproduction signals x (1),..., X (N). When the mounting delay is negligible (FIG. 2), the reproduction signal x (n) is sequentially output without a delay at a predetermined interval (for example, 10 ms) and reproduced via the acoustic signal reproduction unit 930. When there is a mounting delay of one frame (FIG. 3), after the delay of one frame, the reproduction signal x (n) is sequentially output at a predetermined interval and reproduced via the acoustic signal reproduction unit 930. The second serial / parallel converter 960 has a sound collection signal vector y _N (k) = {y (kN−N + 1) having N time-series sound collection signals y (1),..., Y (N) as elements. ,..., Y (kN)} ^T is generated. At this time, an algorithm delay of one frame always occurs.

The subtraction unit 860 subtracts the collected sound signal vector y _N (k) and the pseudo echo vector d ^ _N (k), and the residual echo vector e _N (k) = y _N (k) −d ^ _N (k ) Is output. The second parallel / serial converter 970 converts the residual echo vector e _N (k) into residual echo signals e (1),..., E (N). When the mounting delay can be ignored (FIG. 2), the residual echo signal e (n) is sequentially output at a predetermined interval without delay. When there is a mounting delay of one frame (FIG. 3), the residual echo signal e (n) is sequentially output at a predetermined interval after the delay of one frame.

The second vector increasing unit 870 outputs a residual echo increase vector e _{M ′} (k) including M ′ elements including each element of the residual echo vector e _N (k). Specifically, M ′ = N + L (where L is the number of taps). The second frequency analysis unit 880 performs frequency conversion on the residual echo increase vector e _M ′ (k) and outputs a frequency domain residual echo E ′ (k).

として更新する。ここで、Ｗ⁻’はメモリを上書きする前の周波数領域フィルタ係数、Ｐは拘束行列である。更新ベクトルΔＷ’は、要素ΔＷ’_ｍ’ごとに、例えば、

として計算する。ここで、μはステップサイズ、＊は共役複素数、Ｐ［，γ］はγフレームの平均処理を示す。なお、周波数領域フィルタ係数Ｗ’は、更新するたびにメモリを上書きすればよいので、フレーム番号を示すｋを持たなくてもよい。 The filter update unit 890 updates the frequency domain filter coefficient W using the product of each complex conjugate of the frequency domain reproduction signal X ′ (k) and the frequency domain residual echo E ′ (k). Specifically, according to the FBLMS algorithm described in Non-Patent Document 1,

Update as. Here, W ⁻ ′ is a frequency domain filter coefficient before overwriting the memory, and P is a constraint matrix. The update vector ΔW ′ is, for each element ΔW ′ _{m ′} , for example,

Calculate as Here, μ is a step size, * is a conjugate complex number, and P [, γ] is an average process of γ frames. Note that the frequency domain filter coefficient W ′ does not have to indicate k indicating the frame number because the memory may be overwritten every time it is updated.

  Since the echo canceller 800 operates in this way, when the mounting delay can be ignored (FIG. 2), a delay of two frames occurs. When there is a mounting delay for one frame (FIG. 3), a delay for four frames occurs.

  The present invention intends to reduce the amount of calculation by actively using a delay time caused by an algorithm delay or an implementation delay, and an embodiment thereof will be described below.

  FIG. 4 shows a functional configuration example of an acoustic reproduction system using the echo canceller of the present invention. First serial / parallel converter 910, first parallel / serial converter 920, acoustic signal reproduction unit (speaker) 930, acoustic signal sound collection unit (microphone) 950, second serial / parallel converter 960, second parallel / The serial conversion unit 970 is the same as the conventional sound reproduction system (FIG. 1). FIG. 5 shows a processing flow of the echo canceling apparatus of the present invention. In FIG. 6, the algorithm delay (the delay in the first serial / parallel converter 910 and the second serial / parallel converter 960) in the sound reproduction system in FIG. 4 is one frame, and the implementation delay (first The time chart when the delay in the parallel / serial conversion unit 920 and the second parallel / serial conversion unit 970 is negligible is shown. FIG. 7 shows that the algorithm delay in the sound reproduction system of FIG. 4 (the delay in the first serial / parallel converter 910 and the second serial / parallel converter 960) is one frame, and the implementation delay (first parallel / parallel). The time chart when the delay in the serial conversion unit 920 and the second parallel / serial conversion unit 970) is for one frame is shown. In the figure, the algorithm delay is represented by a two-dot chain line, and the implementation delay is represented by a one-dot chain line.

The first serial / parallel converter 910 includes N time-series reproduction signals x (kN−N + 1),..., X (kN) (one frame is composed of N reproduction signals x (n)). , X (kN)} ^T is generated, with the reproduction signal vector x _N (k) = {x (kN−N + 1),. However, N is an integer greater than or equal to 2, for example 128. K is a number indicating the frame number. At this time, an algorithm delay of one frame always occurs.

  The echo cancellation apparatus 100 includes a first vector increasing unit 110, a first frequency analyzing unit 120, an integrating unit 130, a frequency synthesizing unit 140, a vector decreasing unit 150, a subtracting unit 160, a second vector increasing unit 170, and a second frequency analyzing unit. 180 and a filter update unit 190. For example, the echo canceling apparatus 100 confirms that a reproduction signal x (1),..., X (N) (one frame is composed of N reproduction signals x (n)) is input. Then, the process starts when the reproduction signal x (n) is input, repeats the process while the reproduction signal x (n) is input, and ends when the reproduction signal x (n) is not input ( S105).

The first vector increase unit 110 receives a reproduction signal vector x _N (k) having _N time-series reproduction signals x (n) as elements, and reproduces K pieces (where K is an integer of 2 or more). A reproduction signal increase vector x _M (k) including M elements (where M is an integer equal to or greater than KN) including each element of the signal vector x _N (k),..., X _N (k + K−1) is output. (S110). For example, M = KN + L. However, L is the filter length (the number of taps) of the time domain corresponding filter, for example, 1664. FIG. 6 shows an example of K = 2, and FIG. 7 shows an example of K = 3. For example, in the case of K = 2 (FIG. 6), 2N pieces of data (elements) are discarded in the order of the oldest time of x _M (k−2) and connected to x _N (k) and x _N (k + 1). Thus, x _M (k) is obtained. In the case of K = 3 (FIG. 7), 3N pieces of data (elements) are discarded in the order of the oldest time of x _M (k-3), and x _N (k), x _N (k + 1), x _N (k + 2) ) To obtain x _M (k).

のように、計算する。 The first frequency analysis unit 120 performs frequency conversion on the reproduction signal increase vector x _M (k), and a frequency domain reproduction signal X having M frequency components X _m (k) (where m = 1,..., M). (K) is output (S120). The integrating unit 130 integrates the frequency domain reproduction signal X (k) and the frequency domain filter coefficient W, and outputs a frequency domain pseudo echo D ^ (k) (S130). In particular,

Calculate as follows.

として出力し、Ｋ＝３（図７）の場合は、

として出力すればよい。なお、ｃ_Ｌのｃは直線上畳み込みにあたらない値を、添え字Ｌは要素数を示しており、ｃ_ＬはＬ個の直線上畳み込みにあたらない値を要素とするベクトルを示している。 The frequency synthesizer 140 converts the frequency domain pseudo echo D ^ (k) into the time domain, and outputs a pseudo echo increase vector d ^ _M (k) composed of M elements (S140). Note that the pseudo echo increase vector d ^ _M (k) is K = 2 (FIG. 6),

When K = 3 (FIG. 7),

As output. Incidentally, c of c _L shows the vector values not exposed on a straight line convolution, subscript L denotes the number of elements, c _L is composed of the elements of value not exposed to the convolution on the L line.

The vector reduction unit 150 generates pseudo echo vectors d ^ _N (k),..., D ^ _N (k + K−1) including K N elements from the pseudo echo increase vector d ^ _M (k). One pseudo echo vector is output at each timing when the sound signal vector y _N (k) is input (S150). For example, when the pseudo echo increase vector d ^ _M (k) shown in Expression (5) or Expression (6) is input, the pseudo echo increase vector d ^ _M (k) is pseudo-coded from the last KN elements. The echo vector d ^ _N (k), ..., d ^ _N (k + K-1) may be generated.

The first parallel / serial converter 920 converts the reproduction signal vector x _N (k) into reproduction signals x (1),..., X (N). When the mounting delay can be ignored (FIG. 6), the reproduction signal x (n) is sequentially output at a predetermined interval (for example, 10 ms) without delay, and is reproduced via the acoustic signal reproduction unit 930. When there is a mounting delay of one frame (FIG. 7), after the delay of one frame, the reproduction signal x (n) is sequentially output at a predetermined interval and reproduced via the acoustic signal reproduction unit 930. The second serial / parallel converter 960 has a sound collection signal vector y _N (k) = {y (kN−N + 1) having N time-series sound collection signals y (1),..., Y (N) as elements. ,..., Y (kN)} ^T is generated. At this time, an algorithm delay of one frame always occurs.

The subtracting unit 160 subtracts the collected sound signal vector y _N (k) and the pseudo echo vector d ^ _N (k), and the residual echo vector e _N (k) = y _N (k) −d ^ _N (k ) Is output (S160). The second parallel / serial converter 970 converts the residual echo vector e _N (k) into residual echo signals e (1),..., E (N). When the mounting delay can be ignored (FIG. 6), the residual echo signal e (n) is sequentially output at a predetermined interval without delay. When there is a mounting delay of one frame (FIG. 7), the residual echo signal e (n) is sequentially output at a predetermined interval after a delay of one frame.

として出力し、Ｋ＝３（図７）の場合は、

として出力すればよい。なお、０_ＬはＬ個の“０”を要素とするベクトルを示している。 The second vector increase unit 170 generates a residual echo increase vector e _M (k) composed of M elements including each element of K residual echo vectors e _N (k),..., E _N (k + K−1). Output (S170). For example, M = KN + L. The residual echo increase vector e _M (k) is K = 2 (FIG. 6),

When K = 3 (FIG. 7),

As output. Note that 0 _L indicates a vector having L “0” elements.

として更新する。ここで、Ｗ⁻はメモリを上書きする前の周波数領域フィルタ係数、Ｐは拘束行列である。更新ベクトルΔＷは、要素ΔＷ_ｍごとに、例えば、

として計算する。ここで、μはステップサイズ、＊は共役複素数、Ｐ［，γ］はγフレームの平均処理を示す。なお、周波数領域フィルタ係数Ｗは、更新するたびにメモリを上書きすればよいので、フレーム番号を示すｋを持たなくてもよい。 The second frequency analysis unit 180 frequency-converts the residual echo increase vector e _M (k) and outputs a frequency domain residual echo E (k) (S180). The filter update unit 190 updates the frequency domain filter coefficient W by using the product of each element of the complex conjugate of the frequency domain reproduction signal X (k) and the frequency domain residual echo E (k) (S190). Specifically, by the FBLMS algorithm etc.

Update as. Here, W ⁻ is a frequency domain filter coefficient before overwriting the memory, and P is a constraint matrix. The update vector ΔW is for each element ΔW _m , for example:

Calculate as Here, μ is a step size, * is a conjugate complex number, and P [, γ] is an average process of γ frames. Since the frequency domain filter coefficient W only needs to overwrite the memory each time it is updated, it does not need to have k indicating the frame number.

  Since the echo cancellation apparatus 100 operates in this way, when the mounting delay can be ignored (FIG. 6), a delay of two frames occurs. When there is a mounting delay for one frame (FIG. 7), a delay for four frames occurs. These delays are the same as the delays shown in FIGS. On the other hand, the echo canceller 100 performs frequency analysis and frequency synthesis on K frames together, thereby setting the number of frequency analysis points per K frame to M (for example, M = KN + L). Therefore, when M = KN + L, the number of frequency analysis points per frame is N + L / K. When N = 128, L = 1664, and K = 2 as compared to the conventional N + L = 1789, N + L / K = 960. Further, when N = 128, L = 1664, and K = 3, N + L / K = 682.66. That is, when K = 2, the calculation amount can be reduced to about ½, and when K = 3, the calculation amount can be reduced to about ３.

  FIG. 8 shows the relationship between the value of K when the mounting delay is negligible, the delay amount due to the algorithm delay, and the calculation amount. FIG. 9 shows the relationship between the value of K when there is a mounting delay of one frame, the amount of delay due to the algorithm delay, and the amount of computation. In both figures, the case of K = 1 corresponds to the conventional case. As can be seen from these figures, when the mounting delay is negligible (FIG. 8), when K = 2, when there is a mounting delay of one frame (FIG. 9), K = 2 and K = 3. In this case, the delay is the same as before. If the value of K is increased, the amount of delay can be increased but the amount of computation can be reduced. That is, the echo canceller of the present invention can reduce the amount of calculation while suppressing delay (or the same as the conventional one).

[Modification]
Note that the features of the echo canceller 100 can also be expressed as follows. The first frequency analysis unit 120, the integration unit 130, the frequency synthesis unit 140, the second vector increase unit 170, the second frequency analysis unit 180, and the filter update unit 190 are collectively referred to as a pseudo echo increase vector calculation unit 115. Then, the echo cancellation apparatus 100 includes a first vector increase unit 110, a pseudo echo increase vector calculation unit 115, a vector decrease unit 150, and a subtraction unit 160. Then, the first vector increasing unit 110 includes M elements (where K is an integer equal to or greater than 2) including each element of the reproduction signal vectors x _N (k),..., X _N (k + K−1). , M is an integer greater than or equal to KN) to obtain a reproduction signal increase vector x _M (k). The pseudo echo increase vector calculation unit 115 obtains a pseudo echo increase vector d ^ _M (k) composed of M elements by calculating in the frequency domain the reproduction signal increase vector x _M (k). The vector reduction unit 150 generates pseudo echo vectors d ^ _N (k),..., D ^ _N (k + K-1) including K N elements from the pseudo echo increase vector d ^ _M (k). The subtracting unit 160 subtracts the collected sound signal vector y _N (k) and the pseudo echo vector d ^ _N (k), and the residual echo vector e _N (k) = y _N (k) −d ^ _N (k ) Is output.

  In this modification, the process of the pseudo echo increase vector calculation unit 115 is not limited to the method of the first embodiment. However, even in the echo processing apparatus according to this modification, the amount of calculation can be reduced by collecting signals using the delay time originally generated.

  FIG. 10 shows a functional configuration example of the computer. The above-described embodiment can be implemented by causing the recording unit 2020 of the computer shown in FIG. 10 to read a program that causes a computer to execute as the above-described device and cause the control unit 2010, the input unit 2030, and the output unit 2040 to operate. In addition, as a method of causing the computer to read, the program is recorded on a computer-readable recording medium, and the program recorded on the server or the like is read into the computer through a telecommunication line or the like. There is a method to make it.

The figure which shows the function structural example of the sound reproduction type | system | group using the conventional echo cancellation apparatus. The figure which shows the time chart in case the algorithm delay in the sound reproduction system of FIG. 1 is one frame, and a mounting delay can be disregarded. The figure which shows the time chart in case the algorithm delay in the sound reproduction system of FIG. 1 is for 1 frame, and the mounting delay is for 1 frame. The figure which shows the function structural example of the sound reproduction system using the echo cancellation apparatus of this invention. The figure which shows the processing flow of the echo cancellation apparatus of this invention. The figure which shows the time chart in case the algorithm delay in the sound reproduction system of FIG. 4 is one frame, and a mounting delay can be disregarded. The figure which shows the time chart in case the algorithm delay in the sound reproduction system of FIG. 4 is one frame, and a mounting delay is one frame. The figure which shows the relationship between the value of K in case a mounting delay can be disregarded, the delay amount by algorithm delay, and the amount of calculations. The figure which shows the relationship between the value of K in case there exists mounting delay for 1 frame, the amount of delay by algorithm delay, and the amount of calculations. The figure which shows the function structural example of a computer.

Explanation of symbols

100, 800 Echo canceller 110, 810 First vector increase unit 115 Pseudo echo increase vector calculation unit 120, 820 First frequency analysis unit 130, 830 Accumulation unit 140, 840 Frequency synthesis unit 150, 850 Vector decrease unit 160, 860 Subtraction Units 170 and 870 Second vector increase unit 180 and 880 Second frequency analysis unit 190 and 890 Filter update unit 910 First serial / parallel conversion unit 920 First parallel / serial conversion unit 930 Acoustic signal reproduction unit 940 Echo path 950 Acoustic signal Sound collecting unit 960 Second serial / parallel converter 970 Second parallel / serial converter

Claims (6)

A reproduction signal vector having N (where N is an integer of 2 or more) time-series reproduction signals (one frame) as inputs is input, and K (where K is an integer of 2 or more) reproduction signal vectors. M pieces containing each element (where, M is larger integer than K N) and the first vector increasing unit for outputting a reproduced signal increase vector of elements,
A first frequency analysis unit that frequency-converts the reproduction signal increase vector and outputs a frequency domain reproduction signal;
An integration unit that integrates the frequency domain reproduction signal and the frequency domain filter coefficient and outputs a frequency domain pseudo echo;
A frequency synthesizer that converts the frequency domain pseudo echo to the time domain and outputs a pseudo echo increase vector composed of M elements;
At each timing when K pseudo echo vectors composed of N elements are generated from the pseudo echo increase vector, and a sound collection signal vector having N time series sound collection signals (one frame) as elements is input. A vector reduction unit for outputting the pseudo echo vectors one by one;
Subtracting the sound collection signal vector and the pseudo echo vector, and outputting a residual echo vector;
A second vector increase unit for outputting a residual echo increase vector composed of M elements including each element of the K residual echo vectors;
A second frequency analysis unit that frequency-converts the residual echo increase vector and outputs a frequency domain residual echo;
A filter update unit that updates the frequency domain filter coefficient using a product of each complex conjugate of the frequency domain reproduction signal and the frequency domain residual echo;
An echo canceller comprising: Reproduction signal vector having N (where N is an integer of 2 or more) time-series reproduction signals (one frame) and sound collection having N time-series sound collection signals (one frame) as elements An echo canceling device that receives a signal vector as input and cancels an echo component of the reproduced signal vector included in the collected sound signal vector using a pseudo echo vector generated from the reproduced signal vector,
The K (where, K is an integer of 2 or more) M number (where, M is larger integer than K N) containing each element of the reproduced signal vector of the first vector increasing portion for obtaining a reproduced signal increase vector of elements of When,
A pseudo echo increase vector calculation unit for obtaining a pseudo echo increase vector composed of M elements by calculation in the frequency domain with respect to the reproduction signal increase vector;
A vector reduction unit for generating K pseudo echo vectors composed of N elements from the pseudo echo increase vector;
A subtraction unit that performs subtraction between the collected sound signal vector and the pseudo echo vector and outputs a residual echo vector in which an echo component of the reproduction signal vector included in the collected sound signal vector is deleted;
An echo canceling device comprising: A reproduction signal vector having N (where N is an integer of 2 or more) time-series reproduction signals (one frame) as inputs is input, and K (where K is an integer of 2 or more) reproduction signal vectors. M pieces containing each element (where, M is larger integer than K N) and the first vector increasing step of outputting a reproduction signal increases vector of elements,
A first frequency analysis step of frequency-converting the reproduction signal increase vector and outputting a frequency domain reproduction signal;
Integrating the frequency domain reproduction signal and the frequency domain filter coefficient, and outputting a frequency domain pseudo echo; and
A frequency synthesis step of converting the frequency domain pseudo echo into the time domain and outputting a pseudo echo increase vector composed of M elements;
At each timing when K pseudo echo vectors composed of N elements are generated from the pseudo echo increase vector, and a sound collection signal vector having N time series sound collection signals (one frame) as elements is input. A vector reduction step of outputting the pseudo echo vectors one by one;
Subtracting the sound pickup signal vector and the pseudo echo vector to output a residual echo vector;
A second vector increasing step of outputting a residual echo increase vector composed of M elements including each element of the K residual echo vectors;
A second frequency analysis step of frequency-converting the residual echo increase vector and outputting a frequency domain residual echo;
An echo canceling method comprising: a filter updating step of updating the frequency domain filter coefficient using a product of each complex conjugate of the frequency domain reproduction signal and the frequency domain residual echo. Reproduction signal vector having N (where N is an integer of 2 or more) time-series reproduction signals (one frame) and sound collection having N time-series sound collection signals (one frame) as elements An echo canceling method for canceling an echo component of the reproduced signal vector included in the collected sound signal vector using a pseudo echo vector generated from the reproduced signal vector, the signal vector being an input,
The K (where, K is an integer of 2 or more) M number (where, M is larger integer than K N) first vector increases step of obtaining a reproduced signal increase vector of elements including the elements of the reproduction signal vector When,
A pseudo echo increase vector calculating step for obtaining a pseudo echo increase vector composed of M elements by an operation in a frequency domain with respect to the reproduction signal increase vector;
A vector reduction step of generating K pseudo echo vectors composed of N elements from the pseudo echo increase vector;
Subtracting the sound pickup signal vector from the pseudo echo vector and outputting a residual echo vector from which an echo component of the reproduction signal vector included in the sound pickup signal vector is eliminated. Echo cancellation method.   An echo cancellation program for operating a computer as the echo cancellation apparatus according to claim 1.   A computer-readable recording medium on which the echo cancellation program according to claim 5 is recorded.

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