JP4736628B2 - Radio receiving apparatus and radio receiving method - Google Patents

Description

  The present invention relates to a radio reception apparatus and a radio reception method for receiving radio signals for ultra-wideband communication.

  In recent years, as one of high-speed wireless transmission systems, an ultra wide band (UWB) communication system that performs ultra-wideband communication using a pulse signal sequence composed of pulse signals synchronized with a predetermined cycle timing has attracted attention. Yes. As one aspect of UWB communication, there is known one in which communication is performed using a pulse signal sequence made up of extremely fine pulse signals such as a pulse width of 1 nsec or less without using a carrier wave (see, for example, Patent Document 1). ).

  FIG. 6 is a block diagram showing a UWB communication radio receiving apparatus 100 according to the background art. A radio reception apparatus 100 illustrated in FIG. 6 includes an antenna 101 that receives a UWB communication signal transmitted from a radio transmission apparatus using UWB communication, an amplifier 102 that amplifies the UWB communication signal received by the antenna 101, and a control unit 105. An integrated voltage Sz indicating the correlation between the template signal Sx and the signal Sy is generated by integrating the signal Sy amplified by the amplifier 102 based on the template signal Sx indicating a predetermined timing in time series output from The integration circuit 103, the AD converter 104 that converts the integration voltage Sz into a digital value, and the template signal Sx is output to the integration circuit 103 in synchronization with the UWB communication signal based on the correlation value obtained by the AD converter 104. And a control unit 105 that demodulates data from the correlation value obtained by the AD converter 104.

  The radio receiving apparatus 100 configured as described above receives the transmitted pulse signal and the radio receiving apparatus 100 side in order to receive the UWB communication pulse signal arranged on the time axis in synchronization with a predetermined cycle timing. It is necessary to perform pulse synchronization that synchronizes the reception timing, that is, the timing of the template signal Sx.

  FIG. 7 is an explanatory diagram for explaining the pulse synchronization processing according to the background art. First, as shown in FIG. 7, the communication frame of UWB communication includes pulses P1 for establishing pulse synchronization at a constant period, for example, 200 nsec. The template signal Sx is configured to include a rectangular wave pulse indicating a window period during which the integrating circuit 103 performs an integrating operation.

  The radio reception apparatus 100 receives a UWB communication frame only during a predetermined period, for example, a 10 nsec window period, and gradually sets the timing of the window period, for example, 10 nsec, until the pulse P1 is received within the window period. The timing of the pulse P1 is searched while shifting. When the pulse P1 is received within the window period, the timing of the window period is acquired as the pulse synchronization timing.

Further, the period timing of the rectangular wave pulse indicating the window period in the template signal Sx is synchronized with the pulse synchronization timing acquired in this way, and thereafter the reception period is synchronized with the period timing generated by the control unit 105. By performing the above, the pulse signal arranged on the time axis is received in synchronization with the cycle timing generated on the transmission device side by taking the pulse synchronization.
Japanese National Patent Publication No. 10-508725

  By the way, in the wireless reception device 100 as described above, the accuracy variation of the timing generation circuit that generates the cycle timing of the pulse signal on the transmission device side, and the accuracy variation of the control unit 105 that generates the reception cycle timing on the wireless reception device 100 side. As a result, there is a case in which there is a difference in cycle timing between the transmission device side and the wireless reception device 100 side, and even if pulse synchronization is performed once, the shift in cycle timing increases with time and synchronization may not be achieved. As described above, when synchronization cannot be achieved due to a shift in cycle timing after synchronization is achieved, if a plurality of integration circuits 103 are provided to provide a plurality of window periods, the timing of the pulse P1 is shifted after synchronization is achieved. Even in this case, if any of the plurality of window periods is synchronized with the pulse P1, the pulse P1 can be detected, so that it is considered easy to maintain the synchronization.

  However, when a plurality of integrating circuits 103 are provided, there is a disadvantage that the circuit scale increases and the power consumption increases.

  The present invention has been made in view of such a problem, and an object thereof is to provide a wireless reception device and a wireless reception method that can reduce power consumption while including a plurality of integration circuits. .

  In order to achieve the above-described object, a radio reception apparatus according to the first means of the present invention includes a reception unit that receives a radio signal having a pulse at a predetermined cycle, and a signal received by the reception unit. A plurality of integration circuits that integrate each of a plurality of integration periods that are different periods in a cycle, a power supply unit that supplies a power supply voltage for operation to the plurality of integration circuits, and the plurality of integration circuits The pulse timing at which the pulse is received by the receiving unit is acquired based on the integration value obtained by the step, and a synchronization integration period that is a partial integration period in the plurality of integration periods is acquired with the acquired pulse timing A synchronizing unit that synchronizes, and the synchronizing integration period and the pulse timing are synchronized by the synchronizing unit, and then the synchronizing integration period of the plurality of integrating circuits The power supply control unit for stopping the supply of the power supply voltage by the power supply unit to other integration circuits excluding the integration circuit that performs the integration, and the integration circuit that performs the integration for the synchronization integration period. And a demodulator that demodulates the radio signal based on the integrated value.

  In the above wireless receiver, the power supply unit supplies a power supply voltage for operation to the plurality of integration circuits in accordance with each integration period.

  The wireless reception apparatus further includes a shift direction detection unit that detects a shift direction of the pulse timing, and the power supply control unit synchronizes the synchronization integration period and the pulse timing by the synchronization unit. After that, among the plurality of integration circuits, other integrations except the integration circuit that performs the integration for the integration period in the shift direction detected by the shift direction detection unit than the synchronization integration period and the synchronization integration period. The power supply by the power supply unit to the circuit is stopped.

  Further, in the above-described wireless reception device, the shift direction detection unit includes an integration value obtained by a delay integration circuit that performs the integration for a delay integration period positioned at a timing delayed from the synchronization integration period, and the synchronization The shift direction of the pulse timing is detected based on the integration value obtained by the advance integration circuit that performs the integration for the advance integration period positioned at the timing advanced from the integration period.

  Further, in the above-described wireless reception device, the synchronization unit sets a part of the integration periods so as to overlap each other with an integration period adjacent to each other, and the part of the plurality of integration periods Are set as the synchronization integration period, and the integration period as the synchronization integration period is changed according to the change in the pulse timing, thereby changing the pulse timing and the synchronization integration period. The power supply control unit maintains the synchronization, and the integration value obtained by the two integration circuits that perform the integration for the two integration periods becomes substantially equal to the two integration periods. Supply of the power supply voltage by the power supply unit to the integration circuit that performs the integration for the integration period in the shift direction detected by the shift direction detection unit. It is characterized in that to perform.

  In the above wireless receiver, the signal received by the receiving unit is filtered and output to the plurality of integrating circuits, and the frequency band to be filtered can be switched, and the pulse timing by the synchronizing unit A time-counting unit that counts the time during which the time is not acquired, and a band switching unit that changes a frequency band of the band-pass filter when the time measured by the time-measurement unit exceeds a preset reference time, The integration circuit is characterized by integrating the signal output from the bandpass filter.

  And the radio reception method according to the second means of the present invention includes a step of receiving a radio signal having a pulse at a predetermined period and a difference between the received signals using a plurality of integration circuits in the period. A step of integrating each of a plurality of integration periods as a part of the period, a step of supplying a power supply voltage for operation to the plurality of integration circuits, and an integration value obtained by the plurality of integration circuits. Acquiring a pulse timing at which the pulse is received and synchronizing a synchronization integration period, which is a partial integration period in the plurality of integration periods, with the acquired pulse timing; and the synchronization integration period and the pulse After synchronizing with the timing, the power supply power to the other integration circuits other than the integration circuit that performs the integration for the synchronization integration period among the plurality of integration circuits. A step of stopping the supply of, is characterized in that based on the integrated value obtained by the integration circuit performs the integral for the synchronous integration period and a step of performing demodulation of the radio signal.

  In the wireless reception device and the wireless reception method configured as described above, a wireless signal having a pulse at a predetermined cycle is received, and the signal is a plurality of different periods in the cycle using a plurality of integration circuits. Each integration period is integrated. Based on the integration values obtained by the plurality of integration circuits, the pulse timing at which the pulse is received is acquired, and the synchronization integration period, which is a partial integration period in the plurality of integration periods, is acquired. Synchronized with. Furthermore, after the synchronization integration period and the pulse timing are synchronized, supply of power supply voltage to the other integration circuits other than the integration circuit that performs integration for the synchronization integration period is stopped among the plurality of integration circuits, and the synchronization Since the radio signal is demodulated based on the integration value obtained by the integration circuit that performs integration during the integration period, other integration circuits except for the integration circuit that performs integration for the synchronization integration period while having a plurality of integration circuits Power consumption can be reduced.

  Embodiments according to the present invention will be described below with reference to the drawings. In addition, the structure which attached | subjected the same code | symbol in each figure shows that it is the same structure, The description is abbreviate | omitted.

(First embodiment)
FIG. 1 is a block diagram illustrating an example of a configuration of a wireless reception device using a wireless reception method according to the first embodiment of the present invention. 1 includes an antenna 2 (reception unit), an amplifier 3, a filter 4 (band filter), a detector 5, integration blocks 6-1 to 6-n, a signal processing unit 8, and a gate signal generation unit. 9, a phase control unit 10 and a power supply unit 11.

  The antenna 2 is a receiving antenna that receives an ultra-wideband radio signal. The amplifier 3 is an amplifier circuit that amplifies the signal received by the antenna 2. The filter 4 is a band filter for filtering the output signal of the amplifier 3, and the pass band can be switched between 3.1 GHz and 3.5 GHz according to the control signal from the signal processing unit 8. The detector 5 detects the output signal of the filter 4 and outputs it to the integration blocks 6-1 to 6-n as the detection signal K1. By the antenna 2, the amplifier 3, the filter 4, and the detector 5, the signal of the 3.2 GHz band received by the antenna 2 is envelope-detected, frequency-converted to about 500 MHz, and pulse demodulated. Yes.

  The integration blocks 6-1 to 6-n integrate the detection signal K1 output from the detector 5, and output the integration signals 61-1 to 61-n as the integration signals S1 to Sn, and the integration circuits 61-1 to 61-1. AD converters 62-1 to 62-n that convert the integration signals S1 to Sn output from 61-n into digital values and output the signals as signals AD1 to ADn are provided. The AD converters 62-1 to 62-n are, for example, 8-bit, 255-stage AD converters. Hereinafter, when referring generically, it shows with the reference symbol which abbreviate | omitted the suffix, and when referring to an individual structure, it shows with the reference symbol which attached the suffix.

  The gate signal generation unit 9 is configured to include, for example, an oscillation circuit, and in order to cause the integration circuits 61-1 to 61-n to perform an integration operation at the same cycle as the cycle of the radio signal pulse in ultra-wideband communication. The circuit unit outputs a reference gate signal G indicating an integration period, that is, a window period, every t1.

  The phase control unit 10 converts the phase of the reference gate signal G based on the reference gate signal G output from the gate signal generation unit 9 and the control signal from the signal processing unit 8 to the integration circuits 61-1 to 61-n. Are changed to indicate the timing of the integration operation, and are output to the integration circuits 61-1 and 61-2 to 61-n as gate signals G1, G2 to Gn, respectively. Based on the reference gate signal G output from the gate signal generation unit 9 and the control signal from the signal processing unit 8, the power supply unit 11 integrates the integration blocks 6-1 to 6-n, that is, the integration circuits 61-1 to 61-1. A circuit unit that supplies power supply voltages E1 to En for operation to 61-n and AD converters 62-1 to 62-n, respectively, and is configured using a switching element such as a transistor.

  The signal processing unit 8 includes, for example, a CPU (Central Processing Unit) that executes predetermined arithmetic processing, a ROM (Read Only Memory) that stores a predetermined control program, and a RAM (Random Access Memory) that temporarily stores data. ), A timer circuit, peripheral circuits, and the like, and based on the output signals AD1 to ADn of the AD converters 62-1 to 62-n by executing a control program stored in the ROM An initial synchronization unit 81 that acquires and synchronizes the pulse synchronization timing with the reception pulse, a synchronization maintenance unit 82 that maintains synchronization with the reception pulse, and a reception signal based on the output signals of the AD converters 62-1 and 62-2 The time when the pulse synchronization timing is not acquired by the demodulator 83 which demodulates the data from the data and outputs the data Dout to the outside, for example, the timer circuit, for example, using the timer circuit When the time measured by the time measuring unit 84 and the time measured by the time measuring unit 84 exceed a preset reference time, the operation of the band switching unit 85 that changes the frequency band of the filter 4 and the operation of the power supply unit 11 are performed. It functions as a power supply control unit 86 for controlling.

  Next, the operation of the wireless reception device 1 configured as described above will be described. First, in the initial state where the reception of the radio signal in the ultra-wideband communication by the antenna 2 is started, the timing of the radio signal pulse in the ultra-wideband communication received by the antenna 2 and the reception timing in the radio receiver 1 are synchronized. Therefore, first, the initial synchronization unit 81 performs initial synchronization processing for acquiring the pulse timing at which the radio signal pulse is received by the antenna 2 as the pulse synchronization timing.

  First, an initial synchronization process using two integration blocks 6-1 and 6-2 will be described. FIG. 2A is a signal waveform diagram for explaining the initial synchronization processing by the initial synchronization unit 81. In FIG. 2A, the detection signal K1 output from the detector 5 includes a pulse P every period t2, which is a pulse transmission period in the transmission apparatus for ultra-wideband communication. The gate signal G1 is a signal that causes the integration circuit 61-1 to perform an integration operation at a high level, and the gate signal G2 is a signal that causes the integration circuit 61-2 to perform an integration operation at a high level.

  As shown in FIG. 2A, in the initial state, the timing of the pulse P in the detection signal K1, the integration period ts1 when the gate signal G1 is at the high level, and the timing when the gate signal G2 is at the high level. It does not coincide with a certain integration period ts2, and the pulse is not synchronized. Therefore, for example, as shown in FIG. 2A, the timing of the integration period ts1 in the gate signal G1 is gradually changed in the delay direction by the phase control unit 10 according to the control signal from the initial synchronization unit 81. The timing at which the output signal AD1 of the converter 62-1 increases is searched, and the timing of the integration period ts2 in the gate signal G2 is gradually changed in the direction opposite to the integration period ts1, and the output of the AD converter 62-2. The timing at which the signal AD2 increases is searched.

  Further, when the output signal AD1 increases, the initial synchronization unit 81 acquires the timing of the integration period ts1 from which the output signal AD1 was obtained as the pulse synchronization timing, and when the output signal AD2 increases, the output signal AD2 is The timing of the obtained integration period ts2 is acquired as the pulse synchronization timing.

  In this case, the initial synchronization unit 81 sets a timing at which the integration period ts1 and the integration period ts2 do not overlap each other, and changes the timing of the integration period ts1 and the integration period ts2 according to one of the output signal AD1 and the output signal AD2. Since the timing at which the obtained integral value increases is searched and the timing at which the integral value increases is acquired as the pulse synchronization timing, the pulse synchronization timing can be searched using two integration periods, as shown in FIG. Compared to the case of searching for the pulse synchronization timing while shifting one window period as in the case of the pulse synchronization processing according to the background art, the processing time of the initial synchronization processing can be reduced to about ½.

  In the initial synchronization processing, the example in which the pulse synchronization timing is searched by changing the timings of the integration period ts1 and the integration period ts2 using the integration blocks 6-1 and 6-2 has been shown. The pulse synchronization timing may be searched by changing the timing of n integration periods using the integration blocks 6-1 to 6-n. In this case, the processing time of the initial synchronization processing is reduced to about 1 / n compared to the case of searching for the pulse synchronization timing while shifting one window period as in the case of the pulse synchronization processing according to the background art shown in FIG. be able to.

  Then, as shown in FIG. 2B, in response to the control signal from the initial synchronization unit 81, the phase control unit 10 acquires the timing of the integration period ts1 in the gate signal G1 as the pulse synchronization timing, that is, Synchronized with the timing of the pulse P. Thereby, the pulse P is integrated by the integration circuit 61-1, and the integration signal S1 increases. The operation of the gate signal G2 and the integration signal S2 shown in FIG. 2B will be described later.

  Next, operations of the synchronization maintaining unit 82 (synchronizing unit) and the power supply control unit 86 will be described. FIG. 3 is a timing chart for explaining operations of the synchronization maintaining unit 82 and the power supply control unit 86. In the present embodiment, the signal waveforms of the gate signals G1 and G2 and the voltage waveforms of the power supply voltages E1 and E2 are the same. Therefore, in FIG. 3, the gate signal G1, the power supply voltage E1, and the gate signal G2 The waveform of the power supply voltage E2 is shared by the same waveform.

  First, the pulse synchronization timing is acquired by the initial synchronization unit 81. As shown in FIG. 3A, the timing of the pulse P and the timing of the integration period ts1 in the gate signal G1 are synchronized. In response to the control signal, the phase control unit 10 sets the integration period ts2 to be continuous with the integration period ts1. In this case, the integration periods ts1 and ts2, which are partial integration periods in the plurality of integration periods ts1 to tsn of the plurality of integration circuits 61-1 to 61-n, correspond to synchronization integration periods used for maintaining synchronization. is doing.

  Here, the pulse period t2 in the radio transmission apparatus and the period t1 of the reference gate signal G generated by the gate signal generation unit 9 are set to be basically the same, but the oscillation circuit in the radio transmission apparatus, etc. There may be a difference between the pulse period t1 and the pulse period t2 due to variations in accuracy between the generation circuit of the pulse period t2 and the generation circuit of the pulse period t1 such as the oscillation circuit in the gate signal generation unit 9. Then, for example, when the pulse period t2 is longer than the pulse period t1, the timing of the pulse P is delayed with respect to the timing of the integration period ts1 in the gate signal G1, while the pulse period t2 is shorter than the pulse period t1, for example. In this case, the timing of the pulse P advances with respect to the timing of the integration period ts1 in the gate signal G1, and in any case, the deviation of the cycle timing increases with the passage of time, and the synchronization cannot be achieved as it is.

  Therefore, in the wireless reception device 1, the synchronization maintaining unit 82 converts the signal AD1 indicating the integral value obtained by the AD converter 62-1 and the signal AD2 indicating the integral value obtained by the AD converter 62-2. Based on this, the timing of the integration period ts1 in the gate signal G1 is adjusted to be synchronized with the timing of the pulse P, and synchronization is maintained.

  Specifically, for example, when the pulse period t2 is longer than the pulse period t1, as shown by the arrow A in FIG. 3A, the timing of the pulse P with respect to the timing of the integration period ts1 in the gate signal G1. Is delayed. Then, as shown in FIG. 3B, the level of the integration signal S1 of the AD converter 62-1 decreases and the integration value indicated by the signal AD1 decreases, while the integration signal S2 of the AD converter 62-2 decreases. And the integral value indicated by the signal AD2 increases.

  Then, the synchronization maintaining unit 82 compares the integral value indicated by the signal AD1 and the integral value indicated by the signal AD2, and when the integral value indicated by the signal AD2 becomes larger, the timing of the pulse P is changed. Judged to be late. Further, as shown in FIG. 3C, in response to the control signal from the synchronization maintaining unit 82, the phase control unit 10 causes the timing of the integration period ts1 in the gate signal G1 to be in the direction of the integration period ts2, that is, the delay direction. Changed.

  As a result, the timing of the integration period ts1 in the gate signal G1 is again synchronized with the timing of the pulse P, and pulse synchronization is maintained.

  On the other hand, for example, when the pulse period t2 is shorter than the pulse period t1, the timing of the pulse P advances with respect to the timing of the integration period ts1 in the gate signal G1. As a result, the level of the integration signal S2 of the AD converter 62-1 does not change, and therefore the level of the integration signal S1 of the AD converter 62-1 decreases without increasing the integration value indicated by the signal AD2. The integral value indicated by AD1 decreases.

  When the synchronization maintaining unit 82 detects that the integral value indicated by the signal AD1 decreases without increasing the integral value indicated by the signal AD2, for example, falls below a preset threshold, the pulse P It is determined that the timing has advanced, and the timing of the integration period ts1 in the gate signal G1 is changed in the opposite direction to the integration period ts2, that is, in the advance direction by the phase control unit 10 in accordance with the control signal from the synchronization maintaining unit 82. The

  As a result, the timing of the integration period ts1 in the gate signal G1 is again synchronized with the timing of the pulse P, and pulse synchronization is maintained.

  On the other hand, during the operation of maintaining the pulse synchronization as described above, the integration blocks 6-1 and 6 that perform integration for the integration periods ts1 and ts2 by the power supply unit 11 according to the control signal from the power supply control unit 86. The supply of the power supply voltages E3 to En to the other integration blocks 6-3 to 6-n except -2 is stopped, and the power consumption in the integration blocks 6-3 to 6-n is reduced.

  Further, the power supply unit 11 supplies the power supply voltage E1 to the integration block 6-1 during the integration period ts1 according to the reference gate signal G from the gate signal generation unit 9 and the control signal from the power supply control unit 86. During the integration period ts2, the power supply voltage E2 is supplied to the integration block 6-2. That is, since the power supply unit 11 supplies the operation power supply voltage to the integration block 6-1 and the integration block 6-2 in accordance with each integration period, the integration periods ts1 and ts2 which are synchronization integration periods are set. The power consumption in the integration blocks 6-1 and 6-2 during the removal period is reduced.

  The signal waveforms of the gate signals G1 and G2 and the voltage waveforms of the power supply voltages E1 and E2 are not limited to the same example. For example, from the supply of the power supply voltage to the integration block 6, the integration block 6 becomes operable. The supply start timing of the power supply voltages E1 and E2 may be set earlier than the timing when the gate signals G1 and G2 become the high level by the response time.

  Note that the delay and advance of the timing of such a pulse P occurs due to a shift between the period t1 of the reference gate signal G generated by the gate signal generation unit 9 and the pulse period t2 in the wireless transmission device. When the pulse period t2 is longer than the pulse period t1, the timing of the pulse P is continuously delayed, and when the pulse period t2 is shorter than the pulse period t1, the timing of the pulse P is continuously advanced. .

  Therefore, when the synchronization maintaining unit 82 determines that the timing of the pulse P is delayed, the timing of the pulse P is advanced while the timing of the integration period ts1 in the gate signal G1 is synchronized with the timing of the pulse P as described above. If it is determined that, the timing of the integration period ts2 in the gate signal G2 may be synchronized with the timing of the pulse P thereafter. In this case, the integration period ts2 is the first integration period, the integration circuit 61-2 is the first integration circuit, the integration period ts1 is the second integration period, and the integration circuit 61-1 is the second integration circuit.

  Then, the synchronization maintaining unit 82 compares the integral value indicated by the signal AD1 and the integral value indicated by the signal AD2, and if the integral value indicated by the signal AD1 becomes larger, the timing of the pulse P is changed. Since it is advanced, the timing of the integration period ts2 in the gate signal G2 may be changed in the direction of the integration period ts1, that is, the advance direction by the phase control unit 10 according to the control signal from the synchronization maintaining unit 82. .

  As a result, when the deviation of the timing of the pulse P is in the direction opposite to the second integration period (integration period ts2), a new second integration period (integration period ts1) in the direction of deviation of the timing of the pulse P is obtained. Therefore, it is possible to detect that the timing of the pulse P is shifted by increasing the integration value of the new second integrating circuit (integrating circuit 61-1). It becomes easy.

  Then, pulse synchronization is maintained as described above, and the demodulator 83 is based on the signals AD1 and AD2 obtained in the integration blocks 6-1 and 6-2 in the integration periods ts1 and ts2, which are synchronization integration periods. Data Dout is demodulated.

  Next, operations of the time measuring unit 84 and the band switching unit 85 will be described. First, the time when the pulse synchronization timing is not acquired by the initial synchronization unit 81, that is, the time from when the wireless receiver 1 is activated until the pulse synchronization timing is acquired by the initial synchronization unit 81, and the synchronization maintenance unit 82 maintains the synchronization. The time until the pulse synchronization timing is acquired again by the initial synchronization unit 81 after the synchronization cannot be obtained is counted by the timing unit 84. When the time counted by the time measuring unit 84 exceeds a preset reference time, it is considered that the background noise power is large in a specific frequency range. The frequency band is switched.

  For example, when the filter 4 is set to a pass band of 3.1 GHz and synchronization is not possible, and the time measured by the time measuring unit 84 exceeds a preset reference time, the band switching unit 85 While the frequency band of the filter 4 is switched to 3.5 GHz, synchronization cannot be achieved when the filter 4 is set to the 3.5 GHz pass band, and the time measured by the time measuring unit 84 is a preset reference time. Is exceeded, the band switching unit 85 switches the frequency band of the filter 4 to 3.1 GHz.

  In addition to the example in which the frequency band of the filter 4 is switched when the time when synchronization cannot be achieved exceeds a preset reference time, the frequency of occurrence of a communication error exceeds a preset reference by detecting any communication error. In this case, the frequency band of the filter 4 may be switched.

  Thereby, when communication is difficult because the power of background noise is large, the stability of wireless communication can be improved by changing the frequency band of the filter 4 to avoid the frequency of background noise.

(Second Embodiment)
Next, a radio reception apparatus using the radio reception method according to the second embodiment of the present invention will be described. FIG. 4 is a block diagram illustrating an example of a configuration of a wireless reception device using the wireless reception method according to the second embodiment of the present invention. The radio reception device 1a illustrated in FIG. 4 is different from the radio reception device 1 in that the signal processing unit 8a further includes a deviation direction detection unit 821 for detecting the deviation direction of the pulse timing, and the synchronization maintaining unit 82 and the power supply control unit 86. Is different in that a synchronization maintaining unit 82a and a power supply control unit 86a are provided.

  Since the other configuration is the same as that of the wireless reception device 1, the description thereof is omitted, and the characteristic operation in the present embodiment will be described below. FIG. 5 is a timing chart for explaining operations of the synchronization maintaining unit 82a and the power supply control unit 86a. In the present embodiment, the signal waveforms of the gate signals G1 to Gn are the same as the voltage waveforms of the power supply voltages E1 to En. Therefore, in FIG. 5, the waveforms of the gate signals G1 to Gn and the power supply voltages E1 to En are used. Are shared by the same waveform.

  First, the pulse synchronization timing is acquired by the initial synchronization unit 81 by the operation shown in FIG. Next, as shown in FIG. 5, the synchronization maintaining unit 82 a sets the timings of the integration periods ts <b> 1 to tsn so as to partially overlap with the adjacent integration periods. Then, the synchronization maintaining unit 82a integrates the signal AD1 indicating the integration value obtained by the AD converter 62-1 and the signal AD2 indicating the integration value obtained by the AD converter 62-2 so as to be equal. As a result of adjusting the timing between the period ts1 and the integration period ts2, the overlapping part of the integration period ts1 and the integration period ts2 and the timing of the pulse P are synchronized.

  Further, the synchronization maintaining unit 82 a outputs the signals AD 1 and AD 2 obtained in the integration blocks 6-1 and 6-2 in the integration periods ts 1 and ts 2, which are synchronization integration periods, to the demodulation unit 83. Data Dout is demodulated based on the signals AD1 and AD2.

  In this case, the integration periods ts1 and ts2, which are partial integration periods in the plurality of integration periods ts1 to tsn of the plurality of integration circuits 61-1 to 61-n, correspond to synchronization integration periods used for maintaining synchronization. The integration period ts3 corresponds to a delayed integration period positioned at a timing delayed from the integration period ts2, and the integration period tsn corresponds to a lead integration period positioned at a timing advanced from the integration period ts1.

  Then, due to variations in accuracy between the generation circuit of the pulse period t2 such as the oscillation circuit in the wireless transmission device and the generation circuit of the pulse period t1 such as the oscillation circuit in the gate signal generation unit 9, the pulse period t2 and the pulse period t1 When there is a difference between them, for example, when the pulse period t2 is longer than the pulse period t1, the timing shift of the pulse P is delayed as shown by an arrow B in FIG. Then, according to the delay of the pulse P, the timing of the pulse P sequentially moves in the order of the integration period ts 2 → the integration period ts 3 →... → the integration period tsn → the integration period ts 1, and shows the integration value obtained by the AD converter 62. The value of the signal sequentially increases in the order of signal AD2 → signal AD3 →... → signal ADn → signal AD1.

  On the other hand, for example, when the pulse period t2 is shorter than the pulse period t1, the deviation of the timing of the pulse P is in the advancing direction opposite to the arrow B. Then, as the pulse P advances, the timing of the pulse P sequentially moves in the order of the integration period ts 1 → the integration period tsn →. The value of the signal sequentially increases in the order of signal AD1 → signal ADn →... → signal AD3 → signal AD2.

  Therefore, the deviation direction detection unit 821 is obtained by the AD converter 62-n for the signal AD3 obtained by the AD converter 62-3 for the integration period ts3 which is a delay integration period and for the integration period tsn for the advance integration period. The signal ADn is monitored, and when the value of the signal AD3 increases, it is determined that the shift direction is the lag direction, and when the value of the signal ADn increases, the shift direction is determined to be the advance direction. Is detected.

  Then, the power supply control unit 86a is shifted from the integration blocks 6-1 and 6-2 that perform integration for the integration periods ts1 and ts2 that are the synchronization integration periods among the plurality of integration blocks 6-1 to 6-n. Supply of the power supply voltage by the power supply unit 11 to the other integration circuits excluding the integration circuit that performs integration for the integration period in the deviation direction detected by the direction detection unit 821 is stopped.

  For example, if the shift direction is the delay direction, the power supply control unit 86a performs integration for the integration blocks 6-1 and 6-2 and the integration period ts3 that is an integration period in the delay direction with respect to the integration periods ts1 and ts2. The power supply voltages E1, E2, and E3 are supplied to the integration block 6-3, and power is supplied to the other integration blocks 6-4 to 6-n excluding the integration blocks 6-1, 6-2, and 6-3. Supply of the power supply voltage by the part 11 is stopped.

  On the other hand, if the deviation direction is the advance direction, the power supply control unit 86a performs integration for the integration blocks 6-1 and 6-2 and the integration period tsn that is the integration period in the advance direction from the integration periods ts1 and ts2. The power supply voltages E1, E2, and En are supplied to the integration block 6-n, respectively, and to the integration blocks 6-3 to 6- (n-1) other than the integration blocks 6-1, 6-2, and 6-n. The supply of the power supply voltage by the power supply unit 11 is stopped.

  When the power supply control unit 86a detects that the integration values obtained by the integration blocks 6-1 and 6-2 that perform integration for the integration periods ts1 and ts2 are substantially equal, the power supply control unit 86a. In response to the control signal from the power supply unit 11, the power supply unit 11 supplies the power supply voltage to the integration circuit that performs integration for the integration period in the shift direction detected by the shift direction detection unit 821 from the integration periods ts1 and ts2.

  Specifically, if the deviation direction detected by the deviation direction detection unit 821 is a lagging direction, the values of the signals AD1 and AD2 obtained by the integration blocks 6-1 and 6-2 by the power supply control unit 86a are substantially equal. When it is detected that they are equal, the power supply unit 11 supplies the power supply voltage E3 to the integration block 6-3 according to the control signal from the power supply control unit 86a. On the other hand, if the deviation direction detected by the deviation direction detector 821 is the advance direction, the values of the signals AD1 and AD2 obtained by the integration blocks 6-1 and 6-2 by the power supply controller 86a are substantially equal. When this is detected, the power supply unit 11 supplies the power supply voltage En to the integration block 6-n according to a control signal from the power supply control unit 86a.

  When the synchronization maintaining unit 82a detects that the value of the signal AD2 is larger than the value of the signal AD1, for example, the integration periods ts2 and ts3 are set as new integration periods for synchronization, and the power supply control unit The power supply to the integration block 6-1 is stopped by 86a, and the signals AD2 and AD3 obtained in the integration blocks 6-2 and 6-3 in the integration periods ts2 and ts3 are output to the demodulation unit 83, and the demodulation unit 83 83, the data Dout is demodulated based on the signals AD2 and AD3.

  Similarly, when the synchronization maintaining unit 82a detects that the value of the signal AD1 is larger than the value of the signal AD2, for example, the integration periods tsn and ts1 are set as new synchronization integration periods, and the power supply control is performed. The power supply to the integration block 6-2 is stopped by the unit 86a, and the signals ADn and AD1 obtained by the integration blocks 6-n and 6-1 in the integration periods tsn and ts1 are output to the demodulation unit 83 and demodulated. The unit 83 demodulates the data Dout based on the signals ADn and AD1.

  As a result, even when the timing of the pulse P is shifted, the synchronization maintaining unit 82a sets a new synchronization integration period in accordance with the change in the timing of the pulse P, so that synchronization can be maintained. . Further, the power supply control unit 86a supplies the power supply voltage to the other integration blocks excluding the integration block that performs integration during the synchronization integration period and the integration period shifted from the synchronization integration period. Since it is stopped, power consumption can be reduced while maintaining synchronization using a plurality of integration blocks.

  By the way, when a new synchronization integration period is set and the operation power supply voltage is supplied to the new integration block whose power supply has been stopped and the integration operation starts simultaneously, the operation power supply voltage is supplied. Immediately after the start of the operation, the response time of the integration block is required, and there is a possibility that the stable operation may not be performed. In particular, in the wireless reception device 1a that receives a pulse of about 1 nanosecond, it is necessary to switch the power supply to the integration block 6 by the power supply unit 11 in a switching time of about 1 nanosecond to 90 nanoseconds. Therefore, when the operation power supply voltage is supplied and the integration operation is started at the same time, the integration operation is newly started according to the response time for stable operation of the integration block after the operation power supply voltage supply starts. There is a high possibility that the integration block to be operated does not operate stably.

  However, in the wireless reception device 1a, the power supply control unit 86a sets a new synchronization integration period for the integration block that performs integration for the integration period in the shift direction, that is, the integration block that starts the integration operation next. Since the power supply voltage for operation can be supplied in advance before the integration operation is started, the integration block that newly starts the integration operation when a new synchronization integration period is set by the synchronization maintaining unit 82a. It is possible to reduce the unstable operation.

It is a block diagram which shows an example of a structure of the radio | wireless receiving apparatus using the radio | wireless receiving method which concerns on the 1st Embodiment of this invention. It is a signal waveform diagram for demonstrating the initial synchronization process by the initial stage synchronization part shown in FIG. 3 is a timing chart for explaining operations of a synchronization maintaining unit and a power supply control unit shown in FIG. 1. It is a block diagram which shows an example of a structure of the radio | wireless receiving apparatus using the radio | wireless receiving method which concerns on the 2nd Embodiment of this invention. 5 is a timing chart for explaining operations of a synchronization maintaining unit and a power supply control unit shown in FIG. 4. It is a block diagram which shows the radio | wireless receiver of UWB communication which concerns on background art. It is explanatory drawing for demonstrating the pulse-synchronization process which concerns on background art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,1a Wireless receiver 2 Antenna 3 Amplifier 4 Filter 5 Detector 6 Integration block 8, 8a Signal processing part 9 Gate signal generation part 10 Phase control part 11 Power supply part 61 Integration circuit 62 AD converter 81 Initial synchronization part 82, 82a Synchronization maintaining unit 83 Demodulating unit 84 Timing unit 85 Band switching unit 86, 86a Power supply control unit 821 Deviation direction detecting unit

Claims (7)

A receiving unit for receiving a radio signal having a pulse at a predetermined period;
A plurality of integration circuits that integrate the signals received by the reception unit with respect to a plurality of integration periods, which are different periods of the period, respectively;
A power supply unit for supplying a power supply voltage for operation to the plurality of integrating circuits;
Based on the integration values obtained by the plurality of integration circuits, obtain the pulse timing when the pulse is received by the receiving unit, the synchronization integration period that is a partial integration period in the plurality of integration period A synchronization unit that synchronizes with the acquired pulse timing;
A deviation direction detection unit for detecting a deviation direction of the pulse timing;
After the synchronization integration period and the pulse timing are synchronized by the synchronization unit, the shift direction detection unit detects the synchronization integration period and the synchronization integration period out of the plurality of integration circuits . Other integration circuits except for the integration circuit that performs the integration for the integration period for synchronization and the integration period for the shift direction, by supplying the power supply voltage to the integration circuit that performs the integration for the integration period of the shift direction by the power supply unit. A power supply control unit for stopping the supply of the power supply voltage by the power supply unit,
A radio receiving apparatus comprising: a demodulator that demodulates the radio signal based on an integration value obtained by an integration circuit that performs the integration for the synchronization integration period. The shift direction detection unit is located at an integration value obtained by a delay integration circuit that performs the integration for a delay integration period positioned at a timing delayed from the synchronization integration period, and at a timing advanced from the synchronization integration period. for proceeds integration period based on an integration value obtained by the integration proceeds performs integration circuit, the radio receiving apparatus according to claim 1, wherein the detecting a shift direction of the pulse timing. The synchronization unit sets a part of the integration periods so as to overlap each other with an adjacent integration period, and includes two integration periods in which the part of the plurality of integration periods overlap each other. It is set as a synchronization integration period, and the synchronization between the pulse timing and the synchronization integration period is maintained by changing the integration period that becomes the synchronization integration period according to the change of the pulse timing,
The power supply control unit is detected by the shift direction detection unit more than the two integration periods when the integration values obtained by the two integration circuits performing the integration for the two integration periods are substantially equal. 3. The radio receiving apparatus according to claim 1, wherein the power supply voltage is supplied by the power supply unit to an integration circuit that performs the integration for an integration period in a deviation direction. A receiving unit for receiving a radio signal having a pulse at a predetermined period;
A plurality of integration circuits that integrate the signals received by the reception unit with respect to a plurality of integration periods, which are different periods of the period, respectively;
A power supply unit for supplying a power supply voltage for operation to the plurality of integrating circuits;
Based on the integration values obtained by the plurality of integration circuits, obtain the pulse timing when the pulse is received by the receiving unit, the synchronization integration period that is a partial integration period in the plurality of integration period A synchronization unit that synchronizes with the acquired pulse timing;
After the synchronization integration period and the pulse timing are synchronized by the synchronization unit, the power supply to other integration circuits excluding the integration circuit that performs the integration for the synchronization integration period among the plurality of integration circuits A power supply control unit for stopping supply of the power supply voltage by the supply unit;
A demodulator that demodulates the radio signal based on an integration value obtained by an integration circuit that performs the integration for the synchronization integration period ;
A bandpass filter capable of switching a frequency band to be filtered while filtering the signal received by the receiving unit and outputting the filtered signal to the plurality of integrating circuits;
A timekeeping unit that times the time when the pulse timing is not acquired by the synchronization unit;
A band switching unit that changes the frequency band of the band filter when the time counted by the time counting unit exceeds a preset reference time;
The plurality of integrating circuits integrate the signal output from the bandpass filter.
A wireless receiver characterized by the above. 5. The radio reception apparatus according to claim 1, wherein the power supply unit supplies an operation power supply voltage to the plurality of integration circuits according to each integration period. 6. Receiving a wireless signal having pulses at a predetermined period;
Integrating each of the received signals using a plurality of integration circuits for a plurality of integration periods that are different periods in the period;
Supplying a power supply voltage for operation to the plurality of integrating circuits;
Based on the integration values obtained by the plurality of integration circuits, the pulse timing at which the pulse is received is acquired, and the synchronization pulse that is a partial integration period in the plurality of integration periods is acquired. And the process of synchronizing with
Detecting a shift direction of the pulse timing;
After the synchronization integration period and the pulse timing are synchronized, the integration is performed for the synchronization integration period and the integration period in the shift direction detected from the synchronization integration period of the plurality of integration circuits. Supplying the power supply voltage to an integration circuit, and stopping the supply of the power supply voltage to other integration circuits excluding the integration circuit that performs the integration for the synchronization integration period and the integration period in the shift direction ;
And a step of demodulating the radio signal based on an integration value obtained by an integration circuit that performs the integration for the synchronization integration period. Receiving a wireless signal having pulses at a predetermined period;
Integrating each of the received signals using a plurality of integration circuits for a plurality of integration periods that are different periods in the period;
Supplying a power supply voltage for operation to the plurality of integrating circuits;
Based on the integration values obtained by the plurality of integration circuits, the pulse timing at which the pulse is received is acquired, and the synchronization pulse that is a partial integration period in the plurality of integration periods is acquired. And the process of synchronizing with
After the synchronization integration period and the pulse timing are synchronized, supply of the power supply voltage to other integration circuits excluding the integration circuit that performs the integration for the synchronization integration period is stopped among the plurality of integration circuits And a process of
Demodulating the wireless signal based on an integration value obtained by an integration circuit that performs the integration for the synchronization integration period ;
Measuring the time when the pulse timing is not acquired by the synchronization unit;
Changing the frequency band to be filtered of a band-pass filter that filters the received signal and outputs it to the plurality of integration circuits when the measured time exceeds a preset reference time. ,
The wireless receiving method, wherein the plurality of integrating circuits integrate signals output from the bandpass filter .

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