JP4736770B2 - Serial receiving circuit, serial data transmitting / receiving circuit, and semiconductor memory device - Google Patents

Description

  The present invention relates to a serial reception circuit, a serial data transmission / reception circuit, and a semiconductor memory device, and more particularly, a serial reception circuit that receives fixed data added to the beginning of transferred data, a serial data transmission / reception circuit, and The present invention relates to a semiconductor memory device using a serial data receiving circuit for transmission / reception of redundant addresses of redundant memory cells.

  In a semiconductor storage device such as a DRAM, the number of memory cells arranged in one chip is increasing as the storage capacity is increased. As a result, in the manufacturing process, spare redundant memory cells are increasingly used to replace defective memory cells generated in one chip.

  When using redundant memory cells, a spare memory cell array and redundant word lines and redundant bit lines are first provided in the semiconductor memory device. When actually using the semiconductor memory device, The redundant word line or the redundant bit line is used by replacing the defective word line and bit line.

  The presence of a fault is detected in the memory cell array in the semiconductor memory device by inspection at the manufacturing stage, and the fuse indicating the position of the defect is cut by a laser or the like, so that the position of the defect is stored in the fuse. Let When repairing a defect in the memory cell array, the repair circuit reads the state of the fuse set and generates a redundant address. When the input address matches the redundant address when accessing the memory, a spare decoder is selected, A semiconductor memory device having a circuit configuration in which a normal decoder is inactivated at this time by replacing a word line and a bit line in which the above occurs is used (see, for example, Patent Document 1).

  In the semiconductor memory device shown in FIG. 3 of Patent Document 1, a relief circuit is provided between the address latch circuit and the decoder of the memory cell array, and a CMOS including a fuse set having a large mounting area inside the relief circuit. A type address comparison circuit is provided.

  In the relief circuit having such a circuit configuration, if an attempt is made to increase the number of relief circuits, an increase in the number of wirings related to the relief circuit and an increase in circuit scale accompanying an increase in the number of fuses become problems. This increase in circuit scale increases the chip area, which is a factor that hinders downsizing of the chip.

  In order to reduce the size of a semiconductor memory device equipped with a relief circuit, several hundred or more fuse portions are mounted in a region different from the memory cell array, and the trimmed fuse information is used as word-related redundant addresses and bits. It is preferable to transfer the system redundant address to the decoder of the memory cell array using communication.

  In recent years, the number of fuses has increased as the storage capacity of semiconductor memory devices has increased. When the conduction state or the cut state of the fuse is transmitted to the decoder portion of the memory cell array by independent wiring one by one, the mounting area of the wiring becomes enormous, so serial communication as shown in FIG. 4 is performed. The transfer used is being performed.

  FIG. 4 shows a block diagram of a conventional serial data transmission / reception circuit. The serial data transmission / reception circuit 330 shown in FIG. 4 uses transmission registers 336-1 to 336-4 and reception registers 352-1 to 352-4 as shift registers, and starts transmission based on the serial transfer clock 362 (GCLK). This circuit realizes serial transmission by controlling termination.

  In general, in a semiconductor memory device, there are elements provided with several hundred redundant addresses. However, in the serial data transmission / reception circuit 330 shown in FIG. 4, a circuit for transmitting a 4-bit redundant address is shown to simplify the explanation. Yes.

  As shown in FIG. 4, the conventional serial data transmission / reception circuit 330 includes a plurality of fuses 314-1 to 314-4 indicating the positions of defects and redundant addresses existing in the memory cell array. The serial data transmission / reception circuit 330 receives a redundant address and a redundant address transmission circuit 315 that inputs a conduction state or a disconnection state of the fuses 314-1 to 314-4 and serially transmits the serial transmission path 319. And a redundant address receiving circuit 317 that is handed over to a decoder of the memory cell array.

  The redundant address transmission circuit 315 includes a plurality of latch circuits 334-1 to 334-4 that store the conduction state or the disconnection state of the fuses 314-1 to 314-4. The redundant address transmission circuit 315 inputs the conduction state or the disconnection state of the fuses 314-1 to 314-4 stored in the latch circuits 334-1 to 334-4, and uses this as transmission data for the serial transfer clock 362 (GCLK). Transmission registers 336-1 to 336-4 that shift based on the above.

  The redundant address reception circuit 317 includes a plurality of reception registers 352-1 to 352-4 that receive transmission data transmitted from the redundant address transmission circuit 315 and shifts based on the serial transfer clock 362 (GCLK). Yes. The redundant address receiving circuit 317 generates a serial transmission start signal and an end signal corresponding to the number of transmission registers 336-1 to 336-4 using a counter, and outputs them to the trigger signal generator 356. A control circuit 354 is provided. Further, the redundant address receiving circuit 317 receives a serial transmission start signal and end signal and a clock 364 and serially transfers them to the transmission registers 336-1 to 336-4 and the reception registers 352-1 to 352-4. A trigger signal generator 356 that outputs a clock 362 (GCLK) is provided.

  When the initial value setting signal 360 is input to the serial data transmission / reception circuit 330 shown in FIG. 4, the plurality of latch circuits 334-1 to 334-4 store the conduction state or the disconnection state of the fuses 314-1 to 314-4 and transmit The registers 336-1 to 336-4 acquire and temporarily store the states of the fuses 314-1 to 314-4 stored in the latch circuits 334-1 to 334-4.

  Next, when the serial transmission control circuit 354 outputs a start signal to the trigger signal generator 356, the trigger signal generator 356 outputs the number of pulses corresponding to the number of bits of transmission data until the end signal is output. The serial transfer clock 362 (GCLK) having the above is output to the plurality of transmission registers 336-1 to 336-4 and the reception registers 336-1 to 336-4. The transmission registers 336-1 to 336-4 perform an operation of shifting transmission data in the left direction in FIG. 4 based on the serial transfer clock 362 (GCLK).

  In one of the reception registers 352-1 to 352-4, the data received from the transmission registers 36-1 to 336-4 is shifted to the right side shown in FIG. 4 based on the serial transfer clock 362 (GCLK). The serial transmission control circuit 354 outputs the serial transmission clock 362 (GCLK) for the quantity of the transmission registers 336-1 to 336-4, and then outputs a serial transmission end signal to the trigger signal generator 356.

When the trigger signal generator 356 receives the serial transmission end signal from the serial transmission control circuit 354, the trigger signal generator 356 stops the serial transfer clock 362 (GCLK) and ends the serial transmission. When the serial transmission is completed, the reception registers 352-1 to 352-4 output the received transmission data of Q1 to Q4 to the decoder of the memory cell array.
Japanese Patent Laid-Open No. 11-162191 (FIGS. 1, 2, 11, and 12)

  A counter for outputting the serial transfer clock 362 (GCLK) is required in the serial transmission control circuit 354 shown in FIG. This counter is required to have a number of digits corresponding to the number of bits of transmission data (the number of transmission registers 336-1 to 336-4).

  In a semiconductor storage device having a large storage capacity, an increase in the mounting area of the counter becomes a problem, and when the storage capacity of the semiconductor storage device is different, a number of transmission registers corresponding to the storage capacity is required. Therefore, conventionally, it has been necessary to design and produce a serial transmission control circuit 354 for each type of semiconductor memory device. As a result, the mounting area of the serial transmission control circuit increases, resulting in an increase in the size of the semiconductor memory device and a longer design and production delivery time.

  The present invention has been made to solve the above-described problems, and provides a small serial reception circuit and serial data transmission / reception circuit that do not require a counter for generating a serial transfer clock corresponding to the number of transmission registers and that are easy to design. There is to do.

  It is another object of the present invention to provide a small-sized semiconductor memory device that requires no counter for generating serial transfer clocks corresponding to the number of redundant addresses and that allows easy design of a relief circuit in a short delivery time.

To achieve the above object, a serial receiving circuit of the present invention is used in a semiconductor memory device for repairing a defective memory cell by replacing a defective memory cell existing in a memory cell array with a redundant memory cell, and includes a serial address including a redundant address of the redundant memory cell. A serial reception circuit for receiving transmitted data, having a plurality of serially connected reception registers, sequentially inputting serially transmitted data from a first-stage reception register based on a serial transfer clock, and subsequent stages The reception register unit that shifts and outputs to the reception register and the reception register at the last stage of the reception register unit, and when fixed data is output from the reception register at the last stage, reception of all data is completed a receiving register for fixed data and outputs a reception completion signal determined to have the fixed data receive register After the acquisition of al the reception completion signal, and a transfer clock generating circuit for stopping the output of the serial transfer clock, and configured to complete the reception of the data based on the reception completion signal.

In addition, for the reception register and the fixed data reception register of the serial reception circuit, an initial value setting operation for resetting register data when an initial value setting signal is input is started, and the transfer clock generation circuit is , even after the input of the initial value setting signal, after receiving register and fixed data reception register has finished the initial value setting operation, it may be configured to start outputting the serial transfer clock.

In order to achieve the above object, a serial data transmitting / receiving circuit of the present invention is used in a semiconductor memory device for repairing a defective memory cell by replacing a defective memory cell existing in a memory cell array with a redundant memory cell. The serial data transmission / reception circuit includes a serial transmission circuit that generates and serially transmits data with fixed data added to the head thereof, and a serial reception circuit that receives the data. The serial reception circuit has a plurality of reception registers connected in series, and sequentially inputs the serially transmitted data from the first-stage reception register based on the serial transfer clock, and shifts to the subsequent-stage reception register. Is connected to the reception register at the last stage of the reception register section, and when fixed data is output from the reception register at the last stage, it is determined that reception of all data has been completed and received. A fixed data receiving register for outputting a completion signal, and a transfer clock generating circuit for stopping the output of the serial transfer clock after obtaining the reception completion signal from the fixed data receiving register. The reception of the data is completed based on the reception completion signal.

In addition, for the reception register and the fixed data reception register of the serial data transmission / reception circuit, an initial value setting operation for resetting register data when an initial value setting signal is input is started, and the transfer clock generation is performed. The circuit may be configured to start outputting the serial transfer clock after the input of the initial value setting signal and after the receiving register and the fixed data receiving register finish the initial value setting operation. .

  The present invention also includes a one-shot circuit that generates a data storage signal that is set after the initial value setting signal is input to the serial data transmission / reception circuit and is reset before the serial transfer clock is output. It was. The serial transmission circuit stores transmission data on the basis of the data storage signal, and sequentially shifts the stored transmission data on the basis of the serial transfer clock and outputs the transmission data from the last-stage transmission register. Is connected to the last stage of the transmission register unit, stores fixed data based on the data storage signal, and stores the stored fixed data and data output from the transmission register unit based on the serial transfer clock. And a fixed data addition transmission register that serially transmits data with fixed data added to the head.

In order to achieve the above object, the semiconductor memory device of the present invention inputs the conduction state or the disconnection state of the fuse set in which the redundant address of the redundant memory cell is specified by trimming, and serially transmits the redundant address. And a redundant address receiving circuit for receiving a redundant address serially transmitted by the redundant address transmitting circuit that is present in the vicinity of a decoder of a memory cell array mounted in a region different from the fuse set. ing. The redundant address transmission circuit has a function of generating and transmitting data in which fixed data is added to the head of the redundant address for serial transmission. The redundant address reception circuit has a plurality of reception registers connected in series, and sequentially inputs the serially transmitted data from the first-stage reception register based on the serial transfer clock, and shifts to the subsequent-stage reception register. Is connected to the reception register at the last stage of the reception register section, and when fixed data is output from the reception register at the last stage, it is determined that reception of all data has been completed and received. A fixed data reception register that outputs a completion signal; and a transfer clock generation circuit that stops outputting the serial transfer clock after obtaining the reception completion signal from the fixed data reception register. Based on this, the data reception is completed.

In addition, for the reception register and the fixed data reception register of the semiconductor memory device, an initial value setting operation for resetting register data when an initial value setting signal is input is started, and the transfer clock generation circuit for, even after the input of the initial value setting signal, after receiving register and fixed data reception register has finished the initial value setting operation, it may be configured to start outputting the serial transfer clock.

  According to the present invention, the semiconductor memory device includes a one-shot circuit that generates a data storage signal that is set after the initial value setting signal is input and reset before the serial transfer clock is output. The serial transmission circuit stores transmission data based on the data storage signal, and sequentially shifts the stored transmission data based on the serial transfer clock, and outputs the data from the last-stage transmission register. A register unit is connected to the last stage of the transmission register unit, stores fixed data based on the data storage signal, and uses the stored fixed data and data output from the transmission register unit as the serial transfer clock. It may be configured to include a fixed data addition transmission register that sequentially outputs data based on the data and serially transmits data with fixed data added to the head.

  According to the present invention, in order to stop the output of the serial transfer clock, instead of providing a control circuit such as a counter for counting the number of serial transfer clocks corresponding to the number of data to be transmitted, it is added to the head of the transmitted data. The fixed data receiving register that receives the dummy fixed data is provided after the last stage of the receiving register in the receiving register unit, and when the fixed data receiving register receives the fixed data, the output of the serial transfer clock is stopped. Therefore, a transfer clock generation circuit independent of the number of transmission data to be serially transmitted can be configured.

  Even when the number of transmission data to be serially transmitted is increased, it is not necessary to increase the mounting area of the transfer clock generation circuit, and the same transfer clock generation circuit can be used. Therefore, the design and production of the semiconductor memory device is facilitated, and a small semiconductor memory device can be provided with a short delivery time.

  The serial reception circuit according to the present invention has a plurality of reception registers connected in series, and sequentially inputs the serially transmitted data from the first-stage reception register based on the serial transfer clock, and shifts to the subsequent-stage reception register. And a receiving register unit for outputting. In the present invention, the number of reception register units included in the reception register unit is not limited. The serial receiving circuit according to the present invention is connected to the last receiving register of the receiving register unit, and determines that reception of all data is completed when fixed data is output from the last receiving register. And a fixed data reception register for outputting a reception completion signal, and configured to complete the reception of the data based on the reception completion signal.

  The fixed data is data added to the head of serially transmitted data. In addition, the fixed data receiving register does not necessarily need to use a register, and may detect that fixed data is output from the receiving register at the last stage and read the received data. The transfer clock may be stopped to create a reception completion state. Further, the serial transfer clock in the serial reception circuit may be configured to be output as a trigger when fixed data is output to the serial transfer path.

  By configuring the serial reception circuit in this way, the output of the serial transfer clock can be stopped using the reception completion signal output from the fixed data reception register, and transfer clock generation independent of the number of transmission data to be serially transmitted A circuit can be constructed.

  Further, according to the present invention, an initial value setting operation for resetting register data is started when an initial value setting signal is input to the receiving register and the fixed data receiving register of the serial receiving circuit. Furthermore, the serial receiving circuit according to the present invention starts outputting the serial transfer clock after the initial value setting signal is input and after the receiving register and the fixed data receiving register finish the initial value setting operation. In addition, a transfer clock generation circuit that stops the output of the serial transfer clock after obtaining the reception completion signal indicating completion of reception of all data from the fixed data reception register may be provided. By configuring the serial reception circuit in this way, a counter corresponding to the number of transmission registers becomes unnecessary. Therefore, a small serial receiving circuit can be provided with a short delivery time.

  The serial data transmission / reception circuit of the present invention includes a serial transmission circuit that generates and transmits data in which fixed data is added to the head of transmission data to be serially transmitted, and a serial reception circuit that receives the data. It was made up of a circuit. The serial reception circuit has a plurality of reception registers connected in series, and sequentially inputs the serially transmitted data from the first-stage reception register based on the serial transfer clock, and shifts to the subsequent-stage reception register. Is connected to the reception register at the last stage of the reception register section, and when fixed data is output from the reception register at the last stage, it is determined that reception of all data has been completed and received. A serial data transmission / reception circuit configured to complete the reception of the data based on the reception completion signal. Therefore, the output of the serial transfer clock can be stopped using the reception completion signal output from the fixed data reception register, and a transfer clock generation circuit independent of the number of serially transmitted transmission data can be configured.

  The serial data transmission / reception circuit of the present invention starts an initial value setting operation for resetting register data when an initial value setting signal is input for the reception register and the fixed data reception register. After the input of the initial value setting signal to the serial receiving circuit, the receiving register and the fixed data receiving register start outputting the serial transfer clock at the timing after the initial value setting operation is completed, and the fixed A transfer clock generation circuit that stops the output of the serial transfer clock after obtaining the reception completion signal indicating completion of reception of all data from the data reception register may be provided.

  By configuring the serial data transmission / reception circuit in this way, a counter corresponding to the number of transmission registers becomes unnecessary. Therefore, a small serial data transmission / reception circuit can be designed and produced in a short delivery time and provided to the user.

  The serial data transmitting / receiving circuit of the present invention includes a one-shot circuit that generates a data storage signal that is set after the initial value setting signal is input and is reset before the serial transfer clock is output. . The serial transmission circuit stores transmission data on the basis of the data storage signal, and sequentially shifts the stored transmission data on the basis of the serial transfer clock and outputs the transmission data from the last-stage transmission register. Is connected to the last stage of the transmission register unit, stores fixed data based on the data storage signal, and stores the stored fixed data and data output from the transmission register unit based on the serial transfer clock. And a fixed data addition transmission register that serially transmits data with fixed data added to the head. By providing the serial data transmission / reception circuit with a one-shot circuit, a data storage signal can be easily created from the initial value setting signal.

  According to another aspect of the present invention, there is provided a redundant address transmission circuit for serially transmitting the redundant address by inputting a conduction state or a disconnected state of a fuse set in which a redundant address of the redundant memory cell is designated by trimming, A redundant address receiving circuit that is present in the vicinity of the decoder of the memory cell array mounted in a different area from the fuse set and receives the redundant address serially transmitted by the redundant address transmitting circuit. The redundant address transmission circuit has a function of generating and transmitting data in which fixed data is added to the head of the redundant address for serial transmission. The redundant address reception circuit has a plurality of reception registers connected in series, and sequentially inputs the serially transmitted data from the first-stage reception register based on the serial transfer clock, and shifts to the subsequent-stage reception register. Is connected to the reception register at the last stage of the reception register section, and when fixed data is output from the reception register at the last stage, it is determined that reception of all data has been completed and received. A fixed data reception register for outputting a completion signal, and the reception of the data is completed based on the reception completion signal.

  Therefore, the output of the serial transfer clock can be stopped using the reception completion signal output from the fixed data reception register, and a transfer clock generation circuit independent of the number of serially transmitted transmission data can be configured.

  Further, according to the present invention, an initial value setting operation for resetting register data is started when an initial value setting signal is input to the reception register and the fixed data reception register of the semiconductor memory device. Furthermore, the semiconductor memory device of the present invention starts the output of the serial transfer clock after the input of the initial value setting signal and after the receiving register and the fixed data receiving register finish the initial value setting operation. In addition, a transfer clock generation circuit that stops the output of the serial transfer clock after obtaining the reception completion signal indicating completion of reception of all data from the fixed data reception register may be provided. By configuring the serial receiving circuit in this way, a counter corresponding to the number of redundant addresses becomes unnecessary. Therefore, a small semiconductor memory device can be provided with a short delivery time.

  According to the present invention, the semiconductor memory device includes a one-shot circuit that generates a data storage signal that is set after the initial value setting signal is input and reset before the serial transfer clock is output. The serial transmission circuit stores transmission data based on the data storage signal, and sequentially shifts the stored transmission data based on the serial transfer clock, and outputs the data from the last-stage transmission register. A register unit is connected to the last stage of the transmission register unit, stores fixed data based on the data storage signal, and uses the stored fixed data and data output from the transmission register unit as the serial transfer clock. It may be configured to include a fixed data addition transmission register that sequentially outputs data based on the data and serially transmits data with fixed data added to the head. Thereby, the data storage signal can be easily created from the initial value setting signal.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram of a semiconductor memory device including a serial data transmission / reception circuit according to the present invention. As shown in FIG. 1, a semiconductor memory device 210 according to the present invention is connected to a control bus and an address bus, and receives a command relating to reading / writing of stored data from the CPU side. An I / O 213 such as a data interface that transmits and receives stored data to and from the CPU side, and a memory cell array 212 that stores data input from the I / O 213 in an area specified by an address.

  In the memory cell array 212 with a high degree of integration, defects may occur with a predetermined probability in the manufacturing stage. If the entire memory cell array 212 is made defective due to the presence of defects, the yield of the product is extremely deteriorated, the production efficiency is lowered, and the completed semiconductor memory device 210 becomes very expensive. .

  Therefore, a spare redundant memory cell array and its redundant word lines and redundant bit lines are provided in the semiconductor memory device 210, and these redundant word lines or redundant bit lines are replaced with faulty word lines and bit lines. By adopting a defect relieving method for relieving the semiconductor memory device 210, the product yield of DRAM or the like is increased.

  In the semiconductor memory device 210 adopting the defect relief method, the fuses 214-1 to 21 are detected by inspection at the manufacturing stage for defects existing in the memory cell array 212, and the defective addresses where the defects exist are set as redundant addresses by trimming. 214-4 is provided.

  The semiconductor memory device 210 also serves as a data transmission circuit that transmits a redundant address indicating a defective position of the memory cell array 212 stored in the fuses 214-1 to 214-4 to the redundant circuit 216 existing at a remote position. The redundant address transmission circuit 215 and the redundant address transmitted by the redundant address transmission circuit 215 are stored, and when the memory access is executed from the CPU side, the normal decoder is deactivated when the input address matches the defective address. And a decoder 218 for selecting a spare decoder and delivering the redundant address decoded by the spare decoder to the memory cell array 212.

  FIG. 2 is a block diagram of the serial data transmission / reception circuit 230 including the fuses 214-1 to 214-4.

  As shown in FIG. 2, the serial data transmission / reception circuit 230 inputs a plurality of fuses 214-1 to 214-4 (fuse set) and the conduction state or the cutting state of the fuses 214-1 to 214-4 as redundant addresses. Are latched and transferred to a plurality of transmission registers 236-1 to 236-4 connected in series.

  The serial data transmission / reception circuit 230 includes a redundant address reception circuit 217 and a redundant address transmission circuit 215. The redundant address transmission circuit 215 is provided with transmission registers 236-1 to 236-4 that acquire redundant addresses from the latch circuits 234-1 to 234-4 and serially transmit them to the redundant circuit 216 side that is located at a remote position. It has been. The transmission register unit 240 includes a plurality of serially connected transmission registers 236-1 to 236-4, and shifts received data based on the serial transfer clock 262 (GCLK).

  The serial data transmission / reception circuit 230 is present in the vicinity of the memory cell array 212 mounted in an area different from the plurality of fuses 214-1 to 214-4 (fuse set), and is transmitted by the redundant address transmission circuit 215. The redundant address receiving circuit 217 is provided as a serial receiving circuit that receives the redundant address and delivers it to the decoder 218.

  When the data storage signal 266 (FDFWZ) is set, the transmission registers 236-1 to 236-4 of the redundant address transmission circuit 215 store the fuses 214-1 to 214-4 stored in the latch circuits 234-1 to 234-4. The conduction state or the disconnection state is input and stored as a redundant address, and this is shifted as transmission data for serial transmission based on the serial transfer clock 262 (GCLK). The H fixed data generator 237 generates fixed data (for example, H). The H fixed data addition transmission register 238 is connected to the last stage of the transmission register unit 240, stores fixed data based on the data storage signal 266 (FDFWZ), and is output from the stored fixed data and transmission register unit 240. Data (redundant address and fixed data) are sequentially output and transmitted based on the serial transfer clock.

  Fixed data (for example, H) is added to the head of the redundant address (transmission data) for serial transmission.

  The one-shot circuit 239 of the redundant address transmission circuit 215 generates a data storage signal 266 (FDFWZ) that represents the timing at which the transmission registers 236-1 to 236-4 read the states of the fuses 214-1 to 214-4. The data storage signal 266 (FDFWZ) generated by the one-shot circuit 239 is a signal that is set after the initial value setting signal 260 is input and reset before the serial transfer clock 262 (GCLK) is output.

  The transmission registers 236-1 to 236-4 input and store as a redundant address the conduction state or the disconnection state of the fuse 214-4 stored by the latch circuits 234-1 to 234-4, and transmit this serially transmitted data As follows, based on the serial transfer clock 262 (GCLK), shift to the H fixed data addition transmission register 238 side.

  When the data storage signal 266 (FDFWZ) is set, the H fixed data addition transmission register 238 adds fixed data (for example, H signal) to the head of the redundant address to be transmitted, and based on the serial transfer clock 262 (GCLK). The fixed data is shifted and output to the redundant address receiving circuit 217 side via the serial transmission path 219.

  The H-fixed data addition transmission register 238 shifts the transmission data to the left in FIG. 2 based on the serial transfer clock 262 (GCLK) and stores it when the data storage signal 266 (FDFWZ) is reset. The transmitted data is output to the redundant address receiving circuit 217 side through the serial transmission path 219.

  The first-stage reception register 252-1 of the redundant address reception circuit 217 sequentially inputs the data serially transmitted from the redundant address transmission circuit 215, and enters the subsequent-stage reception register 252-2 based on the serial transfer clock 262 (GCLK). shift. The reception register unit 251 includes a plurality of reception registers 252-1 to 252-4 connected in series. Similarly to the reception register 252-1, the reception register unit 251 receives data received based on the serial transfer clock 262 (GCLK). shift.

  Further, the H fixed data reception register 253 of the redundant address reception circuit 217 is connected to the subsequent stage of the reception register 252-4, and when fixed data is output from the last reception register 252-4, all the data Is received, and a reception completion signal 268 is output.

  FIG. 3 is a timing chart of data transfer using the serial data transmission / reception circuit 230 according to the present invention.

  When the initial value setting signal 260 is input from the CPU side (in the example shown in FIG. 3, the initial value is set in the case of L data), the latch circuits 234-1 to 234-4 are connected to the fuses 214-1 to 214-. The 4 conduction or disconnection state is acquired and stored.

  One of the reception registers 252-1 to 252-4 and the H fixed data reception register 253 is reset to initial data (for example, L data) when an initial value setting signal 260 (for example, L data) is input. In a state where the H fixed data reception register 253 is initialized, the reception completion signal 268 (a signal for stopping the serial transfer clock 262 (GCLK)) output from the H fixed data reception register 253 is L data. Yes.

  Next, after the initial value setting signal 260 rises, the one-shot circuit 239 waits for the timing at which the latch circuits 234-1 to 234-4 acquire and determine the states of the fuses 214-1 to 214-4, and the one-shot circuit 239 receives the data. The storage signal 266 (FDFWZ) is set and output to the transmission registers 236-1 to 236-4 and the H fixed data addition transmission register 238.

  The data storage signal 266 (FDFWZ) output from the one-shot circuit 239 is reset before the serial transfer clock 262 (GCLK) is output. As a result, the inputs of the transmission registers 236-1 to 236-4 and the H fixed data addition transmission register 238 can be switched.

  The transfer clock generation circuit 256 is after the input of the initial value setting signal 260 and the reception completion signal 268 is in an enabled state (L in the example shown in FIG. 3), and the transmission registers 236-1 to 236-4 and H are fixed. After the data storage is completed in the data addition transmission register 238 and the reception registers 252-1 to 252-4 and the fixed data reception register 253 complete the initial value setting operation (reset operation), the serial transfer clock 262 ( GCLK) output is started (time T2 to time T6).

  Whether or not the reception registers 252-1 to 252-4 and the fixed data reception register 253 have finished the initial value setting operation is obtained by ANDing the outputs (Q1 to Q4 and the reception completion signal 268) of each register. The time difference may be managed by a timer.

  When the output of the serial transfer clock 262 (GCLK) is started, the transmission registers 236-1 to 236-4 and the H fixed data addition transmission register 238 shift the data every time the serial transfer clock 262 (GCLK) is acquired. Then, data transmission is started from the redundant address transmission circuit 215 via the serial transmission path 219.

  The reception register 252-1 stores the H fixed data output from the H fixed data adding transmission register 238 at the rising edge (time T2) of the first serial transfer clock 262 (GCLK). At the next rise (time T3) of the serial transfer clock 262 (GCLK), the fixed H data stored in the reception register 252-1 is transferred to the reception register 252-2.

  In this manner, transmission data including H fixed data is sequentially transferred every time the serial transfer clock 262 (GCLK) rises, and finally H fixed data is stored in the H fixed data reception register 253. (Time T6). When the H fixed data reception register 253 receives the H fixed data, the H fixed data reception register 253 outputs the H data to the transfer clock generation circuit 256 as a reception completion signal 268.

  When the transfer clock generation circuit 256 acquires the reception completion signal 268, the output of the serial transfer clock 262 (GCLK) that has been output is stopped (after time T7). When the serial transfer clock 262 (GCLK) stops, the transmission registers 236-1 to 236-4, the H fixed data addition transmission register 238, the reception registers 252-1 to 252-4, and the H fixed data reception register 253 receive data. End transfer of.

  In this state, the transmission data stored in the transmission registers 236-1 to 236-4 is received by the reception registers 252-1 to 252-4, so that the decoder 218 receives the reception registers 252-1 to 252. -4 outputs the redundant address (Q1 to Q4).

  The decoder 218 stores the acquired word-related redundant address and bit-related redundant address as substantial address selection information of the memory cell array 212. When the input address and the defective address coincide with each other during memory access by the CPU or the like, the decoder 218 Select. At this time, the normal decoder is inactivated and a redundant address is selected.

  As described above, fixed data is added to the head of transmission data to be serially transmitted, and when the fixed data reaches the final stage of the reception register unit 251, the serial transfer clock 262 (GCLK) is stopped, and the serial number of the redundant address is set. Transmission can be terminated.

1 is a block diagram of a semiconductor memory device including a serial data transmission / reception circuit according to the present invention. It is a block diagram of a serial data transmission / reception circuit including a fuse. 3 is a timing chart of data transfer using the serial data transmission / reception circuit shown in FIG. 2. The block diagram of the conventional serial data transmission / reception circuit is shown.

Explanation of symbols

210 Semiconductor memory device 211 Controller 212 Memory cell array 213 I / O
214-1 to 214-4 fuse 215 redundant address transmission circuit (serial transmission circuit)
216 Redundant circuit 217 Redundant address receiving circuit (serial receiving circuit)
218 Decoder 219 Serial transmission path 230 Serial data transmission / reception circuit 234-1 to 234-4 Latch circuit 236-1 to 236-4 Transmission register 237 H fixed data generator 238 H fixed data addition transmission register 239 one shot circuit 240 transmission register Unit 251 reception register unit 252-1 to 252-4 reception register 253 H fixed data reception register 256 transfer clock generation circuit 260 initial value setting signal 262 serial transfer clock (GCLK)
264 Clock 266 Data storage signal (FDFWZ)
268 Reception completion signal 314-1 to 314-4 Fuse 315 Redundant address transmission circuit 317 Redundant address reception circuit 319 Serial transmission path 330 Serial data transmission / reception circuit 334-1 to 334-4 Latch circuit 336-1 to 336-4 Transmission register 352 -1 to 352-4 Reception register 354 Serial transmission control circuit 356 Trigger signal generator 362 Serial transfer clock (GCLK)
364 clock

Claims (8)

Used in the semiconductor memory device to repair by replacing defective memory cells existing in the memory cell array to the redundancy memory cell, a serial receiving circuit that receives data transmitted serially including a redundant address of the redundant memory cell,
A reception register unit having a plurality of reception registers connected in series, sequentially inputting the serially transmitted data from the first-stage reception register based on a serial transfer clock, and shifting and outputting to the subsequent-stage reception register; ,
For fixed data that is connected to the reception register at the last stage of the reception register unit and outputs a reception completion signal by judging that reception of all data has been completed when fixed data is output from the reception register at the last stage A receive register;
A transfer clock generation circuit for stopping the output of the serial transfer clock after obtaining the reception completion signal from the fixed data reception register;
A serial reception circuit that completes reception of the data based on the reception completion signal. The plurality of reception registers and fixed data reception registers start an initial value setting operation for resetting register data when an initial value setting signal is input,
2. The transfer clock generation circuit starts output of the serial transfer clock after the input of the initial value setting signal and after the reception register and the fixed data reception register finish the initial value setting operation. The serial receiving circuit described in 1. Serial transmission circuit used in a semiconductor memory device for repairing a defective memory cell in a memory cell array by replacing it with a redundant memory cell, and generating and serially transmitting data with fixed data added to the head of the redundant address of the redundant memory cell And a serial data transmission / reception circuit including a serial reception circuit for receiving the data,
The serial receiving circuit is
A reception register unit having a plurality of reception registers connected in series, sequentially inputting the serially transmitted data from the first-stage reception register based on a serial transfer clock, and shifting and outputting to the subsequent-stage reception register; ,
For fixed data that is connected to the reception register at the last stage of the reception register unit and outputs a reception completion signal by judging that reception of all data has been completed when fixed data is output from the reception register at the last stage A receive register;
A transfer clock generation circuit for stopping the output of the serial transfer clock after obtaining the reception completion signal from the fixed data reception register;
A serial data transmitting / receiving circuit that completes reception of the data based on the reception completion signal. The plurality of reception registers and fixed data reception registers start an initial value setting operation for resetting register data when an initial value setting signal is input,
4. The transfer clock generation circuit starts outputting the serial transfer clock after the input of the initial value setting signal and after the reception register and the fixed data reception register finish the initial value setting operation. Serial data transmission / reception circuit described in 1. A one-shot circuit that generates a data storage signal that is set after the initial value setting signal is input and is reset before the serial transfer clock is output;
The serial transmission circuit includes:
A plurality of transmission registers connected in series, storing transmission data based on the data storage signal, sequentially shifting the stored transmission data based on the serial transfer clock, A transmission register section to output from
Connected to the last stage of the transmission register unit, stores fixed data based on the data storage signal, and sequentially outputs the stored fixed data and data output from the transmission register unit based on the serial transfer clock A fixed data addition transmission register for serial transmission of data with fixed data added to the head,
A serial data transmitting / receiving circuit according to claim 4. In a semiconductor memory device for repairing a defective memory cell existing in a memory cell array by replacing it with a redundant memory cell,
A redundant address transmission circuit that serially transmits the redundant address by inputting a conduction state or a cut state of the fuse set in which the redundant address of the redundant memory cell is specified by trimming, and is mounted in a region different from the fuse set. A redundant address receiving circuit that is present in the vicinity of the decoder of the memory cell array and that receives the redundant address serially transmitted by the redundant address transmitting circuit;
The redundant address transmission circuit is to generate and transmit data by adding fixed data to the beginning of the redundant address for serial transmission,
The redundant address receiving circuit includes:
A reception register unit having a plurality of reception registers connected in series, sequentially inputting the serially transmitted data from the first-stage reception register based on a serial transfer clock, and shifting and outputting to the subsequent-stage reception register; ,
For fixed data that is connected to the reception register at the last stage of the reception register unit and outputs a reception completion signal by judging that reception of all data has been completed when fixed data is output from the reception register at the last stage A receive register;
A transfer clock generation circuit for stopping the output of the serial transfer clock after obtaining the reception completion signal from the fixed data reception register;
A semiconductor memory device that completes reception of the data based on the reception completion signal. The plurality of reception registers and fixed data reception registers start an initial value setting operation for resetting register data when an initial value setting signal is input,
7. The transfer clock generation circuit starts outputting the serial transfer clock after the input of the initial value setting signal and after the receiving register and the fixed data receiving register finish the initial value setting operation. The semiconductor memory device described in 1. A one-shot circuit that generates a data storage signal that is set after the initial value setting signal is input and is reset before the serial transfer clock is output;
The serial transmission circuit includes:
A plurality of transmission registers connected in series, storing transmission data based on the data storage signal, sequentially shifting the stored transmission data based on the serial transfer clock, A transmission register section to output from
Connected to the last stage of the transmission register unit, stores fixed data based on the data storage signal, and sequentially outputs the stored fixed data and data output from the transmission register unit based on the serial transfer clock A fixed data addition transmission register for serial transmission of data with fixed data added to the head,
A semiconductor memory device according to claim 7.

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