JP4740693B2 - CCD drive circuit - Google Patents

Description

  The present invention relates to a drive circuit (drive IC) for a CCD (chargecoupled device) type solid-state imaging device, and more particularly to a CCD drive circuit having an overcurrent prevention function.

  2. Description of the Related Art Conventionally, in CCD area sensors used in digital still cameras, mobile phones, and the like, an electronic shutter that draws out electric charges accumulated in a photoelectric conversion element to a substrate is generally used as a method for setting an exposure time.

In such a CCD area sensor, a photodiode (charge storage region) and a charge transfer channel are formed in an n-type region in a p-type well formed in an n-type substrate NSUB. A structure similar to an npn bipolar junction transistor is formed in the substrate thickness direction. The n-type charge storage region corresponds to the emitter, the p-type well corresponds to the base, and the n-type substrate corresponds to the collector.
The p-type well is set to the ground potential, and a positive bias is applied to the n-type substrate. The height of the potential barrier formed by the p-type well is adjusted according to the magnitude of the substrate bias. Accordingly, the maximum (saturated) charge amount that can be accumulated in the n-type charge accumulation region constituting the potential well varies depending on the bias potential of the n-type substrate NSUB. The amount of saturation charge determines the amount of saturation light.

  When light exceeding the saturation light amount enters, the signal charge overflows and is absorbed by the substrate (overflow drain). Blooming is prevented by discharging (draining) the overflowing signal charges to the substrate. The lower the n-type substrate potential, the greater the saturated charge amount (saturated exposure amount), and the higher the n-type substrate potential, the lower the saturated charge amount (saturated exposure amount). When the n-type substrate potential is extremely increased, the potential barrier formed by the p-type well disappears, and all charges of the photodiode are discharged to the substrate.

  Utilizing the above characteristics, a high voltage is applied to the n-type substrate in the initial stage of exposure, an electronic shutter operation is performed, and the charges accumulated in the photodiode are discharged, and then the n-type substrate is predetermined. By returning to the overflow drain (OFD) voltage, an electronic shutter operation for starting charge accumulation in the photodiode is performed.

The n-type substrate potential during exposure is determined according to the amount of saturation charge that can be accumulated in the photodiode, and is designed to be about 10V. It has also been proposed to change the substrate bias in order to change the saturation charge amount between the still image mode and the case where pixel addition is performed in the vertical charge transfer channel in the moving image or monitor mode.
Further, the voltage applied when discharging unnecessary charges to the substrate in the electronic shutter operation is generated by superimposing an amplitude pulse of about 20 V on the voltage applied during exposure.

  The signal reading / transfer operation of the CCD area sensor is performed using, for example, three potentials: a positive high potential VH of about +15 V, a ground potential VM, and a negative high potential VL of about -8 V. Charge reading from the photodiode to the vertical charge transfer channel is performed using VH, and transfer in the vertical charge transfer channel is performed using VM and VL. An n-type substrate bias (OFD) voltage of about 10 V during exposure can be created using VH. A positive pulse of about 20 V for an electronic shutter can be created using VL and VH. The drive signal for the CCD area sensor is usually generated by a drive circuit formed on a chip separate from the CCD area sensor. Since the CCD area sensor and the CCD drive circuit handle bipolar voltages having a large absolute value as a semiconductor device, an unexpected overcurrent may flow.

  By the way, the area sensor can be driven by VH and VM without starting up the negative power source VL until the electronic shutter is driven. When starting up the negative power supply, inconvenience may occur due to the negative power supply and the n-type substrate of the CCD area sensor being coupled via a capacitor. For example, when a negative potential is applied to the n-type substrate of the CCD area sensor, the pn junction between the p-type well and the n-type substrate is biased in the forward direction, and an overcurrent may flow.

JP 2001-128073 A JP 2002-262186 A JP 2005-123712 A

  An object of the present invention is to provide a CCD drive circuit that performs a protection operation when a negative power supply is turned on and can suppress the possibility of an unexpected overcurrent.

According to one aspect of the present invention,
A p-type well is formed on an n-type substrate, a number of n-type regions constituting the photoelectric conversion element are formed in a matrix in the p-type well, and a high voltage pulse is applied to the n-type substrate to accumulate the photoelectric conversion element. A driving circuit for driving a CCD area sensor capable of performing an electronic shutter operation for extracting charges to an n-type substrate and then performing an exposure by adjusting an amount of saturated light by applying an overflow drain voltage to the n-type substrate;
A positive power supply for generating a positive high voltage;
An overflow drain voltage generation circuit that generates an overflow drain voltage using the positive high voltage;
An overflow drain voltage output node that receives the overflow drain voltage and can supply it to the outside;
A backflow prevention element connected between the overflow drain voltage generation circuit and the overflow drain voltage output node;
A negative power supply that generates negative high voltage,
Using the negative high voltage and the positive high voltage, a pulse voltage used for driving an electronic shutter of a CCD area sensor is generated, the pulse voltage is output from a pulse voltage output terminal, and the overflow drain is connected via a capacitor. A p-channel MOS coupled to a voltage output node and capable of superimposing the pulse voltage on the overflow drain voltage , wherein the pulse voltage is formed on the same silicon substrate and can form a thyristor structure parasitically A clock driver generated by a serial connection including a transistor and an n-channel MOS transistor ;
A first protection circuit connected between the overflow drain voltage output node and the ground node, and capable of connecting both nodes with low impedance;
A second protection circuit connected between the overflow drain voltage output node and the ground node and capable of connecting both nodes with high impedance;
A CCD driving circuit is provided.

  According to the present invention, it is possible to provide a CCD drive circuit that performs a protection operation when a negative power supply is turned on and can suppress the possibility of an unexpected overcurrent.

  FIG. 1 is a block diagram of a solid-state imaging module 1 according to an embodiment of the present invention. The solid-state imaging module 1 includes at least a CCD area sensor 2 and a drive circuit 3. In the CCD area sensor 2, a p-type well 12 is formed on an n-type silicon substrate 11, and n-type charge storage regions (photodiodes) 13 are formed in a matrix on the p-type well 12, along each column of the photodiodes. An n-type vertical charge transfer channel 14 is formed. A p-type channel stopper 16 is formed between the columns. The surface of the n-type charge accumulation region 13 is covered with the p-type buried region 17. A charge transfer electrode 15 made of polycrystalline silicon is disposed via an insulating film so as to intersect the vertical charge transfer channel 14. For example, a four-phase drive signal φVi is applied to the charge transfer electrode 15. High-concentration n-type contact regions 18 and p-type contact regions 19 are formed in the n-type substrate 11 and the p-type well 12, respectively. The p-type well 12 is grounded via the contact region 19. The n-type contact region 18 is connected to the OFD terminal and is applied with the substrate bias voltage OFD. This configuration is well known, and various known modifications, substitutions, additions, improvements, and the like can be made.

The drive circuit 3 has an n-type substrate bias voltage generation function of the CCD area sensor. The control circuit 20 performs overall control of the drive circuit. The positive power supply 28 and the negative power supply 29 are controlled by the control circuit 20. The timing generator 21 generates control signals A, B, prot1, and prot2. The timing generator 21 uses the positive power supply voltage VH, the ground potential, and the negative power supply voltage VL as power supply voltages.
The OFD voltage generation circuit 23 is connected between the positive power supply voltage VH and the ground voltage, and outputs an overflow drain voltage that is substantially the same as the input reference voltage VI. The overflow drain voltage is supplied to the output terminal OFDO via the analog switch S1. The analog switch S1 is controlled to be turned on / off by the control signal B.
The clock driver 24 includes a p-channel MOS transistor M10 and an n-channel MOS transistor M11 connected in series between a positive power supply voltage VH and a negative power supply voltage VL, an interconnection point connected to the output terminal SUBO, and a common input terminal. A control signal A is received. By using VH (= 15 V) and VL (= −8 V) as power sources, an output amplitude exceeding 20 V can be obtained. Therefore, it is desirable that the control signal also has a low level of VL and a high level of VH, and VL is also used as the power source of the timing generator 21.

  The control signal A is normally high H and the n-channel MOS transistor M11 is turned on and outputs VL. Only when a pulse is generated, the control signal A temporarily becomes low L and the p-channel MOS transistor M10 is turned on and VH is output. Generate sex pulses. The reference potential of the pulse is VL. The output terminal SUBO and the output terminal OFDO are coupled via a capacitor C0. A positive pulse voltage is superimposed on the potential of the output terminal OFDO. At this time, since the potential of OFDO becomes higher than VH, the current flows backward from OFDO to the positive power supply VH as it is. Therefore, the analog switch S1 is turned off, and the OFD voltage generation circuit 23 is electrically disconnected from the output terminal OFDO.

  The negative power supply VL is started up with a delay from the positive power supply VH. Until the negative power supply is started, the ground potential is supplied instead of VL. The control signal A is normally high, and the n-channel MOS transistor M11 is on. Therefore, the ground potential is supplied to the output terminal SUBO. If the SUBO potential remains at the ground potential, a pulse height exceeding 20 V cannot be generated. The potential of SUBO needs to be about -8V.

It is assumed that the reference voltage VI is still 0V and the output terminal OFDO is also 0V. When the negative power supply is turned on, the output potential of the clock driver 24 changes from the ground potential toward the negative power supply voltage VL. This negative potential change is transmitted to the n-type substrate 11 of the CCD area sensor 2 via the capacitor C0. Then, in the CCD area sensor 2, the pn junction between the p-type well 12 and the n-type substrate 11 is forward-biased, and a forward overcurrent may flow. Therefore, a protection circuit 25 that clips the substrate bias of the CCD area sensor 2 to the ground potential is provided.
The output terminal OFDO is coupled to ground through a protection circuit 27 that includes a parallel connection of the first protection circuit 25 and the second protection circuit 26. The first protection circuit 25 includes a low-resistance series resistance of about 30Ω, for example, and includes a transistor M1 whose on / off is controlled by a control signal prot1. By turning on the MOS transistor M1, the n-type substrate 11 of the CCD area sensor is clipped to the ground potential with a low resistance. The second protection circuit 26 is provided for another purpose, and has a series resistance that is two to three digits higher than that of the first protection circuit 25, for example, 3 kΩ to 30 kΩ. The second protection circuit 26 includes, for example, a series connection of a resistor R0 and a switch S2 whose on / off is controlled by a control signal prot2. Switch S2 is typically formed of a MOS transistor.

  FIG. 2A shows a configuration example of the protection circuit 27 and the clock driver 24 of the drive circuit chip. N-type wells NWL1 and NWL2 are formed in a p-type silicon substrate 31, and p-type wells PWL1 and PWL2 are formed therein. The n-type wells NWL1 and NWL2 may be integrated wells. In the p-type well PWL1, a gate electrode 36 is formed above the channel region of the transistor M2, and n-type source / drain regions 32 and 33 are formed on both sides of the gate electrode 36 with the channel region interposed therebetween. A gate electrode 37 is also formed above the channel region of the transistor M1, and n-type source / drain regions 34 and 35 are formed on both sides of the gate electrode 37 with the channel region interposed therebetween.

  N-type well NWL1 is connected to positive power supply voltage VH through contact region 38, and p-type well PWL1 is connected to ground voltage GND through contact region 39. Source regions 33 and 35 of transistors M1 and M2 are connected to ground potential GND. The transistor M1 drain region 34 is directly connected to the OFDO terminal. The drain region 32 of the transistor M2 is connected to the OFDO terminal via the polysilicon resistor 38.

  The clock driver 24 includes a series connection of a p-channel MOS transistor M10 formed in the n-type well NWL2 and an n-channel MOS transistor M11 formed in the p-type well PWL2. A polysilicon gate electrode 44 is formed above the n-type well NWL2 via a gate insulating film, p-type source / drain regions 42 and 43 are formed in the wells on both sides thereof, and above the p-type well PWL2 A polysilicon gate electrode 47 is formed through the gate insulating film, and n-type source / drain regions 45 and 46 are formed in the wells on both sides thereof. An n-type contact region 41 and a p-type contact region 48 are formed in the n-type well NWL2 and the p-type well PWL2, respectively.

  The drain regions 43 and 45 of both transistors are connected to each other and connected to the output terminal SUBO. Source region 42 and well contact region 41 of p-channel MOS transistor M10 are connected to positive power supply voltage VH. Source region 46 and well contact region 48 of n-channel MOS transistor M11 are connected to negative power supply voltage VL.

  The p-type regions 42 and 43, the n-type well NWL2, the p-type well PWL2, and the n-type regions 45 and 46 constituting the clock driver 24 constitute a pnpn structure and can form a thyristor structure. When the thyristor latches up, it can be destroyed.

  As shown in FIG. 2B, it is assumed that the potential of the output terminal SUBO decreases and a forward current flows through the pn junction around the n-type region 45. When the NPN bipolar junction transistor NPN1 is turned on and the emitter-collector current flows, the collector (n-type well) potential also decreases.

  As shown in FIG. 2C, when the n-type well potential decreases, the base potential of the PNP bipolar junction transistor PNP1 decreases, and the emitter-base junction is forward biased. When PNP1 is turned on and a current flows, the collector (p-type well) potential is raised.

  As shown in FIG. 2D, when the potential of the p-type well PWL2 rises, the base potentials of NPN1 and NPN2 rise to forward bias the emitter-base junction. When NPN1 and NPN2 are further turned on, the collector (n-type well) potential is lowered. If positive feedback is applied in this way, latch-up occurs.

  Even if the latch-up does not occur, a noise current flows, so that the power supply potentials VH and VL become unstable and adversely affect other circuits.

  FIG. 3A shows a timing chart of the negative power supply startup. In the figure, the horizontal axis represents the time axis, and the vertical axis represents the potential. The control signals prot1, prot2, negative power supply VL, clock driver output SUBO, OFD potential output OFDO, and control signal B are shown at the same timing. When the start-up of the negative power supply VL starts, the potential of VL changes from 0V to -8V. Prior to the start-up of the negative power supply VL, the control signal prot1 is made high, and the transistor M1 of the first protection circuit 25 is turned on. When the transistor M1 of the first protection circuit 25 is turned on, the output terminal OFDO is clipped to the ground potential.

  Prior to the period T1, the analog switch S2 of the second protection circuit 26 is closed (turned on) by the control signal prot2 and the analog switch S1 is opened by the control signal B at the timing of turning on the transistor M1 of the first protection circuit 25. (Off). A high resistance R0 is connected between the output terminal OFDO and the ground potential. The OFD voltage generation circuit 23 is electrically disconnected from the output terminal OFDO.

  In the initial state, the negative power supply VL has not yet risen and is 0V. The reference potential VI is 0V, and the potential of the output terminal OFDO is also 0V. In the clock driver 24, the control signal A is in the high H state, and the transistor M11 is on. The negative power supply potential is 0V. Therefore, the output SUBO of the clock driver is also 0V. When the control signal prot2 is set high to turn on the analog switch S2 of the second protection circuit 26 and the output terminal OFDO is connected to the ground with a high resistance, the period T1 before the first protection circuit 25 is turned on. The ground potential is connected. When the control signal B is set to low and the analog switch S1 is turned off, the OFD voltage generation circuit with an output of 0 V is disconnected from the output terminal OFDO. However, no change occurs.

  After the period T1, the control signal prot1 becomes high, the output terminal OFDO is connected to the ground with a low resistance, and then the negative power supply VL is raised. As the negative power supply changes from 0V to -8V, the output SUBO of the clock driver also changes from 0V to -8V. Due to the capacitive coupling, the potential of OFDO coupled to SUBO also attempts to change. However, since the potential is clipped to the ground potential by the transistor M1 of the protection circuit 25, the change is suppressed. The transistor M1 of the protection circuit having a lower resistance than the transistor M11 of the clock driver 24 becomes dominant, and is suppressed to a constant potential difference. Overcurrent flows in the area sensor by setting the on-resistance of the transistor M1 low so that the drop voltage ΔVo is smaller than the forward breakdown voltage Vbj ′ of the pn junction between the p-type well and the n-type substrate of the area sensor. Can be suppressed. In this negative power supply startup operation, the second protection circuit 26 does not actively contribute.

  FIG. 3B shows a case where the protection operation occurs when the negative power supply VL rises, the reference voltage to the OFD voltage generation circuit 23 is also a normal value, and the high voltage VH ′ (about 10 V) is supplied to OFDO. Show. This is usually an unexpected behavior, but it cannot be said that there is no possibility. If such an operation occurs without the second protection circuit 26, the following occurs.

  The first protection circuit 25 connects OFDO to the ground potential with a low resistance. The potential of OFDO suddenly drops from about 10V toward the ground potential, and this voltage drop is transmitted to the output terminal SUBO of the clock driver via the capacitor C0. As described with reference to FIGS. 2B to 2D, when the potential of SUBO decreases, latchup may occur. If latch-up occurs, the CCD drive circuit may be destroyed. Hereinafter, an operation when the second protection circuit 26 is provided will be described.

  Prior to turning on the first protection circuit 25, the second protection circuit 26 is turned on, and a high resistance is connected between OFDO and the ground potential. The OFDO terminal and the OFD voltage generation circuit 23 are disconnected. The output terminal OFDO of the high voltage VH ′ (and the n-type substrate 11 of the CCD area sensor 2) is connected to the ground potential through the high resistance and gradually discharges. The potential of OFDO gradually goes to the ground potential. Since the potential change is gradual, the potential change experienced by SUBO via the capacitor is also small. If the impedance of the protection circuit 26 is set so that the drop potential ΔVs is smaller than the forward breakdown voltage Vbj of the drain pn junction of the transistor M11, it is possible to prevent a forward current from flowing through the pn junction. The period T1 is selected so that the protective circuit 25 is turned on after a sufficient potential drop occurs. Since the OFD voltage generation circuit 23 is electrically disconnected by turning off the analog switch S1, unnecessary through current can be prevented.

  In addition, although the case where the high impedance 2nd protection circuit was comprised by resistance and a switching transistor was demonstrated, it can also implement | achieve in another form.

  FIG. 4A shows a case where the second protection circuit 26 is also composed of a single transistor M2 like the first protection circuit 25. A region covered with the gate electrode G between the source S and the drain D is a channel. The length in the source-drain direction is the channel length L, and the length in the intersecting direction is the channel width W. The impedance can be selected by the ratio L / W of the channel length L and the channel width W. For example, if the active region has a long and narrow rectangular shape and a current flows along the long side, the on-resistance increases. If a current flows along the short side, the on-resistance decreases. The transistor M1 constituting the low-resistance first protection circuit 25 has a small channel length / channel width ratio L1 / W1 as shown on the right side in the figure, and the transistor M2 constituting the high-resistance second protection circuit 26 is As shown on the left side of the figure, the channel length / channel width ratio L2 / W2 is set large. For example, if the channel length / channel width ratio L1 / W1 = 0.1 of M1 and the channel length / channel width ratio L2 / W2 = 10 of M2, resistance values different by about two digits can be obtained. If the difference is further increased, a different resistance value can be obtained.

  FIG. 4B shows a configuration in which the on-resistance is increased by setting the gate voltage low. The drain of the transistor M2 is connected to OFDO of about 10V, but the gate electrode is controlled by the output n1 of the buffer driver 46 that performs level shift. The buffer driver 46 is driven by using the power supply voltage VH1 which turns on the transistor M2 with the control signal prot2 as an input signal. Therefore, even if the output n1 becomes high, the transistor M2 is turned on in a high impedance state, and its on-resistance is high.

  FIG. 4C shows a form in which the current value is limited. The gate and drain of n-channel transistor M21 are directly connected (node n2) and connected to constant current source 47. The source of the transistor M21 is connected to the ground potential. Another n-channel transistor M24 is connected between output terminal OFDO and the ground potential, and the gate is connected to node n2 via analog switch S21 and to the ground potential via n-channel MOS transistor M25. The analog switch S21 and the transistor M25 are complementarily controlled by a control signal (prot2) and its complementary signal (-prot2). When the protect operation is turned on, the switch S21 is closed (turned on) to form a current mirror. A current proportional to the size of the transistors M21 and M24 flows. A current substantially equal to the current flowing through the transistor M24 flows from the negative power supply ground potential to the output terminal SUBO through the transistor M11 of the clock driver 24. The size of the transistor M22 is set so that the SUBO drop voltage at this time becomes a current value i0 smaller than the forward breakdown voltage of M11. When the current value of the constant current source 47 is i1, the size of the transistor M24 is obtained by multiplying the size of the transistor M21 by i0 / i1. If the switch S21 is turned off and the transistor M25 is turned on, the transistor M24 is turned off and the protection operation is turned off.

  4D shows a configuration in which a plurality of transistors M2_1, M2_2,... M2_n are connected in series to increase the on-resistance. Even for a transistor that is insufficient for a desired on-resistance, a desired high resistance is realized by connecting a plurality of transistors in series.

  FIG. 4E shows another embodiment for realizing a high impedance load with a constant current element. The constant current source 47 and the transistors M21 and M22 are the same as in FIG. 4C, and the node n2 is directly connected to the gate of the transistor M22. Another n-channel transistor M23 is connected between the transistor M22 and the OFDO terminal, and ON / OFF is controlled by the control signal prot2. The sum of the on-resistances of the transistors M22 and M23 is the on-resistance of the protection circuit 25. The operation is the same as that of the circuit of FIG. 4C.

  Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. For example, the reference voltage VI of the OFD voltage generation circuit may be formed in any way. Individual differences can be suppressed by using a resistance bleeder formed in the area sensor as in Patent Document 2. By selecting from a plurality of values, it is possible to realize a saturation charge amount according to the mode. The illustrated numerical values are not limited at all, and can be variously changed according to the purpose and conditions. It will be apparent to those skilled in the art that other various modifications, improvements, combinations, and the like can be made.

1 is a block diagram of a solid-state imaging module 1 according to an embodiment of the present invention. FIG. 2 is a schematic cross-sectional view showing a configuration example of a CCD drive circuit 2 according to an embodiment of the present invention, and an equivalent circuit diagram showing a latch-up operation. It is a timing chart which shows the timing at the time of negative power supply starting, and the timing at the time of an unexpected protection operation | movement. It is an equivalent circuit diagram which shows the modification of a 2nd protection circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Solid-state imaging module, 2 ... CCD area sensor, 3 ... CCD drive circuit, 11 ... n-type silicon substrate (NSUB), 12 ... p-type well (PWL), 13 ... n-type charge storage area, 14 ... n-type charge Transfer channel, 15 ... (polysilicon) transfer electrode, 16 ... p-type channel stopper, 17 ... p-type buried region, 20 ... control circuit, 21 ... timing generator, 23 ... OFD voltage generation circuit, 24 ... clock driver, 25 ... 1st protection circuit, 26 ... 2nd protection circuit, 27 ... Protection circuit, 28 ... Positive power supply, 29 ... Negative power supply, S ... Switch, M ... Transistor

Claims (10)

A p-type well is formed on an n-type substrate, a number of n-type regions constituting the photoelectric conversion element are formed in a matrix in the p-type well, and a high voltage pulse is applied to the n-type substrate to accumulate the photoelectric conversion element. A driving circuit for driving a CCD area sensor capable of performing an electronic shutter operation for extracting charges to an n-type substrate and then performing an exposure by adjusting an amount of saturated light by applying an overflow drain voltage to the n-type substrate;
A positive power supply for generating a positive high voltage;
An overflow drain voltage generation circuit that generates an overflow drain voltage using the positive high voltage;
An overflow drain voltage output node that receives the overflow drain voltage and can supply it to the outside;
A backflow prevention element connected between the overflow drain voltage generation circuit and the overflow drain voltage output node;
A negative power supply that generates negative high voltage,
Using the negative high voltage and the positive high voltage, a pulse voltage used for driving an electronic shutter of a CCD area sensor is generated, the pulse voltage is output from a pulse voltage output terminal, and the overflow drain is connected via a capacitor. A p-channel MOS coupled to a voltage output node and capable of superimposing the pulse voltage on the overflow drain voltage, wherein the pulse voltage is formed on the same silicon substrate and can form a thyristor structure parasitically A clock driver generated by a serial connection including a transistor and an n-channel MOS transistor ;
A first protection circuit connected between the overflow drain voltage output node and the ground node, and capable of connecting both nodes with low impedance;
A second protection circuit connected between the overflow drain voltage output node and the ground node and capable of connecting both nodes with high impedance;
CCD drive circuit having 2. The CCD drive circuit according to claim 1, further comprising a timing generator for generating control signals for the clock driver, the first protection circuit, and the second protection circuit. And a control circuit for controlling the start-up of the negative power supply, wherein the timing generator turns on the second protection circuit prior to the start-up of the negative power supply, and then turns on the first protection circuit. The CCD driving circuit according to claim 2, which generates a signal. The backflow prevention element has an analog switch, the timing generator also generates a control signal for the analog switch, turns off the analog switch prior to the start-up of the negative power supply, and turns on the second protection circuit The CCD driving circuit according to claim 3, wherein: The clock driver is connected between the positive and negative supply, the p includes channel MOS transistor and a series connection of the n-channel MOS transistors, said control circuit launched the positive power supply to the first, the negative supply 5. The CCD drive circuit according to claim 3, wherein the negative power supply is raised at a ground potential and when the electronic shutter is operated. The first protection circuit has a MOS transistor whose channel width / channel length ratio is a first value, and the second protection circuit is a second value whose channel width / channel length ratio is smaller than the first value. 6. The CCD driving circuit according to claim 1, further comprising a MOS transistor. 6. The CCD drive circuit according to claim 1, wherein the second protection circuit includes a level shifter that reduces a logic amplitude, and a MOS transistor to which an output of the level shifter is applied to a gate. The second protection circuit, saw including a series connection of a plurality of MOS transistors having an on-resistance, combined resistance of the on-resistance, latch-up in the p-channel and n-channel MOS transistors may form the thyristor structure results resistance 6. The CCD drive circuit according to claim 1, wherein the resistance value is larger than the value . The CCD driving circuit according to claim 1, wherein the second protection circuit includes a series connection of a MOS transistor functioning as a switch and a constant current source. 6. The second protection circuit includes a MOS transistor having a constant current smaller than a current that causes latch-up in a p-channel and an n-channel MOS transistor capable of forming the thyristor structure when the second protection circuit is turned on. The CCD drive circuit according to any one of the preceding claims.

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