JP4742311B2 - OFDM receiving apparatus and OFDM receiving method - Google Patents

Description

  The present invention relates to an OFDM receiving apparatus and an OFDM receiving method.

  Conventionally, in terrestrial digital broadcasting, an OFDM (Orthogonal Frequency Division Multiplexing) system capable of multiplexing and transmitting and receiving a plurality of signals is used as a modulation system. In this OFDM system, a number of orthogonal subcarriers (carriers) are provided in a transmission band, data is allocated to the amplitude and phase of each carrier, and digital modulation is performed by PSK (Phase Shift Keying) or QAM (Quadrature Amplitude Modulation). It is a method.

An OFDM signal modulated by the OFDM scheme is transmitted in transmission units called OFDM symbols. One symbol includes an effective symbol that is a signal that has been subjected to IFFT (Inverse Fast Fourier Transform) and a guard interval that is a copy of the signal in the latter half of the effective symbol.
An OFDM signal receiving apparatus generates an FFT window pulse indicating an FFT window position for specifying an effective symbol from the received signal, specifies an effective symbol based on the FFT window pulse, and performs an FFT process on the received signal. It was.

As a technique for receiving a digital broadcast signal employing such an OFDM system, a plurality of antennas are connected to a receiving device, and a received signal is selected or synthesized according to the received electric field strength of the signal received by each antenna. Diversity reception technology is known.
For example, it has two antennas and determines whether the received signal strength (RSSI: Receive Signal Strength Indicator) of subcarriers (multiple carriers) received by one antenna is lower than a threshold value. Is disclosed that switches to the other antenna when the number of low subcarriers exceeds a certain number (see Patent Document 1).
JP 2005-236666 A

  However, in the diversity configuration in which the antenna is switched according to the received electric field strength of the received signal and the received signal is selected or combined, even if the received electric field strength is kept good by switching the receiving antenna, a large amount of noise In some cases, the reception signal level is increased by the component, and the reception electric field strength is apparently kept good, but the reception quality such as the C / N (Carrier to Noise) value is actually lowered.

  Further, in the configuration in which the antenna is switched according to the received electric field strength, the optimum FFT window position of the received signal received by each antenna may differ depending on the reception characteristics of each antenna. In this case, a symbol extracted based on the FFT window may not be an effective symbol.

  In the conventional configuration, the antenna switching operation and the FFT window position setting operation are independent of each other. For this reason, in a receiving apparatus that does not always perform FFT window position setting, such as a configuration that performs FFT window position setting only once at start-up or at regular intervals, etc., FFT window position setting is immediately performed when switching antennas. There was a risk of not being done. In this case, there is a problem that after the antenna switching, accurate reception cannot be performed until the FFT window position is set to an optimum position.

  Further, although a receiving device for demodulating a received signal by using a plurality of systems with a tuner and a demodulating unit including an FFT window position setting unit for each antenna can be considered, there is a problem that it is very expensive.

  An object of the present invention is to optimally set the FFT window position when switching a receiving antenna in a configuration in which a plurality of antennas are switched and a received signal received by a single receiving circuit is demodulated.

In order to solve the above problem, an OFDM receiver according to claim 1 of the present invention (for example, the OFDM signal demodulation circuit 100 of FIG. 1) includes:
A plurality of antenna connection terminals (for example, antenna connection terminals 112 and 113 in FIG. 1) to which an antenna can be connected are provided, and one antenna connection terminal is selected from the plurality of antenna connection terminals to switch the antenna to be received. Antenna switching means (for example, the antenna switching circuit 12 of FIG. 1);
Reception quality detection means (for example, reception quality detection circuit 18 in FIG. 1) for detecting the reception quality of the OFDM signal received by the antenna connected to one antenna connection terminal selected by the antenna switching means;
Antenna switching control means (for example, the antenna control circuit 30 in FIGS. 1 and 2) for controlling the antenna switching means so as to switch the antenna to be received based on the reception quality detected by the reception quality detection means;
FFT window pulse generation means for generating an FFT window pulse based on an OFDM signal received by an antenna connected to one antenna connection terminal selected by the antenna switching means (for example, FFT window pulse generation circuit 22 in FIG. 1). )When,
Storage means (for example, the first register 24 in FIG. 1) for storing position data indicating the position of the FFT window pulse generated by the FFT window pulse generation means while updating the position data in association with each of the receiving antennas;
As said by the antenna switching control means only when the control of switching the antenna is made reading the position data corresponding to the antenna after switching from said memory means, for generating an FFT window pulse based on the read out position data FFT window pulse generation control means for controlling the FFT window pulse generation means (for example, FFT window pulse generation circuit 22 in FIG. 1),
FFT processing means (for example, FFT processing circuit 23 in FIG. 1) that performs FFT processing on the received OFDM signal using the FFT window pulse generated by the FFT window pulse generation means and outputs an FFT signal. It is characterized by.

The OFDM reception method according to claim 2 (for example, the FFT processing method of the OFDM signal demodulation circuit 100 in FIG. 1)
An antenna switching step (for example, the antenna switching circuit of FIG. 1) for switching the antenna to be received by selecting one antenna connection terminal from the antenna connection terminals (for example, the antenna connection terminals 112 and 113 of FIG. 1) to which the antenna can be connected 12, step ST16 in FIG. 6),
A reception quality detection step (for example, reception quality detection circuit 18 in FIG. 1, step in FIG. 6) for detecting the reception quality of the OFDM signal received by the antenna connected to one antenna connection terminal selected in this antenna switching step. ST12)
An antenna switching control step (for example, the antenna control circuit 30 in FIGS. 1 and 2, the step in FIG. 6) that controls the antenna switching step so as to switch the antenna to be received based on the reception quality detected by the reception quality detection step. ST14, ST16),
An FFT window pulse generation step (for example, FFT window pulse generation circuit 22 in FIG. 1) that generates an FFT window pulse based on an OFDM signal received by an antenna connected to one antenna connection terminal selected in the antenna switching step. )When,
A storage step (for example, the first register 24 in FIG. 1 ) stores position data indicating the position of the FFT window pulse generated by the FFT window pulse generation step in the storage device while updating the position data in association with each antenna being received . )When,
As said the antenna switching control process only when the control is made to switch the antenna reads the position data corresponding to the antenna after switching from said storage device, it generates an FFT window pulse based on the read out position data FFT window pulse generation control step (for example, FFT window pulse generation circuit 22 in FIG. 1, steps ST23 to ST25 in FIG. 6) for controlling the FFT window pulse generation step,
An FFT processing step (for example, FFT processing circuit 23 in FIG. 1) that performs FFT processing on the received OFDM signal using the FFT window pulse generated by the FFT window pulse generation step and outputs an FFT signal. It is characterized by.

According to the present invention, in a configuration in which a received signal is demodulated by one system, the antenna to be received can be switched based on the reception quality, and at the time of antenna switching, the position data of the FFT window position corresponding to the antenna after switching is changed. An FFT window pulse is generated based on the FFT processing. Thereby, even if antenna switching is performed, good reception can be maintained without deteriorating C / N.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred first and second embodiments of the invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the illustrated example.

(First embodiment)
A first embodiment according to the present invention will be described with reference to FIGS. FIG. 1 shows a functional configuration of receiving apparatus 1 according to the present embodiment.

  First, the functional configuration of the receiving apparatus 1 will be described with reference to FIG.

  The receiving device 1 is a receiving device that receives an OFDM signal transmitted by IFFT processing of digital TV broadcast transmission data at a transmitter (not shown), and performs FFT processing on the OFDM signal to demodulate the transmission data. .

  As shown in FIG. 1, the receiving apparatus 1 includes external antennas 2 and 3 and an OFDM signal demodulation circuit 100. The OFDM signal demodulation circuit 100 includes antenna connection terminals 112 and 113, an antenna switching circuit 12, a tuner circuit 13, an AD (Analog Digital) converter 14, an FFT (Fast Fourier Transform) control circuit 20, The transmission path equivalent circuit 15, the demodulation circuit 16, the error correction circuit 17, the reception quality detection circuit 18, and the antenna control circuit 30 are configured, for example, formed by a semiconductor integrated circuit.

  As shown in FIG. 1, the antennas 2 and 3 receive digital broadcast OFDM signals and output electrical signals. The antennas 2 and 3 are preferably provided at physically different positions. The antenna connection terminal 112 connects the antenna 2. The antenna connection terminal 113 connects the antenna 3. The antenna switching circuit 12 switches the receiving antenna at the antennas 2 and 3 by switching the antenna connection terminals 112 and 113 to receive based on the signal S3 output from the antenna control circuit 30.

  The tuner circuit 13 receives an electrical signal output from the receiving antenna 2 or 3, performs amplification, conversion to an intermediate frequency signal, gain control, and the like on the electrical signal, and tunes to a desired broadcast wave frequency. Do. The AD converter 14 converts the analog signal output from the tuner circuit 13 into a digital signal and outputs the digital signal.

  The FFT control circuit 20 performs FFT processing on the digital signal input from the AD converter 14 based on the signal S4 indicating the antenna switching state input from the antenna control circuit 30, and outputs the result as an FFT signal.

  The transmission line equivalent circuit 15 performs waveform equivalent (amplitude equivalent and phase equivalent) processing on the FFT signal output from the FFT control circuit 20. In the signal received by the receiving apparatus 1, a synchronization signal (referred to as “scattered pilot signal”, hereinafter referred to as “SP signal”) having a predetermined amplitude and phase is embedded in the symbol in advance. . The transmission path equivalent circuit 15 estimates the characteristics of the transmission path by monitoring the amplitude and phase of the SP signal, and performs waveform equalization of the received signal based on the estimated characteristics of the transmission path.

  The demodulation circuit 16 performs demodulation processing on the signal output from the transmission line equivalent circuit 15. The error correction circuit 17 performs error correction processing on the signal output from the demodulation circuit 16 and outputs the signal to the outside of the receiving apparatus 1 as a TS (Transport Stream). The TS is output after being subjected to a predetermined decoding process by a decoding circuit (not shown). The output signal is displayed and output as a television broadcast by a display unit and an audio output unit (not shown).

  The reception quality detection circuit 18 includes a synchronization signal extraction circuit 181. The synchronization signal extraction circuit 181 extracts an SP signal as a synchronization signal from the FFT signal output from the FFT control circuit 20. The reception quality detection circuit 18 calculates a C / N value, which will be described later, using the SP signal extracted by the synchronization signal extraction circuit 181 and outputs it as reception quality S1. The reception quality is not limited to the C / N value.

  The antenna control circuit 30 generates signals S3 and S4 indicating the antenna switching state (antenna identification information after switching) based on the reception quality S1 output from the reception quality detection circuit 18, and generates the antenna switching circuit 12 and the FFT. Output to the control circuit 20.

  Next, a detailed configuration of the FFT control circuit 20 will be described. The FFT control circuit 20 includes a peak detection circuit 21, an FFT window pulse generation circuit 22, an FFT processing circuit 23, and a first register 24.

  The peak detection circuit 21 receives the digital signal output from the AD converter 14, generates a delay signal obtained by delaying the digital signal by an effective symbol, calculates an autocorrelation value between the original digital signal and the delay signal, The autocorrelation value is integrated, and the peak value of the integration value is output. The timing at which this peak value is output indicates the head position of each symbol, that is, the pulse position of the guard interval.

  Based on the peak value output from the peak detection circuit 21, the FFT window pulse generation circuit 22 generates and outputs an FFT window pulse that sets a range in which no intersymbol interference occurs to a high state.

  The FFT window pulse generation circuit 22 has a function of executing a first FFT process described later. The position data of the FFT window position of the antenna is stored in the first register 24 at a predetermined period, and at the time of antenna switching (only when), based on the signal S4 output from the antenna control circuit 30, the first register 24 Of the stored position data of the FFT window position corresponding to the antenna after switching, the value of the position data immediately before switching the antenna is read, and the FFT window is sent to the FFT window pulse generation circuit 22 based on the value of the position data immediately before that. Generate a pulse.

  The FFT processing circuit 23 performs FFT processing on the FFT window pulse range of the digital signal (OFDM time domain signal) output from the AD converter 14 based on the FFT window pulse output from the FFT window pulse generation circuit 22. Let it be an FFT signal (OFDM frequency domain signal). The FFT processing circuit 23 outputs the FFT signal to the transmission line equivalent circuit 15 and the reception quality detection circuit 18.

  The first register 24 stores the position data of the FFT window pulse position updated at a predetermined cycle in an updatable manner. This position data is stored separately by the antennas 2 and 3 one by one, and is overwritten and updated when newly stored. That is, the first register 24 always stores position data indicating the latest position of the FFT window pulse corresponding to the antennas 2 and 3.

  Next, a detailed configuration of the antenna control circuit 30 will be described with reference to FIG. FIG. 2 shows an internal configuration of the antenna control circuit 30.

  The antenna control circuit 30 includes a comparator 31, a control circuit 32, a second register 33, and a third register 34.

  The comparator 31 compares the reception quality S1 output from the reception quality detection circuit 18 with the reception quality read from the second register 33, and outputs a signal S2 as a result of the comparison. Based on the signal S2 output from the comparator 31 and the reception antenna identification information stored in the third register 34, the control circuit 32 indicates the antenna switching timing and the reception antenna identification information after switching. The signals S3 and S4 are output, the reception antenna identification information after switching is stored in the third register 34, and the reception quality S1 is stored in the second register 33.

  For example, the signals S3 and S4 are binary signals, and the antenna 2 corresponds to the low voltage of the signal S3, and the antenna 3 corresponds to the high voltage. That is, the inversion of the signal S3 indicates the switching timing of the antennas 2 and 3, and the voltage levels of the signals S3 and S4 indicate the identification of the antenna 2 or 3 being received.

  The second register 33 stores the reception quality S1 output from the control circuit 32. The third register 34 stores the switched antenna identification information output from the control circuit 32.

  Next, a specific example of peak value detection in the peak detection circuit 21 will be described with reference to FIG. FIG. 3A shows an OFDM signal 200 to be received. FIG. 3B shows a delayed signal 210 of the OFDM signal 200. FIG. 3C shows the correlation value 220 of the OFDM signal. FIG. 3D shows the integral value of the correlation value 220.

  As shown in FIG. 3A, the OFDM signal 200 received by the receiving apparatus 1 includes a plurality of OFDM symbols. Each OFDM symbol has a guard interval 202 and a valid symbol 203. The effective symbol 203 includes transmission data. The guard interval 202 is generated by copying the terminal part 201 in the OFDM symbol to the head of the effective symbol 203.

  As shown in FIG. 3B, the peak detection circuit 21 generates a delay signal 210 obtained by delaying the OFDM signal 200 by the effective symbol 203, and the correlation value between the OFDM signal 200 and the delay signal 210. (Autocorrelation value) 220 is calculated. The termination part 201 of the OFDM signal 200 and the guard interval 202 of the delayed signal 210 are the same signal. For this reason, the peak detection circuit 21 calculates a correlation value 220 as shown in FIG. Then, the peak detection circuit 21 calculates an integral value 230 of the correlation value 220 and outputs a peak value of this integral value.

  The example illustrated in FIG. 3 is an ideal case where the received OFDM signal does not include a delayed wave from a reference wave such as a reflected wave. If the received OFDM signal includes a delayed wave from a reference wave, such as a reflected wave, the peak value decreases.

  Next, an example of the FFT window pulse corresponding to the OFDM signal actually received by the receiving apparatus 1 will be described with reference to FIG. FIG. 4A shows an A-wave OFDM symbol signal Aw. FIG. 4B shows a B-wave OFDM symbol signal Bw delayed from the A-wave. FIG. 4C shows an OFDM symbol signal ABw of a combined wave of A and B waves. FIG. 4D shows an example of the FFT window pulse.

  The actual OFDM signal received by the receiver 1 is composed of the direct wave that directly reaches the antennas 2 and 3 from the transmitter side and the delayed wave that is reflected by the walls of the building and directly reaches the antennas 2 and 3. It becomes a composite wave. The delayed wave is actually a plurality of waves with different delay times from the direct wave. Here, for the sake of simplicity, an example of a combined wave of a direct wave and one type of delayed wave will be considered.

  For example, an A-wave OFDM symbol signal Aw as a direct wave shown in FIG. 4A and a B-wave OFDM symbol signal Bw such as a reflected wave delayed from the A-wave shown in FIG. Consider a case where the receiving apparatus 1 receives the OFDM symbol signal ABw of a combined wave of A and B waves shown in (c).

  Based on the peak value output from the peak detection circuit 21, the FFT window pulse generation circuit 22 performs interference between different symbols (for example, the first symbol in FIG. An FFT window pulse Pa is generated in which a range R in which no interference with the second symbol occurs is in a high state.

  When the received signal is a combined wave of a direct wave and a plurality of delayed signals, the peak value detected by the peak detection circuit 21 is plural. The FFT window pulse generation circuit 22 generates an FFT window pulse based on the plurality of peak values.

  Next, an example of calculating the C / N value in the reception quality detection circuit 18 in, for example, two-phase phase modulation (BPSK: Binary Phase Shift Keying) will be described with reference to FIG. FIG. 5A shows a signal point arrangement of an original SP signal (hereinafter referred to as a standard SP signal) at the time of transmission. FIG. 5B shows the signal point arrangement of the SP signal at the time of actual reception (hereinafter referred to as a received SP signal).

  Each OFDM symbol of the received signal includes a plurality of SP signals for synchronization, and these SP signals are extracted by the synchronization signal extraction circuit 181. In the present embodiment, the reception quality detection circuit 18 calculates the C / N value based on the deviation of the reception SP signal in the reception signal from the standard SP signal.

  As shown in FIG. 5A, in the constellation of I (in-phase component) -Q (quadrature component), the standard point D0 of the data value “0” as the standard SP signal and the standard point of the data value “1” D1 is represented. The received SP signal may deviate from the standard points D0 and D1. For example, as shown in FIG. 5B, the received SP signals are received points d0 and d1.

The coordinates of the standard point D0 or D1 as the standard position are (X1, Y1), and the coordinates of the reception point d0 or d1 as the reception position are represented by (x, y). The carrier power P0 at the standard position is expressed by the following equation (1). The noise power P1 at the reception position is expressed by the following equation (2).
P0 = (X1 ² + Y1 ² ) (1)
P1 = (x−X1) ² + (y−Y1) ² (2)

At this time, the C / N value is calculated by the following equation (3).
10log (P0 / P1)
= 10 log [(X1 ² + Y1 ² ) / {(x−X1) ² + (y−Y1) ² }] [dB] (3)

  The reception quality detection circuit 18 calculates a C / N value according to the above equation (3) based on the SP signal extracted by the synchronization signal extraction circuit 181, for example, a plurality of SP signals in one symbol of the reception signal. An average value of C / N values is calculated and output as received quality S1 per symbol.

  Next, the operation of the receiving apparatus 1 will be described with reference to FIG. FIG. 6 shows a flow of the first antenna switching process executed by the antenna control circuit 30 and the first FFT window position setting process executed by the FFT control circuit 20 (FFT window pulse generation circuit 22). .

  The first antenna switching process is a process of switching the receiving antenna from the antennas 2 and 3 in the receiving apparatus 1. The first FFT window position setting process is a process of setting the FFT window position when the receiving antenna 1 is switched between the antennas 2 and 3 in the receiving apparatus 1. In normal times, the FFT processing circuit 23 generates FFT window pulses at a predetermined cycle. The FFT processing circuit 23 performs FFT processing on the output signal of the AD converter 14 using the FFT window pulse generated in the normal time and the first FFT window position setting processing, and outputs the result as an FFT signal. In addition, it is assumed that the initial value of the C / N value is stored in the second register 33 in advance.

  The first antenna switching process will be described. First, the receiving apparatus 1 is activated, and the control circuit 32 sets an activation receiving antenna corresponding to the antenna identification information stored in the third register 34 (step ST11). The starting antenna is fixed by either antenna 2 or 3.

  Then, the reception quality detection circuit 18 inputs the current reception quality S1 to the comparator 31 and the control circuit 32 (step ST12). Then, the previous reception quality stored in the second register 33 is input to the comparator 31 by the control circuit 32 (step ST13). Then, the comparator 31 compares the current reception quality S1 with the previous reception quality (step ST14). At this time, a signal S2 as a comparison result is output from the comparator 31. Here, for example, the signal S2 as the comparison result is a signal in which the voltage is in a high state when the reception quality is deteriorated, and is a signal in which the voltage is in a low state when the reception quality is not deteriorated.

  When the current reception quality S1 <the previous reception quality (when the reception quality deteriorates) (step ST14; YES), the control circuit 32 causes the control circuit 32 to store the reception antenna identification information (before switching). The reception antenna identification information) is read out, and a signal S4 indicating the switched antenna identification information is generated and transmitted to the FFT control circuit 20 (step ST15).

  In parallel with step ST15, the control circuit 32 generates a signal S3 indicating the antenna switching timing and transmits it to the antenna switching circuit 12, and the receiving antennas are switched at the antennas 2 and 3 (step ST16). Specifically, the signal S3 is inverted. The control circuit 32 stores the switched antenna identification information in the third register 34 (step ST17).

  Then, the current reception quality S1 is stored in the second register 33 by the control circuit 32 (step ST18). When the current reception quality S1 <the previous reception quality is not satisfied (when the reception quality is not deteriorated) (step ST14; NO), the process proceeds to step ST18.

  Then, the control circuit 32 determines whether or not to end the antenna switching control based on power-off of the receiving device 1 or the like (step ST19). When the antenna switching control is not terminated (step ST19; NO), the process proceeds to step ST12. When the antenna switching control is finished (step ST19; YES), the first antenna switching process is finished.

  Next, the first FFT window position setting process will be described. First, the receiving apparatus 1 is activated to start receiving an OFDM signal. Then, the FFT window pulse generation circuit 22 determines whether or not a predetermined time has elapsed since the previous FFT window pulse setting (step ST21). When the predetermined time has elapsed (step ST21; YES), the peak value of the integrated value of the autocorrelation value of the reception signal (output signal of the AD converter 14) detected by the peak detection circuit 21 by the FFT window pulse generation circuit 22 ( FFT window pulse is generated on the basis of (symbol head position) and output to the FFT processing circuit 23, and the position data of the FFT window pulse is associated with the current receiving antenna identification information in the first register. 24 (step ST22).

  Then, the FFT window pulse generation circuit 22 determines whether or not the signal S4 is received from the control circuit 32 of the antenna control circuit 30 (step ST23). When the predetermined time has not elapsed (step ST21; NO), the process proceeds to step ST23. When the signal S4 is not received (step ST23; NO), the process proceeds to step ST21.

  When the signal S4 is received (step ST23; YES), the FFT window pulse generation circuit 22 reads the position data of the FFT window position corresponding to the antenna identification information of the received signal S4 from the first register 24 (step). ST24). Then, the FFT window pulse generation circuit 22 generates an FFT window pulse based on the read FFT window position information, and outputs it to the FFT processing circuit 23 (step ST25).

  Then, the FFT window pulse generation circuit 22 determines whether or not to end the FFT window pulse position setting control at the time of antenna switching (step ST26). When the FFT window pulse position setting control at the time of antenna switching is not terminated (step ST26; NO), the process proceeds to step ST21. When the FFT window pulse position setting control at the time of antenna switching is ended (step ST26; YES), the first FFT window position setting process is ended.

  FIG. 7 shows an example of the reception quality and the signal S3. In the graph shown in FIG. 7, the vertical axis indicates the value level of the reception quality, the voltage level of the signal S3, and the horizontal axis indicates time. Further, regarding the voltage of the signal S3, the antenna 2 corresponds to the voltage V0 (low), and the antenna 3 corresponds to the voltage V1 (high). First, when the receiving apparatus 1 is turned on (time t0), the receiving antenna is set to the antenna 2.

  Next, at time t1, since the value of the reception quality is worse than the value of the reception quality at time t0, the comparator 31 outputs “1” indicating the deterioration as the signal S2. As a result, the control circuit 32 inverts the voltage level of the signal S3 from low to high. For this reason, the receiving antenna is switched to the antenna 3.

  Subsequently, at time t2, since the value of the reception quality is worse again than the value of the reception quality at time t1, the comparator 31 outputs “1” again as the signal S2. As a result, the control circuit 32 inverts the voltage level of the signal S3 again from low to high. For this reason, the receiving antenna is switched to the antenna 2. Thereafter, such control is repeated.

  According to the present embodiment, in receiving apparatus 1 that demodulates a received signal in one system, the receiving antenna can be switched between antennas 2 and 3 based on the C / N value, and based on signal S4 at the time of antenna switching. The antenna 2 or 3 after switching is identified and the FFT window pulse based on the position data of the FFT window position corresponding to the antenna 2 or 3 after switching stored in the first register 24 is generated. The FFT window position can be set optimally.

  In the present embodiment, the signal S4 as the antenna identification information is transmitted from the antenna control circuit 30 to the FFT window pulse generation circuit 22. However, the present invention is not limited to this. For example, since the signal S3 is a signal having the antenna switching timing and the reception antenna identification information, the signal S3 may be transmitted from the antenna control circuit 30 to the FFT window pulse generation circuit 22 as well. The FFT window pulse generation circuit 22 can identify the reception antenna after switching based on the voltage level of the received signal S3.

Further, when the switching interval of the antenna becomes long, the FFT window pulse generation circuit 22 replaces the FFT window position position data corresponding to the antenna after switching from the first register 24 instead of reading the FFT window position position data. A configuration may be adopted in which a prescribed value of position data is read from the first register 24 to generate an FFT pulse.
Further, the FFT window pulse generation circuit 22 stores the position data of the FFT window position of the antenna in the first register 24 at a predetermined cycle. However, the present invention is not limited to this, and for example, the FFT window for each symbol. The position data of the position may be stored, or when receiving the same antenna, the position data of the FFT window position is stored when the position data of the FFT window changes. Also good.

(Second Embodiment)
A second embodiment according to the present invention will be described with reference to FIGS. In the present embodiment, parts that are the same as those in the first embodiment are given the same reference numerals, and parts that are different from those in the first embodiment are mainly described.

  FIG. 8 shows a functional configuration of receiving apparatus 1A of the present embodiment. The receiving apparatus 1A according to the present embodiment includes antennas 2 and 3 and an OFDM signal demodulation circuit 100A. The OFDM signal demodulation circuit 100A is the same as the OFDM signal demodulation circuit 100 of the first embodiment except that the FFT control circuit 20 and the antenna control circuit 30 are replaced with the FFT control circuit 20A and the antenna control circuit 30A shown in FIG. For example, it is formed by a semiconductor integrated circuit.

  The FFT control circuit 20A includes a peak detection circuit 21, an FFT processing circuit 23, an FFT window pulse generation circuit 22A, an FFT processing circuit 23, and a first register 24A.

  The FFT window pulse generation circuit 22A generates and outputs an FFT window pulse based on the peak value (symbol head position) output from the peak detection circuit 21 in a normal reception state, and when antenna switching is performed. (Only when), based on the signal S5 output from the antenna control circuit 30, the specified value of the position data of the FFT window pulse position stored in the first register 24A is read, and the FFT window pulse is read based on the specified value. Is generated and output.

  The first register 24A stores a predetermined value of position data of a preset FFT window pulse position. The specified value of the position data of the FFT window pulse position is a value common to the antennas 2 and 3 and is information of the FFT window pulse position from which a normal FFT signal can be obtained by the FFT processing circuit 23 in a normal reception state.

  FIG. 9 shows the internal configuration of the antenna control circuit 30A. As shown in FIG. 9, the antenna control circuit 30A includes a comparator 31, a control circuit 32A, and a second register 33. Based on the signal S2 output from the comparator 31, the control circuit 32A outputs signals S3 and S5 indicating antenna switching timing, and stores the reception quality S1 in the second register 33. The signal S5 is, for example, a binary signal that is high for a predetermined time when the antenna is switched.

  Next, the operation of the receiving apparatus 1A will be described with reference to FIG. FIG. 10 shows the flow of the second antenna switching process executed by the antenna control circuit 30A and the second FFT window position setting process executed by the FFT control circuit 20A (FFT window pulse generation circuit 22A). .

  The second antenna switching process is a process of switching the receiving antenna between the antennas 2 and 3 in the receiving apparatus 1A. Similar to the first FFT window position setting process, the second FFT window position setting process is a process of setting an FFT window pulse when the reception antenna is switched between the antennas 2 and 3 in the receiving apparatus 1A.

  The second antenna switching process will be described. First, the receiving apparatus 1A is activated, and the receiving antenna at the time of activation is set to the antenna 2 or 3 by the control circuit 32A (step ST31). Steps ST32 to ST34 are the same as steps ST12 to ST14 of the first antenna switching process, respectively.

  When the current reception quality S1 <the previous reception quality (when reception quality deteriorates) (step ST34; YES), the control circuit 32A generates a signal S5 indicating the switching timing and transmits it to the FFT control circuit 20A. (Step ST35).

  Steps ST36 to ST38 are respectively the same as steps ST16, ST18, and ST19 of the first antenna switching process. When the current reception quality S1 <the previous reception quality is not satisfied (when the reception quality is not deteriorated) (step ST34; NO), the process proceeds to step ST37.

  Next, the second FFT window position setting process will be described. First, the receiving apparatus 1A is activated to start receiving an OFDM signal. Then, the FFT window pulse generation circuit 22A determines whether or not the signal S5 is received from the antenna control circuit 30A (step ST41). When the signal S5 is not received (step ST41; NO), the process proceeds to step ST41.

  When the signal S5 is received (step ST41; YES), the FFT window pulse generation circuit 22A reads the specified value of the position data of the FFT window position from the first register 24A corresponding to the received signal S5 (step ST42). ). Steps ST43 and ST44 are the same as steps ST25 and ST26 of the first FFT window position setting process, respectively.

  As described above, according to the present embodiment, in the receiving apparatus 1A that demodulates the received signal with one system, the antennas 2 and 3 to be received can be switched based on the C / N value, and at the time of antenna switching, the first register Since the FFT window pulse based on the specified value of the position data of the FFT window position stored in 24A is generated, the FFT window position can be optimally set at the time of antenna switching.

  Note that the descriptions in the above embodiments are examples of the OFDM receiving apparatus and the OFDM receiving method according to the present invention, and the present invention is not limited thereto.

  In the above embodiment, the configuration has been described in which the receiving apparatuses 1 and 1A receive and demodulate the BPSK OFDM signal. However, the present invention is not limited to this. Instead of BPSK, a signal of another modulation method such as QPSK (Quadrature Phase Shift Keying) may be received and demodulated.

  Here, a method for calculating the C / N value in the QPSK method will be described with reference to FIG. In the receiving device 1, the reception quality detection circuit 18 calculates a C / N value based on the deviation of the FFT signal output from the FFT control circuit 20 from the standard position. FIG. 11A shows the signal point arrangement of the reference data signal in QPSK. FIG. 11B shows the position of the received data signal when the phase changes with respect to the position of the reference data signal.

  As shown in FIG. 11A, in the constellation of I (in-phase component) -Q (quadrature component), the reference point D00 of the data value “00” of the reference data signal and the reference point D01 of the data value “01” A reference point D10 having a data value “10” and a reference point D11 having a data value “11” are represented. The received data signal may deviate from the reference points D00, D01, D10, and D11. For example, as shown in FIG. 11B, the received data signals are received points d00, d01, d10, and d11.

The coordinates of the reference point D00, D01, D10 or D11 as the reference position are (X2, Y2), and the coordinates of the reception point d00, d01, d10 or d11 as the reception position are represented by (x, y). The carrier power P0 at the standard position is expressed by the following equation (4), and the noise power P1 at the reception position is expressed by the following equation (5).
P0 = (X2 ² + Y2 ² ) (4)
P1 = (x−X2) ² + (y−Y2) ² (5)

At this time, the C / N value is calculated by the following equation (6).
10log (P0 / P1)
= 10 log [(X2 ² + Y2 ² ) / {(x−X2) ² + (y−Y2) ² }] [dB] (6)
For example, the reception quality detection circuit 18 calculates the C / N value in one symbol of the received signal by the above equation (6), calculates the average value, and outputs it as the C / N value per symbol.

  In each of the above embodiments, the antenna is switched when the current reception quality deteriorates from the previous one as the reception antenna switching timing based on the reception quality. However, the present invention is not limited to this. . For example, when the current reception quality is lower than a predetermined threshold and worse than the previous one, the antenna is switched, or the current reception quality is lower than the predetermined threshold and worse than the previous one, and the previous reception A configuration in which the antenna is switched when the quality is lower than the threshold and when the current reception quality is lower than the predetermined threshold and worse than the previous one, and the previous reception quality is higher than the threshold and the previous antenna is switched. It is good also as a structure of the switching timing of the other receiving antenna based on receiving quality.

  In each of the above embodiments, two antennas are provided and the reception antenna is switched. However, the present invention is not limited to this. For example, a configuration may be adopted in which three or more antennas are provided and the reception antenna is switched.

  Further, instead of the configuration for switching the reception antenna, a configuration may be adopted in which one antenna is provided and the reception characteristics of the antenna are switched. FIG. 12 shows the configuration of the variable characteristic antenna unit 4. For example, the receiving apparatus may be configured to include the variable characteristic antenna unit 4 illustrated in FIG. 12 instead of the plurality of antennas and the antenna switching circuit. The variable characteristic antenna unit 4 includes an antenna 41, an auxiliary antenna 42, an inductor 43, and a varicap 44. The antenna 41 receives a radio wave from a broadcasting station, converts the received radio wave into an electric signal, and outputs it to a tuner circuit. One end of the inductor 43 and one end of the varicap 44 are connected to the auxiliary antenna 42. The other end of the inductor 43 is connected to the output terminal of the antenna control circuit, and the other end of the varicap 44 is grounded.

  The arrangement position of the auxiliary antenna 42 with respect to the antenna 41 is set to a position where the antenna 41 can be affected by the electric field generated around the auxiliary antenna 42 when a voltage is applied to the auxiliary antenna 42. As a result, when a voltage is applied to the auxiliary antenna 42, the strength of the electric field (potential) around the auxiliary antenna 42 changes greatly, and the reception characteristics such as directivity of the antenna 41 are affected. In addition, the axial direction of the antenna 41 and the auxiliary antenna 42 are arranged to be parallel to each other. The auxiliary antenna 42 is formed of a conductor such as metal. The antenna control circuit is configured to switch and output two or more types of voltage signals based on the reception characteristics to switch the reception characteristics of the variable characteristic antenna unit 4.

  In the above embodiment, the antenna control circuits 30, 30A (comparator 31, control circuits 32, 32A), the FFT control circuit 20 (peak detection circuit 21, FFT window pulse generation circuits 22, 22A), etc. However, it has a CPU (Central Processing Unit), a RAM (Random Access Memory), a ROM (Read Only Memory), etc., and a program stored in the ROM is expanded in the RAM. A software configuration in which various functions are realized by the cooperation of the program developed in the RAM and the CPU may be employed.

  In addition, it is needless to say that the detailed configuration and detailed operation of each component of the receiving devices 1 and 1A in the above embodiments can be appropriately changed without departing from the spirit of the present invention.

It is a block diagram which shows the function structure of the receiver 1 of 1st Embodiment which concerns on this invention. It is a block diagram which shows the internal structure of the antenna control circuit 30 of 1st Embodiment concerning this invention. (A) is a figure which shows the OFDM signal 200 to receive. (B) is a diagram showing a delayed signal 210 of the OFDM signal 200. FIG. (C) is a figure which shows the correlation value 220 of an OFDM signal. (D) is a figure which shows the integral value of the correlation value 220. FIG. (A) is a figure which shows A-wave OFDM symbol signal Aw. (B) is a figure which shows the OFDM symbol signal Bw of the B wave delayed from the A wave. (C) is a figure which shows OFDM symbol signal ABw of the synthetic wave of A wave and B wave. (D) is a figure which shows an example of a FFT window pulse. (A) is a figure which shows the signal point arrangement | positioning of the standard SP signal in BPSK. (B) is a figure which shows the signal point arrangement | positioning of a reception SP signal. 4 is a flowchart showing a first antenna switching process executed by the antenna control circuit 30 according to the first embodiment of the present invention and a first FFT window position setting process executed by the FFT control circuit 20; . It is a figure which shows an example of the reception quality in the 1st Embodiment which concerns on this invention, and signal S3. It is a block diagram which shows the function structure of 1 A of receivers of 2nd Embodiment which concerns on this invention. It is a block diagram which shows the internal structure of 30 A of antenna control circuits of 2nd Embodiment which concerns on this invention. It is a flowchart which shows the 2nd antenna switching process performed with the antenna control circuit 30A of the 2nd Embodiment which concerns on this invention, and the 2nd FFT window position setting process performed with the FFT control circuit 20A. . (A) is a figure which shows the signal point arrangement | positioning of the standard SP signal in QPSK. (B) shows the signal point arrangement of the received SP signal. FIG. 3 is a diagram illustrating a configuration of a variable characteristic antenna unit 4.

Explanation of symbols

1, 1A Receiving device 2, 3 Antenna 100, 100A OFDM signal demodulation circuit 112, 113 Antenna connection terminal 13 Tuner circuit 14 AD converter 15 Transmission line equivalent circuit 16 Demodulation circuit 17 Error correction circuit 18 Reception quality detection circuit 181 Synchronization signal extraction circuit 20, 20A FFT control circuit 21 Peak detection circuit 22, 22A FFT window pulse generation circuit 23 FFT processing circuit 24, 24A First register 30, 30A Antenna control circuit 31 Comparator 32, 32A Control circuit 33 Second register 34 Third register 4 Variable characteristic antenna 41 Antenna 42 Auxiliary antenna 43 Inductor 44 Varicap

Claims (2)

An antenna switching means that has a plurality of antenna connection terminals to which an antenna can be connected, and selects one antenna connection terminal from among the plurality of antenna connection terminals to switch the antenna to receive;
Reception quality detection means for detecting the reception quality of the OFDM signal received by the antenna connected to one antenna connection terminal selected by the antenna switching means;
An antenna switching control means for controlling the antenna switching means so as to switch the antenna to be received based on the reception quality detected by the reception quality detection means;
FFT window pulse generating means for generating an FFT window pulse based on an OFDM signal received by an antenna connected to one antenna connection terminal selected by the antenna switching means;
Storage means for storing position data indicating the position of the FFT window pulse generated by the FFT window pulse generation means while updating the position data in association with each antenna being received ;
As said by the antenna switching control means only when the control of switching the antenna is made reading the position data corresponding to the antenna after switching from said memory means, for generating an FFT window pulse based on the read out position data FFT window pulse generation control means for controlling the FFT window pulse generation means,
FFT processing means for performing FFT processing on the received OFDM signal using the FFT window pulse generated by the FFT window pulse generating means and outputting an FFT signal;
An OFDM receiving apparatus comprising: An antenna switching step of selecting one antenna connection terminal from among the antenna connection terminals that can be connected to the antenna and switching the antenna to be received;
A reception quality detection step of detecting a reception quality of an OFDM signal received by an antenna connected to one antenna connection terminal selected by the antenna switching step;
An antenna switching control step for controlling the antenna switching step so as to switch the antenna to be received based on the reception quality detected by the reception quality detection step;
An FFT window pulse generating step for generating an FFT window pulse based on an OFDM signal received by an antenna connected to one antenna connection terminal selected by the antenna switching step;
A storage step of storing in the storage device while updating the position data indicating the position of the FFT window pulse generated by the FFT window pulse generation step in association with each of the antennas being received ;
As said the antenna switching control process only when the control is made to switch the antenna reads the position data corresponding to the antenna after switching from said storage device, it generates an FFT window pulse based on the read out position data An FFT window pulse generation control step for controlling the FFT window pulse generation step;
FFT processing step of performing FFT processing on the received OFDM signal using the FFT window pulse generated by the FFT window pulse generating step and outputting an FFT signal;
An OFDM reception method comprising:

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