JP4744071B2 - Semiconductor module - Google Patents

Description

  The present invention relates to a semiconductor device and a semiconductor module, and more particularly to a technique for preventing a problem due to mismatch of thermal expansion coefficients when a semiconductor device is mounted on a mounting substrate.

  Conventionally, in a hybrid integrated circuit device set in an electronic device, a conductive pattern is formed on, for example, a printed circuit board, a ceramic substrate, or a metal substrate, on which an active element such as an LSI or a discrete TR, a chip capacitor, a chip Passive elements such as resistors or coils are mounted. The conductive pattern and the element are electrically connected to realize a circuit having a predetermined function.

  FIG. 24 shows an example of the circuit. This circuit is an audio circuit, and the elements shown therein are mounted as shown in FIG.

  In FIG. 25, the outermost rectangular line is the mounting substrate 1 whose surface is insulated at least. And the conductive pattern 2 which consists of Cu is affixed on this. The conductive pattern 2 includes an external extraction electrode 2A, a wiring 2B, a die pad 2C, a bonding pad 2D, an electrode 4 to which the passive element 3 is fixed.

  On the die pad 2C, a TR, a diode, a composite element, an LSI, or the like is fixed in a bare chip shape via solder. The electrodes on the fixed chip and the bonding pads 2D are electrically connected through the fine metal wires 5A, 5B, and 5C. This metal thin wire is generally classified into a small signal and a large signal, and the small signal portion employs an Au wire or Al wire 5A comprising about 40 μmφ, and the large signal portion comprises an Au wire or Al wire of about 100 to 300 μmφ. It has been adopted. In particular, since a large signal has a large wire diameter, 150 μmφ Al wire 5B and 300 μmφ Al wire 5C are selected in consideration of cost.

  Further, the power TR6 for flowing a large current is fixed to the heat sink 7 on the die pad 2C in order to prevent the temperature of the chip from rising.

  The wiring 2B is extended to various places in order to use the external extraction electrode 2A, the die pad 2C, the bonding pad 2D, and the electrode 4 as a circuit. In addition, jumping lines 8A and 8B are employed when the wirings intersect due to the position of the chip and the way the wirings extend.

  On the other hand, as a semiconductor device mounted on the mounting substrate 1, there is a semiconductor device packaged with an insulating resin. For example, a lead frame type semiconductor device, a ceramic substrate, a printed circuit board or a flexible sheet in which a semiconductor chip is mounted on a lead frame and packaged with an insulating resin is used as a support substrate, and the semiconductor chip is mounted on the insulating resin. There are a support substrate type semiconductor device packaged in (1) and a plating type semiconductor device in which a semiconductor chip is mounted on a plating electrode and packaged including the plating electrode (see Patent Document 1 below).

A schematic diagram of this is shown in FIG. 26A. Reference numerals 10 </ b> A to 10 </ b> D denote conductive paths formed of a plating film. The semiconductor chip 11 is fixed on the die pad 10 </ b> A, and the bonding pad 10 </ b> B made of plating and the bonding pad 10 </ b> B made of plating are electrically connected by the thin metal wires 12. Connected. Further, the passive element 13 is fixed between the electrode 10C and the electrode 10D through a brazing material. This semiconductor device. Since the plating film is embedded in the insulating resin without adopting the support substrate, a thin semiconductor device is possible.
Japanese Patent Laid-Open No. 3-94431

  As described above, the semiconductor device packaged by various methods is mounted on the mounting substrate 1. However, the lead frame type semiconductor device has a problem that the area occupied by the mounting substrate becomes large because the lead protrudes from the package, resulting in an increase in the size of the mounting substrate. Furthermore, there is a problem that the lead frame is cut or burrs are generated in the lead. In addition, since the support substrate type semiconductor device employs the support substrate, the semiconductor device becomes thick, which increases the weight. Furthermore, since the plated semiconductor device does not employ a support substrate and leads do not protrude from the package, a thin and small semiconductor device can be realized, but there are problems in the following respects.

  FIG. 26B is a diagram for explaining this, and is a schematic enlargement of the circled portion in FIG. 26A. Reference numeral 10B indicated by an aggregate of triangular pyramids is a conductive path formed by plating, and reference numeral 17 is solder. Reference numeral 15 denotes a mounting substrate, and 16 denotes a conductive pattern attached to the mounting substrate 15.

  This plating film is generally formed by electrolytic plating and has a columnar crystal structure with a thin tip. This is indicated by the triangular pyramid in the figure. Since this film is thin and has a polycrystalline structure, its mechanical strength is weak, and further, cracks are likely to occur due to the difference in thermal expansion coefficient from the insulating resin. Moreover, the crystal grain boundary easily diffuses substances from the outside. For example, an external atmospheric gas such as flux or moisture used for solder enters the connecting portion of the fine metal wire 12 through the crystal grain boundary, thereby deteriorating the connection strength. Further, when the electrode 11B is formed by Cu plating, there is a problem that the lower layer solder diffuses and the plating film itself is eroded by the solder and deteriorates the connection strength with the fine metal wire.

  If the plating film is formed thin and long as a wiring, the wiring is also disconnected due to a mismatch with the thermal expansion coefficient of the insulating resin. Similarly, when this plated semiconductor device is mounted on a mounting board, there is a problem that a crack is generated in the wiring due to a mismatch with the thermal expansion coefficient of the mounting board, resulting in disconnection or an increase in wiring resistance. In particular, when an elongated wiring is formed by the plating electrode 10B, the stress is generated in proportion to the length. Therefore, the difference in thermal expansion coefficient from the insulating resin 14 or the mounting substrate 15 has a problem that the defects of the plating film are made redundant and the deterioration of reliability is further accelerated.

  The present invention has been made in view of the above-described problems. First, a plurality of conductive paths made of a conductive material having a large crystal growth in the X and Y directions, and a semiconductor chip electrically connected to the conductive paths, The problem is solved by providing an insulating resin that covers the semiconductor chip and is filled in a separation groove between the conductive paths and exposes the back surface of the conductive paths and supports it integrally.

  Here, as shown in FIG. 1A, a film in which the growth in the Z-axis direction is larger than the growth in the X-axis / Y-axis direction is called a Z film, and a film in which the growth in the X-axis / Y-axis direction is larger than the growth in the Z-axis direction. It is called an XY film. For example, the Z film is a plated film grown by electrolysis or electroless, and the XY film is a film formed by rolling, for example, a rolled copper foil.

  As shown in FIG. 1C, when the XY film is viewed in cross section, each film has a crystal grain boundary area larger than that of the Z film in FIG. Is also suppressed. Therefore, the diffusion or transmission phenomenon through the crystal grain boundary is greatly suppressed. Further, the Z film of FIG. 1B has a structure that is very weak against stress acting by an external force that is bent and extends left and right. However, as shown in FIG. 1C, the XY film becomes stronger than the Z film against warping and breaking of the XY film itself. Therefore, the occurrence of cracks in the conductive path can be prevented due to the difference in the thermal expansion coefficient of the insulating resin that seals the conductive path itself. Further, since the size of the crystal is large, the resistance of the entire conductive path itself can be reduced. In particular, when the thickness of the package is 0.5 mm or less and the conductive path is embedded in the package, the plane size is larger than the thickness. Therefore, due to the difference in thermal expansion coefficient between the conductive path and the insulating resin, X− Stress is applied in the Y direction. However, since each crystal grows greatly in the XY direction, the structure is strong against the stress.

  For example, when an electrode made of rolled Cu foil is embedded in an insulating resin and when an electrode made of Cu plating is embedded, the strength against the stress described above is superior to the rolled copper foil, and contamination of the contact portion due to diffusion. Also, the rolled copper foil is superior.

  Secondly, the problem is solved by drawing the back surface of the insulating resin and the side surface of the conductive path with substantially the same etching surface.

  Although it becomes clear with a later manufacturing method, since the insulating resin is embedded after half etching, the half-etched curved structure becomes the shape of the insulating resin. This has the feature that the contact effect on the back surface is lowered at the same time as the anchor effect is generated. Therefore, the movement and self-alignment of the semiconductor device itself are facilitated.

  Thirdly, the problem is solved by forming the back surface of the conductive path to be recessed from the back surface of the separation groove.

  By forming the conductive path to be concave, the solder formed on the conductive path can be thickened, and by forming the convex portion of the insulating resin, the adjacent solder does not come into contact.

  Fourth, the problem is solved by forming an oxide of the conductive material on the surface of the conductive path in contact with the insulating resin.

  By forming copper oxide on the surface of a metal having a conductive path, particularly, Cu as a main material, adhesion with an insulating resin can be improved.

  Fifth, the thickness of the insulating resin is substantially less than 1 mm, and the conductive path is a thickness that can be achieved by a rolling method.

  Sixth, a plurality of conductive paths made of a crystal whose X and Y directions are larger than the Z axis, and a conductive path formed on the upper surface of the conductive path and made mainly of crystals whose Z axis direction is larger than the X and Y axis directions. A coating, a semiconductor chip electrically connected to the conductive coating, and an insulating resin that covers the semiconductor chip and is filled in a separation groove between the conductive paths and exposes the back surface of the conductive paths to be integrally supported To solve the problem.

  In principle, the conductive pattern to be an electrode or wiring is formed by an XY film, and if a Z film is grown only on a portion that requires electrical connection, it is superior to the case where all the conductive patterns are formed by a Z film. The characteristics can be demonstrated. For example, the semiconductor device is excellent against disconnection and contamination of the connection portion.

  Seventh, a plurality of conductive paths made of crystals whose X and Y directions are larger than the Z axis, and a conductive film formed on the upper surface of the conductive path, mainly having a Z axis direction larger than the X axis and Y axis directions, A semiconductor chip electrically connected to the conductive film; and an insulating resin that covers the semiconductor chip and is filled in a separation groove between the conductive paths and that integrally supports the exposed back surface of the conductive path. The back surface of the insulating resin and the side surface of the conductive path are solved by drawing substantially the same etching surface.

  Eighth, a plurality of conductive paths made of crystals whose X and Y directions are larger than the Z-axis, a conductive film formed on the upper surface of the conductive path and having a large crystal growth mainly in the Z-axis direction by plating, and the conductive film A semiconductor chip that is electrically connected to the semiconductor chip, and an insulating resin that covers the semiconductor chip and that is filled in a separation groove between the conductive paths and exposes the back surface of the conductive path so as to be integrally supported. The side surface of the road is etched into a curve, and at least a part of the back surface of the insulating resin is solved by drawing a curve continuous with the etched surface.

  Ninthly, the etching surface is solved by drawing a continuous curve with a surface formed by non-anisotropic etching.

  Tenth, the problem is solved by forming the back surface of the conductive path to be recessed rather than the back surface of the insulating resin.

  Eleventh, the conductive path in contact with the insulating resin is solved by forming an oxide on the surface.

  Twelfth, the problem is solved by forming a conductive film on the back surface of the conductive path.

  By covering the back surface of the conductive path with, for example, a metal film, solder, or the like, oxidation of the conductive path can be prevented. Therefore, even if the circuit pattern on the mounting substrate and the conductive path are connected by the brazing material, since there is no oxide of the conductive path, the defect can be greatly suppressed.

  13thly, the said conductive film is solved by comprising eaves on the surface of the said conductive path.

  Since the shape of the eaves can be realized by the conductive path and the conductive film or the conductive path itself, an anchor effect is generated, and the disconnection and peeling of the conductive path can be suppressed.

  14thly, the conductive path exposed from the said insulating resin is solved by being covered with an insulating film except for an electrical connection place.

  When there are various shapes of conductive paths, the brazing material gets wet in the entire region. Therefore, at the same time that the amount of solder is different, the thickness of the solder also differs depending on the size, surface tension, and dead weight. Therefore, by forming a film with poor solder wettability on the exposed conductive path, the solder wetted area can be controlled, and solder with a desired thickness can be formed on the back surface of the conductive path.

  Fifteenth, a wiring is provided as the conductive path, and the conductive path exposed from the insulating resin is solved by being covered with an insulating coating except for an electrical connection portion.

  In the structure of the semiconductor device, the back surface of the conductive path is exposed from the insulating resin. Therefore, the wiring as shown in FIG. 6, FIG. 7, and FIG. Therefore, when this semiconductor device is mounted on the mounting substrate, the conductive pattern and the wiring of the mounting substrate are short-circuited. However, the short circuit can be prevented by forming the insulating film.

  Sixteenth, a plurality of conductive paths made of a conductive material whose crystal growth in the X and Y directions is larger than the Z axis, a conductive film formed on the upper surface of the conductive path and mainly made of crystal growth in the Z axis direction, A semiconductor chip electrically connected to the conductive film; and an insulating resin that covers the semiconductor chip and is filled in a separation groove between the conductive paths and exposes a back surface of the conductive path to integrally support the conductive chip. The semiconductor device is solved by being mounted on the mounting substrate through the exposed portion.

  Seventeenth, a plurality of conductive paths made of a conductive material whose crystal growth in the X and Y directions is larger than the Z axis, a conductive film formed on the upper surface of the conductive path and mainly made of crystal growth in the Z axis direction, A semiconductor chip electrically connected to the conductive film; and an insulating resin that covers the semiconductor chip and is filled in a separation groove between the conductive paths and that integrally supports the exposed back surface of the conductive path. The semiconductor device in which the back surface of the insulating resin and the side surface of the conductive path form a substantially continuous curve is mounted on the mounting substrate via the exposed portion.

  Eighteenth, a plurality of conductive paths made of a conductive material whose crystal growth in the X and Y directions is larger than that of the Z axis, and a conductive film formed on the upper surface of the conductive path and having large crystal growth mainly in the Z axis direction by plating A semiconductor chip electrically connected to the conductive film; and an insulating resin that covers the semiconductor chip and is filled in a separation groove between the conductive paths and that integrally supports the exposed back surface of the conductive path. A side surface of the conductive path is curvedly etched, and a semiconductor device in which at least a part of the back surface of the insulating resin substantially coincides with the etched surface is mounted on the mounting substrate through the exposed portion. To solve this problem.

  Nineteenth, the back surface of the conductive path and the mounting substrate are connected via a brazing material, and the back surface of the conductive path and / or the connection pattern on the mounting substrate is provided with a coating that prevents the flow of the brazing material. It is solved by being done.

  When a plurality of conductive paths having different sizes are employed, the brazing material spreads so as to get wet throughout the conductive path, and the brazing material formed on the back surface of the semiconductor device has a different thickness. The same phenomenon occurs in the conductive pattern on the mounting board side. This phenomenon may narrow the gap between the mounting substrate and the conductive path. However, by forming a film having poor wettability with respect to the brazing material on at least one side, the spread of the brazing material can be suppressed, and this gap can be kept constant.

  Twenty, the etching surface is solved by drawing substantially the same curve as the surface formed by non-anisotropic etching.

  Twenty-first, the problem is solved by forming the back surface of the conductive path to be recessed rather than the back surface of the insulating resin.

  Twenty-second, the conductive path in contact with the insulating resin is solved by forming an oxide on the surface.

  23rd is to solve the problem by forming a conductive film on the back surface of the conductive path.

  24thly, the said conductive film is solved by comprising eaves on the surface of the said conductive path.

  As is apparent from the above description, in the present invention, a thin semiconductor device can be mounted in a wide range of forms such as a discrete type, a BGA type, a multichip type, a hybrid type, and the like. In addition, since the semiconductor device is thin, warping of the semiconductor device becomes a problem. However, since a rolled XY film is used as the conductive path, disconnection of the conductive path due to warpage and resin shrinkage can be prevented. In addition, the electrical connection portion employed as a semiconductor device employs an XY film as a lower layer, thereby preventing contamination of the connection portion and being resistant to changes with time and defects after packaging. Can be supplied to users. In addition, thin and long wirings are more easily stressed than other conductive paths, but the use of an XY film makes it possible to suppress the disconnection of the wirings.

  Further, the same etching surface is drawn on the back surface of the insulating resin and the side surface of the conductive path in order to employ this manufacturing method. In particular, the back surface of the insulating resin is curved, and an empty area is formed in a portion adjacent to the curved portion. Therefore, it is possible to create a relief area for the melted solder and to reduce the friction coefficient on the back surface of the semiconductor device.

  In addition, after the half etching, the conductive foil undergoes a heat treatment step for generating an oxide film, and thus an oxide of Cu is formed on the surface thereof. This oxide can improve the adhesion between the conductive foil and the insulating resin.

  First, the size of the semiconductor device will be described with reference to FIG. Since the adopted semiconductor chip 30 uses a TR chip here, it has a thickness of about 0.55 × 0.55 mm and a thickness of 0.24 mm. The plane size of the semiconductor device 31 is 1.6 × 2.3 mm and the thickness is 0.5 mm. The planar size of the semiconductor device with respect to the planar size of the chip is more than twice, and the thickness of the package is about twice the thickness of the chip or less, especially when mounted face down, the metal thin wire does not extend upward. Therefore, the thickness can be further reduced. That is, although it is thin, the size of the plane can be developed in various sizes from about 1 mm × 2 mm to a size far exceeding this size by a combination of a semiconductor element and a passive element described below.

  As will be described later, as can be understood from FIGS. 6B, 7, 10, and 11, the semiconductor device can be used from a discrete package to a package constituting a circuit or system, and can be thin. Semiconductor device.

  Further, in this semiconductor device, the conductive paths 32 to 34 are exposed on one surface, and the insulating resin 35 is covered from the conductive paths 32 to 34 toward the other surface. For this reason, the shrinkage rate of the insulating resin 35 is larger, and the entire structure is easy to warp. Therefore, it is required to employ conductive paths 32-34 that can withstand this stress. In particular, this problem becomes more important as the wiring becomes longer.

  Furthermore, while considering an increase in cost as a semiconductor device, since the conductive paths 32 to 34 are as thin as about 30 to 50 μm or less, diffusion of impurities and gas through the interface of crystal grain boundaries, deterioration of electrical connection portions It is necessary to consider and adopt them comprehensively. In the case of mounting a power semiconductor element, the film thickness of the conductive path is preferably 100 to 200 μm in consideration of current capacity and generated heat.

  In general, there are two types of materials employed as electrodes, a Z film shown in FIG. 1A and an XY film shown in FIG. 1C. As described in the section of the problem, the back surface of the conductive path 40 made of the Z film has a large number of interfaces, and as shown by arrows, a structure in which contaminants from outside easily diffuse through the crystal grain boundaries 41. have. For example, the pollutant is a gas in the external atmosphere, such as moisture. In addition, when a brazing material is used, flux or the like is a contaminant. This means deterioration of the fixing force of the fine metal wire 42 fixed to the Z film, and also means deterioration of the fixing force of the chip 43 die-bonded to the Z film.

  Further, as shown in FIG. 1B, the Z film 40 has a gap between the crystal grains 45 even when the disconnection 49 is generated or the disconnection 49 is not generated in response to the warp generated by the shrinkage of the insulating resin 44. In order to spread, there is a problem that resistance becomes large. In order to prevent this, it is necessary to make the Z film 40 thick or to stack several layers of Z films. However, this has a problem that the film formation time becomes long and the cost increases.

  On the other hand, as shown in FIG. 1C, the back surface of the conductive path 46 made of the XY film has less exposure of the interface 47 than the Z film 40. In addition, since crystal growth toward the XY direction is large and the crystal grains 48 are stacked in layers, it is possible to prevent the diffusion of contaminants from the outside through the crystal grain boundaries 47 as indicated by arrows. Has characteristics. This means that contamination of the surface of the conductive path 46 caused by the diffusion can be greatly suppressed.

  Further, the XY film 46 has a feature that the wire is less likely to be disconnected and the resistance thereof is reduced against the warp caused by the shrinkage of the insulating resin 44. For example, a conductive foil made of a metal material processed by rolling is listed as an XY film.

  FIG. 2 shows bending characteristics of a rolled conductive foil (XY film) containing Cu as a main material and an electrolytic foil (Z film) treated by electrolysis. It can be seen that the conductive foil annealed after rolling and the conductive foil only for rolling are very strong against breakage compared to the electrolytic foil.

  That is, as shown in FIG. 1D, it can be seen that the use of this XY film for a conductive path having a large length or area, for example, a die pad, a bonding pad or a wiring, has excellent characteristics as a conductive path. That is, it can be seen that when the XY film is employed as the wiring shown in FIGS. 6 to 11, the characteristics superior to those of the wiring employing the Z film are obtained.

  Moreover, when considering cost and resistance, a rolled copper foil containing Cu as a main material is preferable. However, considering that the surface of Cu is easily oxidized, the bondability of fine metal wires is poor, and the bondability with Au bumps is poor, as described in FIG. It is important to place 40. Even if warpage occurs and cracks 49 occur in the Z film 40, the XY film 46 is stably disposed in the lower layer, so that disconnection can be prevented.

  In addition, in the Ag plating film, a film thickness of about 2 to 10 μm is excellent in bonding properties, and it is said that bonding properties deteriorate if the film thickness exceeds this film thickness. In addition, it has been found that good bonding can be obtained with an Au plating film of about 0.2 μm. This is said to be because the growth rate of each crystal grain begins to differ greatly as the film thickness increases, and irregularities occur on the surface. It is said that the bonding film and the Z film are bonded to each other only by bonding the uneven Z film and the ball, and the connection strength between them is weak and the connection resistance is large. However, even if a thin Z film is used to improve the bondability, cracks and breaks are likely to occur in the wiring and die pad, and the reliability is lowered.

  Therefore, in the present invention, the XY film 46 which is strong against breakage is adopted as the conductive path such as the wiring 50, the die pad, and the bonding pad 51, and the XY film 46 is used as a support film as necessary. A Z film 40 is formed on the film 46. For example, a plating film made of Ag, Au, Ni, Pd, or the like is employed as necessary in a portion that requires bonding properties or solderability. However, considering the connection strength and cost, the Z-axis growth film 40 has a thin film thickness as described above. Therefore, the entire conductive path is not composed only of the Z film, but the XY film 46 functions as a support film and a protective film, and the Z film 40 is provided thereon, thereby deteriorating characteristics such as disconnection of the conductive path and increase in resistance. Is preventing.

  FIG. 3 illustrates this point. In FIG. 3, a crack 49 is generated in the Z film 40 and is divided into two regions 40A and 40B. However, since the two Z-axis growth films 40A and 40B are electrically connected by the XY film 46, the two Z-axis growth films are equivalently electrically connected, resulting in a disconnection failure. It explains that it does not happen. In addition, the arrows explain that the XY film 46 becomes a barrier film against intrusion from the external atmosphere and prevents contamination of the surface of the Z film 40.

  In FIG. 1D and FIG. 3B, the following features occur in addition to the features described above. A curved structure 52 or eaves 53 is provided on the side surface of the XY film 46, and this structure has a feature that the XY film 46 embedded in the insulating resin 44 is not peeled off and is embedded in a stable state. . Therefore, the Z film 40 provided thereon is maintained in a more stable state.

  FIG. 4 shows the conductive foil 54 half-etched before being sealed with the insulating resin 44. A Cu oxide film (Cu 2 O, CuO) 55 is generated on the surface excluding the region where the Z film 40 is formed, and this oxide film 55 improves chemical bonding with the insulating resin 44 as a sealing material. It explains that the adhesion between the conductive path and the insulating resin is improved.

  4A, the Z film 40 is formed over the entire upper surface of the conductive path 56, and in FIG. 4B, the oxide film 55 is exposed except for the main region. In FIG. 4B, since the copper oxide 55 is exposed as compared with FIG. 4A, the adhesiveness on the upper surface of the conductive path 56 is further improved.

  Further, when forming the separation groove 57 by half etching in the conductive path 56, non-anisotropic etching causes the following effects. First, since the curved structure 52 and the eaves 53 are generated, the anchor effect is generated, and at the same time, the region of the copper oxide 55 is expanded as compared with the straight separation groove, and there is an advantage that the adhesiveness with the insulating resin is improved.

  Finally, rigidity will be described with reference to FIG. 2B. The lower view of FIG. 2B shows that the conductive foil 54A is handled like a lead frame and is attached to a mold. A semiconductor manufacturer employs a lead frame and performs transfer molding, and has an advantage in that the semiconductor device can be manufactured with the mold used here. Although the present invention will be apparent from the description of FIGS. 14 to, since the conductive foil 54 is half-etched and attached to the mold, the rigidity is considered in consideration of ease of handling and the fact that it is sandwiched between the upper and lower molds. Is required. The conductive foil obtained by rolling can easily be impregnated with a manufacturing method to increase its rigidity. The table in FIG. 2B shows the weight percent of the impurities. In Type A, Ni, Si, Zn, and Sn are mainly employed as impurities. In Type B, Zn, Sn, and Cr are mixed as impurities. Furthermore, type C is mixed with Zn, Fe, and P. The types and weight percentages of impurities shown in this table are only examples, and any conductive foil having Cu as the main material may exhibit rigidity.

  On the other hand, if it is intended to form a conductive foil only with a plating film, it is difficult to add impurities due to the manufacturing method, and it is made of substantially pure Cu. Thus, the conductive foil is soft and has a problem of reduced workability, and a support substrate for supporting the conductive foil is required.

  In general, the larger the lead frame size, the larger the number of semiconductor devices. However, as the size increases, the workability is lowered because the warp or bend. In the present invention, a rectangular conductive foil having a length of 220 mm, a width of 45 mm, and a thickness of 70 μm is employed. Also, the lead frame generally adopted is up to about 250mm in length, up to about 75mm in width and about 0.5mm in thickness, and if the conductive foil used as a standard in the industry is adopted, the lead frame The mold used in the mold can be used.

Now, the structure of the semiconductor device will be specifically described. The present invention is a discrete type in which one TR is sealed, a BGA type in which one IC or LSI is sealed, a multi-chip type in which a plurality of TRs or a plurality of ICs are mounted, a plurality of TRs, a plurality of TRs, ICs and / or passive elements are mounted, wiring is used as a conductive path, and can be roughly classified into a hybrid type in which a desired circuit is configured. That is, it is important that most of the packages of semiconductor devices can be realized by this method.

<Reference Example 1>
Reference Example Explaining Discrete Type Semiconductor Device FIG. 5 shows a package of TR, which is embedded in an insulating resin 35 and the back surfaces of the conductive paths 32 to 34 are exposed.

  Reference numerals 32 to 34 denote conductive paths to be a collector electrode, a base electrode, and an emitter electrode, and the surface thereof is coated with Ag as a Z film 36 as shown in FIG. 5C. This Z film 36 is a film that enables wire bonding and die bonding, and in addition, Au, Pd, Ni, and the like are conceivable. Since the conductive paths 32 to 34 are etched non-anisotropically, the side surfaces thereof are curved structures 52, and eaves 53 can be formed on the surface of the conductive paths. Therefore, by adopting at least one of these, an anchor effect with the insulating resin 35 can be generated. Further, the insulating resin 35 is embedded in the separation groove 57 formed by half etching, and the insulating resin 35 exposed from the back surface of the semiconductor device 31 becomes the outer shape of the package. Since the separation groove 57 is formed by half etching and the bottom is curved, there is a feature that the friction coefficient of the chip can be reduced. Further, since the bottom of the separation groove 57 protrudes from the back surfaces of the conductive paths 32 to 34, there is an advantage that a short circuit between the conductive paths can be prevented and a connection material such as solder can be formed thicker.

  FIG. 5E shows a semiconductor device in which the semiconductor chip 30 is mounted face down. For example, a solder ball is formed on the surface of a semiconductor element and melted in a conductive path. When the space between the semiconductor chip 30 and the conductive path becomes very narrow and the permeability of the insulating resin 35 is poor, an underfill material 37 having a low viscosity and easily penetrating into the gap is employed. In this case, unlike FIG. 5D, the underfill material 37 is filled in the separation groove 57 and becomes one element of the outer shape. As shown in FIGS. 5D and 5E, the conductive path is exposed. Therefore, an appropriate conductive material is selected and coated in order to be electrically connected to the circuit pattern of the mounting board. For example, as shown in FIG. 5F, a brazing material SL such as solder, a plating material such as Au or Ag, a conductive paste, or the like is formed on the exposed portion.

  Further, since the exposed conductive paths have different areas, the thickness of the brazing material will be different, so that the exposed shape may be made substantially constant by covering the back surface with an insulating coating 38 as shown in FIG. 5G.

As described at the beginning of the embodiment of the present invention, even if a semiconductor chip having a thickness of about 0.55 × 0.55 mm and a thickness of 0.24 mm is molded, the semiconductor device 31 has a size of 1.6 × 2.3 mm, It can be seen that a very thin semiconductor device having a thickness of 0.5 mm or less can be realized and is suitable for use in portable equipment, computer equipment, and the like.

<Example 1>
Example of explaining a multi-chip (or hybrid) semiconductor device Next, FIG. 6 shows a hybrid or multi-chip semiconductor device 60. Since it is composed only of a transistor chip, it is a multi-chip type. If passive elements such as capacitors and resistors are mounted in this, a hybrid type is obtained.

  FIG. 24 shows an audio circuit. From the left, an Audio Amp 1ch circuit unit, an Audio Amp 2ch circuit unit, and a switching power supply circuit are surrounded by a thick dashed line.

  In each circuit portion, a circuit surrounded by a solid line is formed as a semiconductor device.

  First, in the Audio Amp 1ch circuit portion, three types of semiconductor devices and two semiconductor devices integrated with the 2ch circuit portion are prepared.

Here, the semiconductor device 60 is shown in FIG. 6 as an example. As shown in FIG. 6A , a current mirror circuit composed of TR1 and TR2 and a differential circuit composed of TR3 and TR4 are integrally configured. The semiconductor device 60 is shown in FIGS. 6B to 6E. Here, four transistor chips each having a thickness of 0.55 × 0.55 mm and a thickness of 0.24 mm are adopted and bonded with Au fine wires. The size of the semiconductor device 60 is 2.9 × 2.9 mm and the thickness is 0.5 mm. FIG. 6C illustrates a die pad 61 on which the Z film 36 is formed, a bonding pad 62 on which the Z film 36 is formed, and a wiring 63 that electrically connects the die pad and the bonding pad. In particular, the wiring 63 is provided very short in the figure, but actually, it may be formed long as shown in FIG.

The wiring 63 is a feature of the present invention, and is characterized by using a rolled copper foil as a main material of the wiring. Although depending on the scale of the circuit shown in FIG. 6A, when the planar size of the entire package increases, the length of the wiring arranged there also increases. Further, due to the difference in thermal expansion coefficient between the insulating resin 35 and the conductive path, the wiring is warped each time heat is applied. However, as shown in FIG. 2A, the rolled copper foil (XY film) has durability against the repetition (flexibility) of the warp, and therefore, the disconnection of the wiring can be suppressed.

<Reference example 2>
Reference Example Explaining BGA Type Semiconductor Device First, the semiconductor device 70 will be described with reference to FIG. In the figure, the following components are embedded in the insulating resin 71. That is, bonding pads 72A, wirings 72B integrated with the bonding pads 72A, and wirings 72B are integrated, and an external connection electrode 72C provided at the other end of the wirings 72B is embedded. Furthermore, a heat radiation electrode 72D provided in a region surrounded by the conductive patterns 72A to 72C and a semiconductor element 73 provided on the heat radiation electrode 72D are embedded. The semiconductor element 73 is fixed to the heat radiation electrode 72D through the insulating bonding means AD, and is indicated by a dotted line in FIG. 7A. Further, in order to enable bonding, the bonding pad 72A is patterned so as to be located around the semiconductor element 73, and the bonding electrode 74 and the bonding pad 72A of the semiconductor element 73 are electrically connected through the metal thin wire W. ing.

  Further, the side surfaces of the conductive patterns 72A to 72D are etched non-anisotropically, and here are formed by wet etching, so that they have a curved structure, and the curved structure generates an anchor effect.

  This structure includes a semiconductor element 73, a plurality of conductive patterns 72A to 72C, a heat radiation electrode 72D, a thin metal wire W, an insulating adhesive means AD, and an insulating resin 71 for embedding them. Further, in the arrangement region of the semiconductor element 73, the insulating adhesive means AD is formed on and between the conductive patterns 72B to 72D, and the insulating groove AD is formed on the separating groove 75 formed by etching. Adhesive means AD are provided. And it seals with the insulating resin 71 so that the back surface of conductive pattern 72A-72D may be exposed.

  As the insulating adhesive means, an adhesive made of an insulating material and an adhesive insulating sheet are preferable. Moreover, although it becomes clear by a later manufacturing method, a material that can be attached to the entire wafer and can be patterned by photolithography is preferable.

  Further, as the insulating resin 71, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin or polyphenylene sulfide can be used. As the insulating resin, any resin can be adopted as long as it is a resin that can be hardened using a mold, a resin that can be coated by dipping or coating.

  In addition, as the conductive patterns 72A to 72D, a conductive material mainly made of Cu formed by rolling and a rolled copper foil are preferable in consideration of half-etchability, plating formability, heat stress, and bending resistance.

  In the present invention, since the insulating resin 71 and the insulating adhesive means AD are also filled in the separation groove 75, the conductive pattern can be prevented from coming off. Further, by adopting non-anisotropic etching by employing dry etching or wet etching as the etching, the side surface of the conductive pattern can be formed into a curved structure, and an anchor effect can be generated. As a result, it is possible to realize a structure in which the conductive patterns 72A to 72D do not come off from the insulating resin 71.

  Moreover, the back surfaces of the conductive patterns 72A to 72D are exposed on the back surface of the package. Therefore, the back surface of the heat radiating electrode 72D can be fixed to the electrode on the mounting substrate. With this structure, the heat generated from the semiconductor element 73 can be radiated to the electrode on the mounting substrate, and the temperature of the semiconductor element 73 is prevented from rising. Accordingly, a structure capable of increasing the drive current of the semiconductor element 73 can be realized. In addition, as a method of thermally coupling the heat radiation electrode 72D and the electrode on the mounting substrate, they may be connected with a brazing material or a conductive paste, or an insulating material having excellent thermal conductivity such as silicone is disposed between them. Also good.

  In this semiconductor device, since the conductive patterns 72A to 72D are supported by the insulating resin 71 which is a sealing resin, a support substrate is not necessary. This configuration is a feature of the present invention. Since the conductive path of the conventional semiconductor device is supported by a support substrate (flexible sheet, printed circuit board, or ceramic substrate) or supported by a lead frame, a configuration that may be unnecessary is added. However, this circuit device is configured with the minimum necessary components and does not require a support substrate. Therefore, the circuit device is thin and lightweight, and has a feature of being inexpensive because material costs can be suppressed.

  Further, the conductive patterns 72A to 72D are exposed on the back surface of the package. When this region is covered with a brazing material such as solder, the heat radiating electrode 72D has a larger area, so that the brazing material gets wet thickly. Therefore, when fixing on the mounting substrate, it is assumed that the brazing material on the back surface of the external connection electrode 72C does not get wet with the electrode on the mounting substrate, resulting in poor connection.

  In order to solve this, an insulating film 76 is formed on the back surface of the semiconductor device 70. The dotted circles shown in FIG. 7A indicate the external connection electrodes 72C exposed from the insulating coating 76, and the heat radiation electrode 72D. In other words, the portions other than the circle are covered with the insulating film 76, and the sizes of the circles are substantially the same size, so that the thickness of the brazing material formed here is substantially the same. This is the same even after solder printing and after reflow. The same applies to conductive pastes such as Ag, Au, Ag-Pd. This structure can also suppress poor electrical connection. The exposed portion 77 of the heat radiation electrode 72D may be formed larger than the exposed size of the external connection electrode 72C in consideration of the heat dissipation of the semiconductor element. Since the external connection electrodes 72C are all substantially the same size, the external connection electrodes 72C are exposed over the entire region, and a part of the back surface of the heat radiation electrode 72D is insulated with the same size as the external connection electrode 72C. The film 76 may be exposed.

Further, by providing the insulating film 76, the wiring provided on the mounting substrate can be extended to the back surface of the semiconductor device. In general, the wiring provided on the mounting substrate side is arranged to bypass the fixing region of the semiconductor device, but can be arranged without bypassing by forming the insulating film 18. Moreover, since the insulating resin 71 and the insulating adhesive means AD protrude beyond the conductive pattern, a gap can be formed between the wiring on the mounting substrate side and the conductive pattern, and a short circuit can be prevented.

<Reference Example 3>
Reference Example Explaining BGA Type Semiconductor Device 78 First of all, in FIG. 8, the semiconductor element 73 is mounted face down, the flow prevention film DM is disposed on the conductive pattern, and instead of the insulating adhesive means AD. Since this embodiment is substantially the same except that the underfill material AF is adopted, this point will be described.

  First, the bonding electrode 74 and the pad 72A of the semiconductor element 73 are electrically connected via an electrical connection means SD such as a brazing material such as solder, a conductive paste, or an anisotropic conductive resin.

  In order to prevent the flow of the electrical connection means SD, the conductive pattern is provided with a flow prevention film DM. For example, taking solder as an example, a flow prevention film DM is formed on at least a part of the conductive patterns 72A to 72C, and the flow of solder is blocked by this film. The flow preventing film is a film having poor wettability with solder, such as a polymer film (solder resist) or an oxide film formed on the surface of Ni.

  This flow prevention film is provided at least around the region where the solder is disposed, and prevents the flow of brazing material such as solder, conductive paste such as Ag paste, and conductive resin. It has poor wettability. For example, when solder is provided, when the solder is melted, it is blocked by the flow prevention film DM, and a clean hemispherical solder is formed by the surface tension. Further, since a passivation film is formed around the bonding electrode 74 of the semiconductor element to which the solder is attached, the solder gets wet only to the bonding electrode. Therefore, when the semiconductor element and the pad are connected via the solder, the solder is maintained at a certain height in a shell shape. Also, this height can be adjusted by the amount of solder, so that a certain gap can be provided between the semiconductor element and the conductive pattern, and a cleaning liquid can be infiltrated between them, and a low-viscosity adhesive (here underfill material) Can also be infiltrated. Furthermore, it is possible to improve the adhesion with the underfill material AF by covering all the areas other than the connection region with the flow prevention film DM.

  This structure includes a semiconductor element 73, a plurality of conductive patterns 72A to 72C, a heat radiation electrode 72D, an underfill material AF, and an insulating resin 71 that embeds these. As described above, in the arrangement region of the semiconductor element 73, the underfill material AF is filled in the separation grooves on the conductive patterns 72A to 72D and between them. In particular, the underfill material AF is filled in the separation groove 75 formed by etching, and everything including these is sealed with the insulating resin 71. The conductive patterns 72A to 72D and the semiconductor element 73 are supported by the insulating resin 71 and the underfill material AF.

  As the underfill material AF, a material that can penetrate into the gap between the semiconductor element and the conductive pattern is preferable. Further, a filler that functions as a spacer and contributes to heat conduction may be mixed therein.

  In the present invention, since the insulating resin 71 and the underfill material AF are also filled in the separation groove 75, the conductive pattern is prevented from coming off due to the anchor effect. Further, by applying dry etching or wet etching as etching and performing non-anisotropic etching, the side surfaces of the pads 72A can be curved. As a result, it is possible to realize a structure in which the conductive patterns 72A to 72D are not removed from the package.

  Moreover, the back surfaces of the conductive patterns 72 </ b> A to 72 </ b> D are exposed from the insulating resin 71. In particular, the back surface of the heat radiation electrode 72D can be fixed to a circuit pattern on a mounting board (not shown). With this structure, the heat generated from the semiconductor element 73 can be dissipated to the second circuit pattern on the mounting substrate, the temperature rise of the semiconductor element 73 can be prevented, and the drive current of the semiconductor element 73 can be increased correspondingly. When heat dissipation is not considered, the heat dissipation electrode 72D may be omitted. At this time, the circuit pattern of the mounting board is omitted.

  In this semiconductor device, the conductive patterns 72A to 72D are supported by the insulating resin 71 which is a sealing resin and the underfill material AF, so that a support substrate is not necessary. This configuration is a feature of the present invention. As explained in the section of the prior art, the copper foil pattern of the conventional semiconductor device is supported by a support substrate (flexible sheet, printed circuit board or ceramic substrate) or supported by a lead frame, so it is essentially unnecessary. However, a good configuration is added. However, this circuit device is configured with the minimum necessary components and does not require a support substrate. Therefore, the circuit device is thin and lightweight, and has a feature of being inexpensive because it does not require material costs.

  In addition, the semiconductor device has an external connection electrode 72C, a first heat radiation path through the brazing material, a heat radiation electrode 72D, and a second heat radiation path through the brazing material. It can improve more.

Further, the back surface of the semiconductor element 73 may be exposed from the insulating resin film 71. By exposing, the thermal coupling between the heat dissipation means and the semiconductor element 73 can be further improved. However, if the heat dissipation means and the semiconductor element 73 are poorly coupled, an insulating material such as a silicone resin is provided between them. This silicone resin is resistant to heat and has excellent heat conduction due to the inclusion of a filler, and thus has been widely used.

<Reference Example 4>
Reference Example for Explaining BGA Type Semiconductor Device 79 In FIG. 8, the wiring 72B and the external connection electrode 72C are integrally formed on the pad 72A, but here, as shown in FIG. It consists of a connection electrode.

  Further, since the bonding pad 72A is rectangular, the pattern of the heat radiation electrode 72D exposed from the insulating coating 76 is also formed in the same pattern. In consideration of the adhesiveness of the insulating adhesive means AD, the groove 80 is formed so that the heat radiation electrode 72D is divided into a plurality of parts. Note that the symbol W is a thin metal wire.

Further, the semiconductor element 73 may be mounted face down. In this case, an underfill material is employed as shown in FIG. In this embodiment, since the wiring and the external connection electrode are not provided, the heat radiation electrode 72D can be enlarged, and the heat radiation of the semiconductor element is improved.

Sixth Embodiment Explaining Multi-Chip Type Semiconductor Device 81 A semiconductor device 81 on which a plurality of semiconductor chips 72A and 72B are mounted will be described with reference to FIG.

  In the present embodiment, a bridge 83 is employed to electrically connect the first semiconductor chip 73A and the second semiconductor chip 73B. When this bridge 83 is formed of a lead frame, it is formed in an island shape, so it must be supported by suspension leads or adhesive tape. However, as can be seen from the later manufacturing method, since the conductive path is separated after half etching of the conductive foil and resin molding, these support materials are not required. Further, in both semiconductor chips 82A and 82B, the thin metal wires W to be connected are connected by ball bonding and become stitch bonding on the bridge 83 side, so that the impact of stitch bonding is not applied to the chips.

  Further, as shown in FIG. 7, the bonding pad 72 may be integrally provided with wiring and external connection electrodes. In this case, it is better to make the size of the first die pad 82A and the second die pad 82B smaller than the size of the semiconductor chip and enlarge the extended region of the wiring and external connection electrodes. Further, the semiconductor chip 73 and the die pad 82 are electrically connected with a brazing material such as solder. However, when the wiring or the external connection electrode extends under the semiconductor chip, it is preferable to provide the insulating adhesive means AD in consideration of short circuit prevention.

On the other hand, the semiconductor chip 73 may be mounted face down. This is shown in FIG. 10C. This structure is substantially the same as FIG. Since the semiconductor chip and the pad are connected by a brazing material such as solder, the underfill material AF or the like penetrates into this gap.

<Example 2>
Embodiments Explaining Features and Manufacturing Method of Semiconductor Device The features shown in FIGS. 12 to 13 are formed with a projecting portion 91 made of an insulating resin 90, and the conductive path 92 enters inside the projecting portion 91, The recess 93 is formed there. As a result, it is possible to increase the connection strength of the solder 94, prevent a short circuit between the solder or the conductive paths 92, and reduce the friction coefficient of the back surface of the semiconductor device.

  Now, the manufacturing method will be described with reference to FIGS.

  First, as shown in FIG. 14, a sheet-like conductive foil 100 is prepared. The conductive foil 100 is selected in consideration of the adhesiveness, bonding property, and plating property of the brazing material, and a rolled conductive foil mainly composed of Cu is used as the material. In addition, impurities are diffused to add rigidity to the conductive foil so that handling in each process becomes easy. An example of this impurity is shown in FIG. 2B.

  The thickness of the conductive foil is preferably about 35 μm to 300 μm in consideration of later etching, and here, a copper foil of 70 μm (2 ounces) is employed. However, it is basically good if it is 300 μm or more and 35 μm or less. As will be described later, it is only necessary that the separation groove 101 shallower than the thickness of the conductive foil 100 can be formed. In addition, when considering a later transfer mold, a mold of a transfer mold generally used in a post process, and a standard conductive foil adopted for this, the size of the conductive foil is about 220 mm in length, ~ 75 mm in width, It is better to have a thickness of about 300 mm and cut into strips. If this size is adopted, a commercially available transfer mold apparatus, mold, and conductive foil can be adopted, and a merit can be achieved in terms of cost.

In addition, the sheet-like conductive foil 100 may be prepared by being wound into a roll with a predetermined width, and this may be conveyed to each step described later. (See Figure 14 above)
Subsequently, there is a step of removing the conductive foil 100 excluding at least the region that becomes the conductive path 102 to be thinner than the thickness of the conductive foil 100.

  First, a photoresist (etching resistant mask) PR is formed on the Cu foil 100, and the photoresist PR is patterned so that the conductive foil 100 excluding the region to be the conductive path 102 is exposed (see FIG. 15 above).

  Then, as shown in FIG. 16, etching may be performed through the photoresist PR.

  The depth of the separation groove 101 formed by etching is, for example, 50 μm, and its side surface is roughened by an etching process or a roughening process, so that adhesion to the insulating resin 103 is improved.

  Further, the side wall of the separation groove 101 has a different structure depending on the removing method. This removal process can employ wet etching, dry etching, laser evaporation, and dicing. Moreover, you may form with a press. In the case of wet etching, ferric chloride or cupric chloride is mainly used as the etchant, and the conductive foil is dipped in the etchant or showered with the etchant. Since wet etching is generally non-anisotropic, the side surface has a curved structure as shown in FIGS. 16B and 16C. For example, in FIG. 16B, when an etching-resistant mask having good adhesion is selected or Ni or the like is used, eaves are formed. This is because the conductive path itself constitutes the eaves or the eaves are formed together with the conductive film formed on the conductive paths. Further, depending on the method of forming the etching resistant mask, a semicircle may be drawn as shown in FIG. 16C. In either case, since the curved structure 104 is formed, an anchor effect can be generated.

  In the case of dry etching, etching can be performed anisotropically or non-anisotropically. At present, it is said that Cu cannot be removed by reactive ion etching, but it can be removed by sputtering. Etching can be anisotropic or non-anisotropic depending on sputtering conditions.

  In the case of a laser, the separation groove can be formed by direct laser light irradiation. In this case, the side surface of the separation groove 101 is formed straight.

  In dicing, it is impossible to form a complicated bent pattern, but it is possible to form a lattice-like separation groove.

  In FIG. 16, instead of the photoresist PR, a conductive film resistant to the etching solution may be selectively coated. If the conductive film is selectively deposited on the conductive path, this conductive film becomes an etching protective film, and the separation groove can be etched without employing a resist. Possible materials for this conductive film are Ni, Ag, Au, Pt, Pd, and the like. In addition, these corrosion-resistant conductive films have the feature that they can be used as they are as die pads and bonding pads.

For example, the Ag coating adheres to Au and also to the brazing material. Therefore, if the Au coating is coated on the back surface of the chip, the chip can be thermocompression bonded to the Ag coating on the conductive path 51 as it is, and the chip can be fixed via a brazing material such as solder. Further, since an Au fine wire can be adhered to the Ag conductive film, wire bonding is also possible. Accordingly, there is an advantage that these conductive films can be used as they are as die pads and bonding pads. (See Figure 16 above)
Subsequently, as shown in FIG. 17, there is a step of mounting the circuit element 105 by electrically connecting it to the conductive foil 100 in which the separation groove 101 is formed.

  As described with reference to FIGS. 1 to 13, the circuit element 105 includes a semiconductor element 105 </ b> A such as a transistor, a diode, and an IC chip, and a passive element 105 </ b> B such as a chip capacitor and a chip resistor. Although the thickness is increased, a face-down type semiconductor element such as CSP or BGA represented by a wafer scale CSP or the like can be mounted.

Here, the transistor chip 105A as a bare semiconductor chip is die-bonded to the conductive path 102A, and the emitter electrode and the conductive path 105B and the base electrode and the conductive path 105B are fixed by ball bonding by thermocompression bonding or wedge bonding by ultrasonic waves. The thin metal wires 106 are connected. Reference numeral 105B denotes a passive element and / or an active element such as a chip capacitor. Here, a chip capacitor is adopted and fixed by a brazing material such as solder or a conductive paste 107. (See Figure 17 above)
Further, as shown in FIG. 18, there is a step of attaching an insulating resin 103 to the conductive foil 100 and the separation groove 101. This can be realized by transfer molding, injection molding, or dipping. As the resin material, a thermosetting resin such as an epoxy resin can be realized by transfer molding, and a thermoplastic resin such as polyimide resin or polyphenylene sulfide can be realized by injection molding.

  In the present embodiment, the thickness of the insulating resin coated on the surface of the conductive foil 100 is adjusted so that about 100 μm is coated from the top of the circuit element. This thickness can be increased or decreased in consideration of strength.

  The feature of this step is that the conductive foil 100 that becomes the conductive path 102 becomes the support substrate until the insulating resin 103 is coated. For example, in a CSP using a printed circuit board or a flexible sheet, a conductive path is formed by using a support substrate (printed circuit board or flexible sheet) that is not originally required. In the present invention, the conductive foil 100 serving as a support substrate is It is a material necessary as a conductive path. Therefore, there is a merit that the work can be performed with the constituent materials omitted as much as possible, and the cost can be reduced.

  Further, since the separation groove 101 is formed shallower than the thickness of the conductive foil, the conductive foil 100 is not individually separated as the conductive path 102. Therefore, it can be handled from mounting of circuit elements to dicing, and particularly when molding an insulating resin, it has a feature that the work of transporting to the mold and mounting to the mold becomes very easy. Further, as described above, since impurities are added, rigidity is added to the conductive foil, and workability is further improved.

  Subsequently, there is a step of chemically and / or physically removing the back surface of the conductive foil 100 and separating it as a conductive path 102. Here, this removal step is performed by polishing, grinding, etching, laser metal evaporation, or the like.

  A semiconductor device formed by this separation method is shown in FIGS. 21A to 21C.

  First, FIG. 21A shows a state in which the back surface is finally polished so that the back surface of the conductive path 102 and the back surface of the separation groove 101 coincide with each other.

  Subsequently, FIG. 21B shows a state where etching is performed at least before the separation groove 101 is exposed. In general, the conductive path 102 is recessed from the back surface of the separation groove 102 for over-etching in order to completely separate the conductive path 102.

  Further, FIG. 21C shows a state in which an etching resistant mask is formed on the back surface of the conductive foil 100 at the portion to be the external connection electrode at the stage of FIG. 18 and is etched through this mask. Thereby, a part of the conductive path 102 is formed so as to protrude from the back surface of the separation groove 101.

  The exposed surfaces shown in FIGS. 21A and 21B are indicated by dotted lines in FIG.

  FIG. 19 shows an example of a semiconductor device from which the conductive path 102 is separated. It is separated by wet etching.

Further, an insulating film 108 is formed on the back surface of the semiconductor device in order to prevent a short circuit with the wiring on the mounting substrate. Reference numeral 109 denotes a brazing material such as solder. Since the insulating coating 108 does not wet the brazing material, a clean hemispherical brazing material is formed.
As a result, the conductive paths 102 having a thickness of about 40 μm are separated. (See Figure 20 above)
Note that a conductive film of Au or Ag may be applied to the back surface of the conductive path 102. This conductive film may be formed in advance on the back surface of the conductive foil shown in FIGS. The deposition method is, for example, plating. The conductive film is preferably made of a material that is resistant to etching.

  In this manufacturing method, only the semiconductor chip and the chip capacitor are mounted on the conductive foil 100, but these may be arranged in a matrix form as a unit. In this case, dicing is performed to separate each unit.

<Main effects of the present invention>
As can be seen from the above manufacturing method, various semiconductor devices can be manufactured by this manufacturing method. As an active element (semiconductor chip), a discrete type or BGA type in which one transistor, diode, IC or LSI is mounted, a multi-chip type in which a plurality of the active elements are mounted, a transistor as an active element (semiconductor chip), A variety of semiconductor devices such as diodes, ICs or LSIs, hybrid ICs that are configured by mounting chip resistors and chip capacitors as passive elements, and forming wiring as conductive paths to realize the desired circuit can be developed. .

  By the above manufacturing method, a semiconductor device in which the conductive path is embedded in the insulating resin and the back surface of the conductive path 51 is exposed on the back surface of the insulating resin can be realized.

  This manufacturing method has a feature that the conductive path can be separated using the insulating resin as a support substrate. The insulating resin is a necessary material for embedding the conductive path, and does not require an unnecessary support substrate. Therefore, it has the characteristics that it can be manufactured with a minimum amount of material and cost can be reduced.

  As can be seen from the above manufacturing method, the recess 93 can be formed on the back surface of the conductive path as shown in FIG. In addition, a package in which the curve on the side surface of the conductive path and the curve on the side surface of the separation groove coincide with each other is obtained. Further, since the bottom of the separation groove is formed by non-anisotropic etching, a free area 93 </ b> A drawn with a curved surface and indicated by a triangle is formed.

  Due to the curved surface of the separation groove, even if melted solder is provided in the separation groove portion, the separation groove has an inclination and the solder flows as indicated by the arrow due to the surface tension of the solder, and the island-shaped hemisphere is completely separated Solder can be formed. Further, since the empty area 93A is provided, a solder escape area is formed, and the phenomenon that the melted solder is united adjacent to each other and short-circuited can be suppressed.

  FIG. 12B shows a part of the protruding portion of the separation groove made flat. In the case of etching, the depth of the separation groove varies depending on the interval between the conductive paths, and the height of the protrusion 91 may vary. In this case, it can be assumed that the semiconductor device cannot be arranged horizontally. In this case, after separating the conductive paths, the back surface of the semiconductor device is polished to make all the heights of the protruding portions uniform. The portion indicated by FL is the flat portion.

  FIG. 13 shows a structure in which a semiconductor device is mounted on a mounting substrate 520. Since the circuit pattern 521 formed on the conductive path of the mounting substrate is coupled to the conductive path 522 connected to the semiconductor chip, there is an advantage that the heat of the semiconductor chip can be released to the circuit pattern.

  Moreover, the code | symbol H shown in FIG. 12 shows how much the top part of the protrusion part 91 protrudes from the back surface of the conductive path. Here, H is about 20 μm. The brazing material solidified on the back surface of the conductive path must be formed higher than the protrusion 91 in the solidified state. However, at the time of melting, the solder 94 is crushed by the weight and external force of the element, the protruding portion 91 serves as a stopper, and the protruding portion contacts the mounting substrate 520 as shown in FIG. However, since the protrusion 91 draws a curve, it also helps that the coefficient of friction on the back surface of the semiconductor device is small, which makes it easy to move the semiconductor device and facilitates self-alignment.

  FIG. 22 explains how much the size is reduced by employing the semiconductor device of the present invention. The photograph shown in the figure is the same magnification, and shows a single SMD employing a lead frame from the left, a composite SMD employing a lead frame, and a semiconductor device of the present invention. A single product SMD is molded with one TR, and a composite TR is molded with two TRs. The semiconductor device of the present invention is a semiconductor device on which the circuit shown in FIG. 6 is mounted, and four TRs are sealed. As is apparent from the figure, the size of the semiconductor device is only slightly larger than that of the composite SMD including the lead frame, even though the element twice that of the composite SMD is sealed. A semiconductor device in which one TR is sealed is shown on the rightmost side. As will be understood, a small and thin semiconductor device can be realized by the present invention, which is most suitable for a portable electronic device.

  Finally, a mounting board on which the present semiconductor device is mounted is shown in FIG. A circuit pattern is re-formed and mounted on the conventional mounting substrate shown in FIG. As is clear from FIG. 23, the circuit pattern of the mounting substrate is simplified and the interval can be formed wide. This makes it possible to form the circuit pattern of the mounting board more densely and to reduce the size of the mounting board. In addition, the number of die bonding and wire bonding of the semiconductor chip is reduced, and the number of assembly steps on the mounting substrate is greatly reduced. In the mounting substrate, some kinds of fine metal wires are used. For example, in FIG. 25, it is assumed that 40 μm Au wire or Al wire used for a small signal system, and 150 μm and 300 μm Al wires used for a large signal system are adopted. If all of the semiconductor elements connected to at least one of the three types of metal wires have this structure, the bonding of the metal wires is completely unnecessary. For example, the Au wire and the Al wire are connected by different bonders because the bonder mechanism is completely different. However, if all the semiconductor elements connected by the Au wire are packaged with this structure and the portion jumped by the Au wire is replaced by the Al wire, no Au wire bonder is required for assembling the mounting substrate. This greatly leads to simplification of the assembly process.

  Further, in the lead frame package used in the past, the suspension leads, tie bars and the like cut on the side surfaces of the package are always exposed. Therefore, the contact with the exposed portion is considered and the package cannot be placed in contact with the package. However, since the present invention is entirely covered with an insulating resin except for the back surface, the semiconductor device and the semiconductor device can be placed in contact with each other on the mounting substrate.

  Furthermore, the back surface of the semiconductor device has a curved protrusion portion made of an insulating resin, and the back surface has a very small coefficient of friction. Further, coupled with the fact that the semiconductor device itself is thin and light, there is a feature that the semiconductor device is naturally self-aligned during soldering.

  If a metal substrate is employed as the mounting substrate, the heat of the semiconductor device can be released through the metal substrate, and the temperature rise of the entire mounting substrate as a module can be suppressed.

It is a figure explaining the XY film employ | adopted as the semiconductor device of this invention. It is a figure explaining the characteristic of the XY film | membrane of FIG. It is a figure explaining the XY film employ | adopted as the semiconductor device of this invention. It is a figure explaining the surface structure of an XY film. It is a figure explaining the semiconductor device of the present invention. It is a figure explaining the semiconductor device of the present invention. It is a figure explaining the semiconductor device of the present invention. It is a figure explaining the semiconductor device of the present invention. It is a figure explaining the semiconductor device of the present invention. It is a figure explaining the semiconductor device of the present invention. It is a figure explaining the conductive pattern employ | adopted as the semiconductor device of this invention. It is a figure explaining the semiconductor device of the present invention. It is a figure explaining the mounting board | substrate which mounted the semiconductor device of this invention. It is a figure explaining the manufacturing method of the semiconductor device of this invention. It is a figure explaining the manufacturing method of the semiconductor device of this invention. It is a figure explaining the manufacturing method of the semiconductor device of this invention. It is a figure explaining the manufacturing method of the semiconductor device of this invention. It is a figure explaining the manufacturing method of the semiconductor device of this invention. It is a figure explaining the manufacturing method of the semiconductor device of this invention. It is a figure explaining the manufacturing method of the semiconductor device of this invention. It is a figure explaining the manufacturing method of the semiconductor device of this invention. It is a figure explaining the size of the semiconductor device of the present invention. It is a figure explaining the hybrid integrated circuit board which mounted the semiconductor device of the present invention. It is a figure explaining the example of a circuit employ | adopted as the semiconductor device of this invention. It is a figure explaining the conventional hybrid integrated circuit board using the circuit of FIG. It is a figure explaining the conventional semiconductor device.

Explanation of symbols

40, 46 conductive path
41, 47 Grain boundary
42 Fine metal wire
43 Semiconductor chip
44 Insulating resin
45, 48 crystal grains
50 Wiring
51 Die pad or bonding pad
52 Curved structure
53 Eaves

Claims (2)

A semiconductor element;
A pad electrically connected to the semiconductor element with a fine metal wire, a die pad mounted with a back surface of the semiconductor element fixed thereto , and electrically connected to the pad and the die pad, and between the pad and the die pad. and a wiring portion extending growth of X-axis -Y-axis direction is larger than the Z-axis direction, a conductive path made of rolled conductive film of Cu formed by rolling a main material,
A multi-chip semiconductor device having the semiconductor element, an insulating resin that seals the conductive path and exposes a back surface of the conductive path ;
A semiconductor module comprising a mounting substrate on which the semiconductor device is mounted. The conductive path is mainly made of copper,
In the conductive path, Ni, Si, Zn and Sn are mixed as impurities,
Zn, Sn and Cr mixed as impurities ,
Or Zn, Fe and P mixed with impurities ,
The semiconductor module according to claim 1, comprising:

Images