JP4744909B2 - Hysteresis comparator - Google Patents

Description

  The present invention relates to a hysteresis comparator including a constant current type hysteresis circuit.

  A normal comparator compares an input voltage with a reference voltage and outputs a binary voltage according to the comparison result. In contrast, the hysteresis comparator has a high reference voltage (hereinafter referred to as “first reference voltage”) when the input voltage changes from the low level to the high level, and a low reference when the input voltage changes from the high level to the low level. Voltage (hereinafter referred to as “second reference voltage”). The hysteresis comparator is mainly composed of a comparator and a hysteresis circuit. As a hysteresis circuit, a constant current type hysteresis circuit including a constant current source is known (for example, see Patent Document 1). In the constant current type hysteresis circuit, the reference voltage has a hysteresis width by branching the output signal of the comparator and performing on / off control of the current from the constant current source in accordance with the branched signal.

In the above-described constant current type hysteresis circuit, a certain time is required for the rising of the constant current source, and therefore a certain time is required until the operation of the hysteresis circuit is stabilized. As a result, during high-speed operation, a situation occurs in which the output of the comparator is switched before the operation of the hysteresis circuit is stabilized. For this reason, when a hysteresis comparator including a constant current type hysteresis circuit is operated at high speed, there is a high possibility of malfunction.
Japanese Patent Laid-Open No. 7-130082

  The present invention provides a hysteresis comparator that does not cause malfunction even when the operation speed is increased.

  One aspect of the present invention is a comparator that compares an input voltage with a reference voltage, generates a first constant current, maintains the reference voltage when the input voltage is smaller than the reference voltage, and the input voltage exceeds the reference voltage. The hysteresis comparator includes a hysteresis circuit that decreases the reference voltage according to the first constant current when the input voltage exceeds the reference voltage and a current supply circuit that adds current to the first constant current for a certain period after the input voltage exceeds the reference voltage. This is the gist.

  According to the present invention, it is possible to provide a hysteresis comparator that does not cause malfunction even when the operation speed is increased.

  Next, an embodiment of the present invention will be described with reference to the drawings. In the description of the drawings in the following embodiments, the same or similar parts are denoted by the same or similar reference numerals.

  As shown in FIG. 1, the hysteresis comparator according to the embodiment of the present invention includes a comparator 4, a hysteresis circuit 5, a current supply circuit 6, an output voltage generation circuit 7, and a current supply control circuit 8. The comparator 4 compares the input voltage Va with the reference voltage Vb. In the example shown in FIG. 1, the comparator 4 outputs a high level signal when the input voltage Va is smaller than the reference voltage Vb, and outputs a low level signal when the input voltage Va exceeds the reference voltage Vb. . The hysteresis circuit 5 generates the first constant current I1, maintains the reference voltage Vb when the input voltage Va is smaller than the reference voltage Vb, and the first constant current when the input voltage Va exceeds the reference voltage Vb. The reference voltage Vb is decreased according to I1. The current supply circuit 6 adds the current I5 to the first constant current I1 in a certain period after the input voltage Va exceeds the reference voltage Vb.

  Further, the output voltage generation circuit 7 switches the output voltage OUT at the timing when the reference voltage Vb changes. The current supply control circuit 8 stops the operation of the current supply circuit 6 in response to switching of the output voltage OUT.

  A first resistor R <b> 1 is connected between the first input terminal 1 to which the variable voltage value first input voltage V <b> 1 is applied and the negative input terminal (−) of the comparator 4. A second resistor R2 and a constant current source 12 are connected in parallel between the negative input terminal (−) of the comparator 4 and the low-level power supply GND. The current from the first resistor R1 flows to the low power supply GND through the second resistor R2 and the constant current source 12. A third resistor R3 is connected between the second input terminal 2 to which the second input voltage V2 having a fixed voltage value is applied and the positive input terminal (+) of the comparator 4. The first input voltage V1 may be directly input to the negative input terminal (−) of the comparator 4 without providing the first resistor R1, the second resistor R2, and the constant current source 12. A configuration without the third resistor R3 and the second input voltage V2 may be employed.

  A first inverter 13 and a second inverter 14 are sequentially connected to the output of the comparator 4. One end of a resistor R8 is connected to the output of the second inverter 14. The first inverter 13 inverts the output signal of the comparator 4. The second inverter 14 further inverts the output signal of the first inverter 13.

  The hysteresis circuit 5 further includes a resistor R4, a first constant current source 51, a second constant current source 11, a first current mirror circuit 50, and a first switch transistor M3. The first constant current source 51 generates a first constant current I1. The second constant current source 11 generates a second constant current I2. The resistor R4 changes the reference voltage Vb by generating a voltage proportional to the second constant current I2. The first current mirror circuit 50 reduces the second constant current I2 flowing through the resistor R4 according to the first constant current I1. The first switch transistor M3 operates the first current mirror circuit 50 when the input voltage Va exceeds the reference voltage Vb.

  The first current mirror circuit 50 includes a first mirror transistor M1 and a second mirror transistor M2. As each of the first switch transistor M3, the first mirror transistor M1, and the second mirror transistor M2, for example, an n-type channel MOS transistor (hereinafter referred to as “nMOS transistor”) can be used.

  The resistor R4 is connected between the positive input terminal (+) of the comparator 4 and the low-level power supply GND. The first switch transistor M3 has a drain connected to the first constant current source 51, a gate connected to the other end of the resistor R8, and a source connected to the low potential power supply GND. The first mirror transistor M1 has a drain connected to the second constant current source 11 and a source connected to the low potential power supply GND. The second mirror transistor M2 has a drain connected to the first constant current source 51, a gate connected to the gate of the first mirror transistor M1 and its own drain, and a source connected to the lower power supply GND.

  When the output signal CS of the second inverter 14, that is, the output signal of the comparator 4, is at a high level, the first switch transistor M3 is in a conducting state, and the first constant current I1 from the first constant current source 51 is the first switch transistor. It flows to the lower power supply GND via M3. When the output signal of the comparator 4 is switched from the high level to the low level, the first switching transistor M3 becomes non-conductive, and the first constant current I1 from the first constant current source 51 is low through the second mirror transistor M2. It flows to the power supply GND.

  A part of the current I2 corresponding to the first constant current I1 flows through the first mirror transistor M1. Therefore, the current I2 flowing through the resistor R4 decreases and the reference voltage Vb decreases. As a result, the reference voltage Vb can be changed.

  The current supply circuit 6 further includes a first current supply transistor M4 and a first current adjustment resistor R5. As the first current supply transistor M4, for example, a p-type channel MOS transistor (hereinafter referred to as “pMOS transistor”) can be used.

  The first current supply transistor M4 has a source connected to the high-level power supply VCC, a gate connected to the current supply control circuit 8, and a drain connected to one end of the first current adjustment resistor R5. The other end of the first current adjusting resistor R5 is connected to the respective drains of the first switch transistor M3 and the second mirror transistor M2.

  The output voltage generation circuit 7 includes a third constant current source 72, a fourth constant current source 71, a second current mirror circuit 70, a second switch transistor M7, a second current supply transistor M8, and a second current adjustment transistor. A resistor R6, a third current supply transistor M9, and a third current adjustment resistor R7 are provided. That is, the output voltage generation circuit 7 is configured in the same manner as the hysteresis circuit 5 except that the output voltage generation circuit 7 includes a third current supply transistor M9 and a third current adjustment resistor R7.

  The third constant current source 72 generates a third constant current I3. The fourth constant current source 71 generates a fourth constant current I4. The second current mirror circuit 70 switches the output voltage OUT using the third constant current I3 and the fourth constant current I4. The second switch transistor M7 operates the second current mirror circuit 70 in response to switching of the output signal of the comparator 4.

  When the output signal CS of the second inverter 14, that is, the output signal of the comparator 4, is at a high level, the second switch transistor M7 becomes conductive, and the third constant current I3 from the third constant current source 72 is the second switch transistor. It flows to the lower power supply GND via M7.

When the output signal of the comparator 4 is switched from the high level to the low level, the second switch transistor M7 becomes non-conductive, and the third constant current I3 from the third constant current source 72 is low through the fourth mirror transistor M6. It flows to the power supply GND. The current I4 corresponding to the third constant current I3 flows through the third mirror transistor M5, the potential of the connection node n ₁ of the third mirror transistor M5 and the fourth constant current source 71 is reduced.

  The second current mirror circuit 70 includes a third mirror transistor M5 and a fourth mirror transistor M6. Here, as each of the second switch transistor M7, the third mirror transistor M5, and the fourth mirror transistor M6, for example, an nMOS transistor can be used. As each of the second current supply transistor M8 and the third current supply transistor M9, for example, a pMOS transistor can be used.

  In the second switch transistor M7, the drain is connected to the third constant current source 72, the gate is connected to the other end of the resistor R8, and the source is connected to the low potential power supply GND. The third mirror transistor M5 has a drain connected to the fourth constant current source 71 and a source connected to the low potential power supply GND. The fourth mirror transistor M6 has a drain connected to the third constant current source 72, a gate connected to the gate of the third mirror transistor M5 and its own drain, and a source connected to the low potential power supply GND.

  The second current supply transistor M8 has a source connected to the high-level power supply VCC, a gate connected to the current supply control circuit 8, and a drain connected to one end of the second current adjustment resistor R6. The other end of the second current adjusting resistor R6 is connected to the drains of the second switch transistor M7 and the fourth mirror transistor M6.

  The third current supply transistor M9 has a source connected to the high-level power supply VCC, a gate connected to the output of the first inverter 13, and a drain connected to one end of the third current adjustment resistor R7. The other end of the third current adjustment resistor R7 is connected to the drain of the third mirror transistor M5.

  The resistor R8 is used to configure an RC filter using the gate capacitances of the first switch transistor M3 and the second switch transistor M7, but may be configured without the resistor R8.

Further, the current supply control circuit 8 includes a Schmitt inverter 81, an inverter 82, a NAND circuit 83, and an inverter 84. However, a normal inverter may be used instead of the Schmitt inverter 81. The input of the Schmitt inverter 81 is connected to the connection node n ₁ of the third mirror transistor M 5 and the fourth constant current source 71. The input of the inverter 82 is connected to the output of the Schmitt inverter 81. The inverter 84 has an input connected to the output of the Schmitt inverter 81 and an output connected to the output terminal 3. The NAND circuit 83 has inputs connected to the outputs of the inverter 82 and the first inverter 13, and outputs connected to the gates of the first current supply transistor M4 and the second current supply transistor M8.

The Schmitt inverter 81 inverts the potential generated at the connection node n ₁ of the second current mirror circuit 70 and the fourth constant current source 71. The inverter 82 inverts the output signal of the Schmitt inverter 81 and transmits it to the NAND circuit 83. The inverter 84 inverts the output signal of the Schmitt inverter 81 and transmits it to the output terminal 3. The NAND circuit 83 performs an NAND operation on the output signals of the inverter 82 and the first inverter 13, and supplies the operation result to the gates of the first current supply transistor M4 and the second current supply transistor M8.

  Further, as shown in FIG. 2, the hysteresis comparator shown in FIG. 1 switches the output voltage OUT according to the first input voltage V1 and the second input voltage V2. The detailed operation of the hysteresis comparator shown in FIG. 1 near time T1 in FIG. 2 will be described below with reference to the waveform diagram shown in FIG.

  (A) The output signal CS of the second inverter 14 shown in FIG. 1 is maintained at a high level during the period from time t0 to time t1 in FIG. 3, which is in the vicinity of time T1 in FIG. Therefore, the first switch transistor M3 and the second switch transistor M7 shown in FIG. 1 are kept in a conductive state. Therefore, the constant currents I1 and I3 generated by the first constant current source 51 and the third constant current source 72 flow to the lower power supply GND through the first switch transistor M3 and the second switch transistor M7, respectively. The current mirror circuit 50 and the second current mirror circuit 70 do not operate. At this time, the output voltage OUT is at a high level, and the output signal of the inverter 82 is kept at a high level.

  (B) At time t1, the output signal CS of the second inverter 14 is switched from the high level to the low level. That is, the output signal of the first inverter 13 is switched from the low level to the high level. As a result, the output signal of the NAND circuit 83 is switched from the high level to the low level. When the output signal of the NAND circuit 83 becomes a low level, the first current supply transistor M4 and the second current supply transistor M8 are turned on. As a result, a current path is formed by the first current supply transistor M4 and the first current adjustment resistor R5. A current path is constituted by the second current supply transistor M8 and the second current adjustment resistor R6.

  When the output signal CS of the second inverter 14 falls from the high level to the low level, the first switch transistor M3 and the second switch transistor M7 are turned off. Therefore, the first current mirror circuit 50 and the second current mirror circuit 70 operate. Here, in addition to the first constant current I1 from the first constant current source 51, the current I5 is supplied to the first current mirror circuit 50 via the first current supply transistor M4 and the first current adjustment resistor R5. Since it is supplied, the gate potential of the second mirror transistor M2 rises sharply. Similarly, the fourth mirror transistor M6 of the second current mirror circuit 70 includes a second current supply transistor M8 and a second current adjustment resistor R6 in addition to the third constant current I3 from the third constant current source 72. Since the current I6 is supplied via, the gate potential of the fourth mirror transistor M6 rises steeply.

  When the first current mirror circuit 50 is operated, a part of the constant current I2 supplied from the second constant current source 11 to the resistor R4 flows to the lower power supply GND via the first mirror transistor M1. Therefore, the voltage generated at the resistor R4 is lowered, and the reference voltage Vb applied to the comparator 4 is also lowered. The time from the time t1 when the output signal CS of the second inverter 14 switches to the time t2 when the reference voltage Vb decreases can be set to about 5 ns, for example.

(C) Further, when the second current mirror circuit 70 is operated, the potential of the connection node n ₁ of the third mirror transistor M5 and the fourth constant current source 71 is shifted to the low potential power supply GND side, and the potential of the connection node n ₁ is descend. Therefore, the output signal of the Schmitt inverter 81 becomes high level, and the output signal of the inverter 84, that is, the output voltage OUT becomes low level near the time t3. The time from time t2 to time t3 can be about 13 ns.

  (D) When the output voltage OUT is switched to the low level, the output signal of the inverter 82 becomes the low level, and the output signal of the NAND circuit 83 is switched from the low level to the high level. Therefore, the first current supply transistor M4 and the second current supply transistor M8 are turned off, and the first current mirror circuit 50 and the second current from the first current supply transistor M4 and the second current supply transistor M8. Supply of the currents I5 and I6 to the mirror circuit 70 is stopped.

  Next, a comparative example of the hysteresis comparator according to the embodiment of the present invention will be briefly described with reference to the waveform diagram shown in FIG. As a comparative example, a configuration that does not include the current supply circuit 6, the output voltage generation circuit 7, and the current supply control circuit 8 will be described.

  (A) During the period from time t0 to time t1 in FIG. 4, the output signal CS of the second inverter 14 is at a high level (5 V), and the gate potential of the second mirror transistor M2, that is, the gate potential of the second mirror transistor M2. Is at a low level (0 V). The gate-drain parasitic capacitance of the first switch transistor M3 and the gate-drain parasitic capacitance of the first mirror transistor M1 are capacitively coupled. Therefore, when the gate of the first switch transistor M3 changes transiently from the high level (5V) to the low level (0V), the gates of the first mirror transistor M1 and the second mirror transistor M2 are affected.

  (B) When the output signal CS of the second inverter 14 falls from the high level (5V) to the low level (0V) around time t1 in FIG. 4, the gate potential of the first mirror transistor M1 is affected and the gate An inversion phenomenon occurs in which the potential transitions to the negative side.

  (C) Although the output voltage OUT is switched at time t2, the time t3 when the reference voltage Vb is decreased is after the switching of the output voltage OUT. Note that the time from time t1 to time t3 requires, for example, about 49 ns.

  Hereinafter, with reference to the waveform diagram shown in FIG. 5, the operation at the time of return of the hysteresis comparator according to the embodiment of the present invention, that is, the detailed operation in the vicinity of time T2 in FIG.

  (A) At time t1, the output signal CS of the second inverter 14 is switched from the low level to the high level. When the output signal CS of the second inverter 14 is switched from the low level to the high level, the first switch transistor M3 and the second switch transistor M7 are turned on, and the first current mirror circuit 50 and the second current mirror circuit at time t2. The operation of 70 stops.

(B) When the operation of the first current mirror circuit 50 stops, the reference voltage Vb increases. When the operation of the second current mirror circuit 70 is stopped, the potential of the connection node n ₁ of the fourth constant current source 71 and the third mirror transistor M5 increases. Here, since the output signal of the first inverter 13 is switched from the high level to the low level, the third current supply transistor M9 becomes conductive. When the third current supply transistor M9 becomes conductive, it can be promoted that the potential of the connection node n ₁ of the fourth constant current source 71 and the third mirror transistor M5 increases.

  (C) In the vicinity of time t3, the output voltage OUT switches to a high level. The time required from time t2 to time t3 is, for example, about 17 ns.

  Next, a comparative example of the hysteresis comparator according to the embodiment of the present invention will be briefly described with reference to the waveform diagram shown in FIG. As a comparative example, a configuration that does not include the current supply circuit 6, the output voltage generation circuit 7, and the current supply control circuit 8 will be described.

  (A) When the output voltage OUT is not generated by the output voltage generation circuit 7, the time required from the time t2 when the reference voltage Vb increases until the time t3 when the output voltage OUT switches to the high level is, for example, about 10.7 ns. .

  As described above, according to the hysteresis comparator according to the embodiment of the present invention, the current supply circuit 6 is provided to prevent the gate potential of the second mirror transistor M2 from transitioning to the negative side and reduce the reference voltage Vb. The time required for this can be greatly reduced. Further, by providing an output voltage generation circuit 7 for generating the output voltage OUT separately from the comparator 4, the supply of the current I5 supplied from the first current supply transistor M4 of the current supply circuit 6 at the time of detection is stopped at high speed. The time for shifting to a stable state after detection can be shortened. Further, by providing the current supply control circuit 8, the current supply circuit 6 can be automatically stopped. Therefore, it is possible to provide a hysteresis comparator that does not cause malfunction even when the operation speed is increased.

(First modification)
As a first modification of the embodiment of the present invention, as shown in FIG. 7, an output voltage generation circuit 7b includes a fourth constant current source 71, a third constant current source 72, a second current mirror circuit 70, a second switch. The configuration may include a transistor for transistor M7, a second current supply transistor M8, and a second current adjustment resistor R6. That is, the output voltage generation circuit 7b shown in FIG. 7 does not include the third current supply transistor M9 and the third current adjustment resistor R7 shown in FIG.

  When the third current supply transistor M9 and the third current adjustment resistor R7 are not provided, the time required for switching the output voltage OUT at the time of recovery increases, but the operation at the time of detection is the same as the waveform diagram shown in FIG. Same operation.

(Second modification)
As a second modification of the embodiment of the present invention, as shown in FIG. 8, an output voltage generation circuit 7c includes a fourth constant current source 71, a third constant current source 72, a second current mirror circuit 70, and a second current mirror circuit 70. A configuration including a switching transistor M7 may also be used. That is, the output voltage generation circuit 7c shown in FIG. 7 includes the second current supply transistor M8, the second current adjustment resistor R6, the third current supply transistor M9, and the third current adjustment resistor R7 shown in FIG. Not equipped.

  When the second current supply transistor M8, the second current adjustment resistor R6, the third current supply transistor M9, and the third current adjustment resistor R7 are not provided, the first current supply for the current supply circuit 6 after detection is provided. Although the time for stopping the supply of the transistor M4 increases and the time required for switching the output voltage OUT at the time of recovery increases, the operation for decreasing the reference voltage Vb is the same as the waveform diagram shown in FIG.

(Other embodiments)
As mentioned above, although this invention was described by embodiment, it should not be understood that the description and drawing which form a part of this indication limit this invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  As a hysteresis comparator according to another embodiment, an arbitrary power supply may be added between the second resistor R2 and the fourth resistor R4 shown in FIG. 1 and the low potential power supply GND.

  In the above-described embodiment, an example in which pMOS transistors are used as the first current supply transistor M4, the second current supply transistor M8, and the third current supply transistor M9 has been described. However, instead of the pMOS transistor, for example, pnp A type bipolar transistor or the like may be used. Furthermore, a configuration without the first current adjusting resistor R5, the second current adjusting resistor R6, and the third current adjusting resistor R7 is also possible.

  In addition, although an example in which the NAND circuit 83 is used for the current supply control circuit 8 has been described, the NAND circuit 83 is not limited to the NAND circuit 83 as long as similar logic can be realized.

  Thus, it should be understood that the present invention includes various embodiments and the like not described herein. Therefore, the present invention is limited only by the invention specifying matters in the scope of claims reasonable from this disclosure.

It is a circuit diagram which shows the structural example of the hysteresis comparator which concerns on embodiment of this invention. It is a wave form diagram which shows the outline | summary of operation | movement of the hysteresis comparator which concerns on embodiment of this invention. It is a wave form diagram which shows the detailed operation example at the time of the detection of the hysteresis comparator which concerns on embodiment of this invention. It is a wave form diagram which shows the comparative example for demonstrating the effect at the time of the detection of the hysteresis comparator which concerns on embodiment of this invention. It is a wave form diagram which shows the detailed operation example at the time of the return | restoration of the hysteresis comparator which concerns on embodiment of this invention. It is a wave form diagram which shows the comparative example for demonstrating the effect at the time of the reset of the hysteresis comparator which concerns on embodiment of this invention. It is a circuit diagram which shows the structural example of the hysteresis comparator which concerns on the 1st modification of embodiment of this invention. It is a circuit diagram which shows the structural example of the hysteresis comparator which concerns on the 2nd modification of embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 4 ... Comparator 5 ... Hysteresis circuit 6 ... Current supply circuit 7, 7b, 7c ... Output voltage generation circuit 8 ... Current supply control circuit

Claims (3)

A comparator having a negative input terminal to which an input voltage is input and a positive input terminal to which a reference voltage is input;
A first constant current source with one end connected to the high-level power supply, a second constant-current source with one end connected to the high-level power supply, the other end connected to the positive terminal, one end connected to the positive terminal, and the other end A resistor connected to the lower power supply, a drain connected to the other end of the second constant current source, a first mirror transistor connected to the lower power supply, a drain connected to the other end of the first constant current source, and a gate Is connected to the lower power supply, the drain and the gate are connected to each other, the drain is connected to the drain of the second mirror transistor, and the gate is connected to the lower mirror power source. A hysteresis circuit comprising, at the output of the comparator, a first switching transistor having a source connected to a low-level power supply;
A third constant current source having one end connected to the high level power source, a fourth constant current source having one end connected to the high level power source, a drain connected to the other end of the fourth constant current source, and a source connected to the low level power source. The third mirror transistor, the drain is connected to the other end of the third constant current source, the gate is connected to the gate of the third mirror transistor, the source is connected to the lower power supply, and the drain and the gate are connected to each other. An output voltage generation circuit comprising: a fourth mirror transistor; a drain connected to the drain of the fourth mirror transistor; a gate connected to the output of the comparator; and a source connected to a low power supply;
An inverter circuit having an input connected between the fourth constant current source and the third mirror transistor; and an arithmetic circuit having an input connected to the output of the inverter circuit and the output of the comparator; A current supply control circuit in which the output of is transmitted to the output terminal;
A current supply circuit including a first current supply transistor having a source connected to a high-level power supply, a gate connected to an output of the arithmetic circuit, and a drain connected between the first constant current source and the second mirror transistor;
A hysteresis comparator comprising:   The output voltage generation circuit further includes a second current supply transistor having a source connected to a high-level power supply, a gate connected to the output of the arithmetic circuit, and a drain connected between the third constant current source and the fourth mirror transistor. The hysteresis comparator according to claim 1, further comprising:   The output voltage generation circuit further includes a third current supply transistor having a source connected to a high-level power supply, a gate connected to the output of the arithmetic circuit, and a drain connected between the fourth constant current source and the third mirror transistor. The hysteresis comparator according to claim 1, further comprising a hysteresis comparator.

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