JP4745956B2 - Simulation device - Google Patents

Description

The present invention relates to simulation equipment, about the particular simulation equipment available in analog simulator.

  Recently, a resistance random access memory (ReRAM) element has attracted attention. The resistance change memory element can be read at a high speed, operates at a high temperature, and can be manufactured at a low cost in a mixed use. Among these, a resistance change memory element (unipolar resistance change memory element) whose resistance value changes by electrical stimulation of a single sign has a good affinity with a silicon process, and is composed of a single layer film of an inexpensive material, and is mixedly loaded. Suitable as a non-volatile memory.

  The resistance value of the unipolar resistance change memory element changes from a high resistance state to a low resistance state by applying a voltage higher than the set voltage. This is called a set. Further, by applying a voltage higher than the reset voltage and lower than the set voltage, the low resistance state is changed to the high resistance state. This is called reset. Reading is performed by applying a voltage smaller than the reset voltage. For example, the set voltage is 1.6V and the reset voltage is 0.75V. The resistance value in the high resistance state is 80 kΩ when 1.6 V is applied, and the resistance value in the low resistance state is 4 kΩ. In addition, the resistance value in the high resistance state is a feature of the unipolar resistance change memory element that the resistance value varies greatly depending on the voltage applied to itself.

FIG. 34 is a diagram for explaining general voltage-current characteristics of a unipolar resistance change memory element. In this figure, the horizontal axis represents voltage (V), and the vertical axis represents current (mA).
For example, the curve shown between A and B in the figure shows the relationship between voltage and current when the resistance is in a high resistance state, and the IV curve between A and B is not linear. This is because, as described above, when the resistance is in a high resistance state, the resistance value varies greatly depending on the voltage applied to itself. When the voltage is gradually increased along the IV curve, the resistance shifts from the high resistance state to the low resistance state at the point B which is the set voltage.

When the resistance is in a low resistance state, the resistance value is constant, so this time, it follows the linear IV curve between A and C.
And in order to start reset, when a voltage is raised on the IV curve shown between AC, resistance will change from a low resistance state to a high resistance state again at the C point which is a reset voltage.

  Writing and reading of the resistance change memory element is performed using the characteristic that the resistance value changes by the application of such a voltage. As a resistance material of the unipolar resistance change memory element, for example, a report example of a resistance change memory element using a transition metal oxide is disclosed (for example, Non-Patent Document 1).

  The unipolar resistance change memory element is used after first applying a high voltage to cause a phenomenon such as dielectric breakdown in the resistance change memory element. This is called forming. The forming may be performed once for one resistance change memory element. Forming may or may not be necessary depending on the material and film thickness. A voltage necessary for forming is referred to as a forming voltage. The forming voltage is higher than the set voltage, for example, about 3V.

  However, when the resistance change memory element is set and enters a low resistance state, if the large current flows excessively, the resistance change memory element is destroyed. For this reason, it is necessary to limit the electric current at the time of setting. In the case of a unipolar resistive memory element, the setting takes place in a few ns. On the other hand, the reset requires a time of 100 ns or more. Further, since the resistance value becomes high at the time of resetting, it is necessary to control the voltage so that a large voltage is applied at this moment and it is not set again.

  Since such a set voltage and a reset voltage vary depending on the unipolar resistance change memory element, it is necessary to apply a voltage sufficiently higher than the set voltage to the resistance change memory when setting. A voltage that is sufficiently high and sufficiently lower than the set voltage needs to be applied to the resistance change memory element.

  By the way, in designing a resistance change memory product and a resistance change memory CTEG (Circuit Test Element Group) using a resistance change memory element, circuit simulation before design plays an important role. This is because the element attributes that make up a circuit differ depending on the product, and therefore it is necessary to perform circuit simulation on the entire memory circuit or a part of the circuit at the design stage in order to guarantee the operation of the circuit. is there. Further, the circuit mounted on the CTEG used for demonstrating the operation of the memory circuit also needs to be verified by circuit simulation for the same reason.

  Here, a commercially available analog circuit simulator HSPICE (registered trademark of synopsys) is generally used for circuit simulation of a memory circuit that operates in an analog manner. When a circuit simulation is performed using HSPICE, a library that summarizes element attributes is required.

  For example, even when a circuit simulation using a resistance change memory element is performed, the element attribute of a part for storing data in the resistance change memory element needs to be included in the library. However, a library that enables simulation of the resistance change memory element is not provided at present. Therefore, at present, the operation verification of the resistance change memory element cannot be confirmed by simulation using an analog circuit simulator.

  However, when verifying the read operation of a circuit using a resistance change memory element, the resistance value changes as a resistance change memory element by one pure resistance having a constant resistance value or by a voltage applied to itself. A method of performing simulation using two voltage-dependent resistors can be considered. In this method, the read operation is performed assuming that either 1 or 0 is stored in the resistance change memory element. According to such a method, it can be predicted that the reading operation can be verified relatively accurately.

In addition, when writing a circuit using a resistance change memory element, it is impossible to confirm in detail by simulation results that a specific voltage is applied to the resistance used as the resistance change memory element for a specific time. Absent.
IGBaek et al., "Highly scalable non-volatile resistive memory using simple binary oxide driven by asymmetric unipolar voltage pulses", Tech. Digest IEDM 2004, p. 587

However, in the above simulation method, it takes a lot of work to perform the simulation and the work including confirmation of the result.
For example, in the case of performing a simulation including a read operation from a resistance change memory element that has been written after writing to the resistance change memory element, there are a large number of combination patterns of writing and reading, and all patterns Every simulation has to be done and labor is required.

  As described above, in the above simulation method, it is practically impossible to verify an operation in which writing and reading are repeatedly performed on the resistance change memory element while changing the resistance value of the resistance change memory element.

The present invention has been made in view of the above points, and can easily reproduce the characteristics of the resistance change memory element determined by the manufacturing conditions and the like, and can perform reading and writing with respect to the storage unit including the resistance change memory element. and to provide a simulation equipment which can be easily performed operation was.

To solve the above SL problems, the simulation apparatus is provided for performing operation verification of the resistance change memory device. The simulation apparatus includes: a first power supply node held at a first potential; a first resistor connected to the first power supply node; and the first resistor connected in series via a second resistor. A second power supply node connected and held at a second potential; a storage node located between the first resistor and the second resistor; the storage node and the second power supply node; And a capacitor connected in parallel to the second resistor, and the resistance value of the first resistor and the resistance value of the second resistor are applied to a variable resistance unit provided in the simulation device. By changing the voltage according to the voltage, the potential of the storage node is controlled to the potential of either the first power supply node or the second power supply node.

According to simulation equipment, storage nodes in the sub-circuit that represents the storing unit indicating the storage state is provided, a sub-circuit that represents the storage unit to the operation according to the state of the variable resistor. Thereby, the state after the operation of the sub-circuit representing the storage unit is maintained, and based on the state, the sub-circuit representing the storage unit can continuously perform the following operations.

As a result, analog simulation of writing and reading of the storage device using the storage unit including the resistance change memory element can be continuously performed. Therefore, the resistance change memory element including the storage unit described above can easily perform simulation of the memory circuit. it is possible to realize a simulation equipment.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
(First embodiment)
First, a simulation apparatus, a simulation method, and a resistance change memory circuit design support method using the simulation method according to the first embodiment will be described with reference to FIGS.

First, the basic configuration of the circuit configuration of the resistance change memory element will be described.
FIG. 1 is a circuit diagram showing the contents of a sub-circuit corresponding to a resistance change memory element.
The circuit shown in this figure includes a variable resistance unit 10, a delay potential generation unit 30, and a storage unit 20. In this circuit, the state of the resistance change memory element, that is, information on the high resistance state or the low resistance state is represented by a storage node rin of the storage unit 20.

  The variable resistance unit 10 includes a high resistance element R11, a low resistance element R12, a resistance element R13, a resistance element R14, a node bl, and a node gl, and the high resistance element R11 and the resistance between the node bl and the node gl. The element R13 is connected in series. A low resistance element R12 and a resistance element R14 are connected in series between the node bl and the node gl.

The high resistance element R11 represents a characteristic of the resistance change memory element in a high resistance state, and is a voltage dependent resistance whose resistance value changes depending on a voltage applied to itself.
The low resistance element R12 is an element representing the characteristics of the resistance change memory element in the low resistance state. The low resistance element R12 may be a voltage-dependent resistor whose resistance value changes depending on the voltage applied to itself, or may be a constant resistance whose resistance value does not change depending on the voltage applied to itself. In the case of a constant resistance, for example, 4 kΩ is suitable for the low resistance element R12.

  On the other hand, the storage unit 20 includes a high-potential power supply node vddr, a low-potential power supply node vssr, a storage node rin, a resetter switch, a resistance element R21 that functions as a resetter load resistance element, a resistance element R23 that functions as a setter switch, and a capacitor C24. The resistor element R21 and the resistor element R23 are connected in series between the high potential power supply node vddr and the low potential power supply node vssr. A capacitor C24 is connected between the storage node rin and the low potential power supply node vssr.

Here, the resistance element R21 and the resistance element R23 are voltage-dependent resistances that depend on the voltage between the two nodes bl-gl.
Also, the resistance element R21 has a resistance value that is somewhat low when the voltage between the two nodes bl and the node gl is not less than the reset voltage and not more than the set voltage, and in other cases, the resistance element R21 has a very high resistance ( Open state).

The potential of the storage node rin changes by changing the resistance values of the resistance element R21 and the resistance element R23.
The delay potential generator 30 includes a delay element 31, a node dtmo, and a low potential power supply node vssr. The delay element 31 is an element for preventing a reset from easily occurring after setting. The delay element 31 copies the voltage between the two nodes bl-gl to the potential of the node dtmo with a somewhat short delay.

The sub circuit will be described with reference to another drawing in order to easily understand the operation.
FIG. 2 is a circuit diagram corresponding to a resistance change memory element. FIG. 2 illustrates the contents of the subcircuit corresponding to the resistance change memory element shown in FIG. 1 more specifically, and shows the basic principle of the simulation apparatus of the first embodiment. In this figure, in order to easily understand the basic principle of the simulation apparatus, a resistive element having a switching function is directly represented as a switching element.

The circuit shown in FIG. 2 represents a basic configuration of the resistance change memory element, and the resistance change memory element includes a variable resistance unit 10 and a storage unit 20.
And this memory | storage part 20 has a function to hold | maintain memory | storage and to change a state and memory content according to information, such as a voltage applied to the variable resistance part 10. FIG. Further, the variable resistance unit 10 has a function of changing the resistance value between the two nodes bl and the node gl according to the potential of the storage node rin of the storage unit 20.

  Accordingly, the storage unit 20 is controlled by the variable resistance unit 10, and the variable resistance unit 10 is controlled by the storage unit 20. A feature is that information indicating whether the resistance change memory element is in a high resistance state or a low resistance state is represented by a storage node rin of the storage unit 20. In other words, whether the variable resistance unit 10 is in the high resistance state or the low resistance state is controlled by the potential of the storage node rin.

Next, members constituting the circuit of the storage unit 20 and the variable resistance unit 10 will be described.
The storage unit 20 includes a high-potential power supply node vddr, a low-potential power supply node vssr, a storage node rin, a resetter switch SW21, a resetter load resistance element R22, a setter switch SW23, and a capacitor C24 having a fixed capacity for storing data. is doing. The high potential power supply node vddr, the resetter switch SW21, the resetter load resistance element R22, the setter switch SW23, and the low potential power supply node vssr are connected in series.

  The setter switch SW23 becomes conductive when the set voltage condition is satisfied. On the other hand, the resetter switch SW21 conducts when the reset condition is satisfied. Whether or not the condition is satisfied is determined by a voltage applied between the two nodes bl and the node gl of the variable resistance unit 10. As described above, the storage unit 20 is controlled by the variable resistance unit 10.

  Here, that the voltage condition of the set is satisfied means, for example, a case where the voltage between the two nodes bl-gl is equal to or higher than the set voltage. When the set condition is satisfied, the setter switch SW23 becomes conductive, and the potential of the storage node rin becomes the same as that of the low potential power supply node vssr.

  The condition that the reset voltage condition is satisfied means, for example, a case where the voltage between the two nodes bl and gl is not less than the reset voltage and not more than the set voltage. When the reset condition is satisfied, the resetter switch SW21 is turned on, and the potential of the storage node rin rises to the potential of the high potential power supply node vddr.

  However, immediately after the resetter switch SW21 is turned on, the potential of the storage node rin does not immediately become the same as the potential of the high potential power supply node vddr. This is because the resetter load resistance element R22 and the capacitor C24 exist in the storage unit 20. In this case, the potential change of the storage node rin is determined by the time constants of the resetter load resistance element R22 and the capacitor C24 (described later).

  Here, the time constant is a product of the resistance value of the resetter load resistance element R22 and the capacitance of the capacitor C24. Therefore, by adjusting the resetter load resistance element R22 and the capacitor C24, the time constant changes and the time required for resetting can be adjusted.

  As described above, in the case of the unipolar resistance change memory element, the time required for the set to shift from the high resistance state to the low resistance state is short, and the time required for the reset to shift from the low resistance state to the high resistance state is long. Therefore, in order to make the circuit similar to that of an actual unipolar resistance change memory element, in the circuit shown in FIG. 2, the storage unit 20 is provided in addition to the variable resistor unit 10, and the time required for resetting is instantaneous and the time required for resetting. Only the RC product is used to adjust the switching between the low resistance state and the high resistance state.

  When neither the set condition nor the reset condition is satisfied, neither the setter switch SW23 nor the resetter switch SW21 is conducted. In this case, it is assumed that a predetermined potential is held by the capacitor C24.

  Next, the variable resistance unit 10 includes a high resistance element R11 representing a resistance change memory element in a high resistance state, a low resistance element R12 representing a resistance change memory element in a low resistance state, a switch SW13 for selecting a high resistance state, a low resistance The switch SW14 for selecting the state is included.

  One of the switches SW13 and SW14 is always turned on according to the potential of the storage node rin of the storage unit 20. Thus, the variable resistance unit 10 is controlled by the storage unit 20.

Here, in the control for selecting either the switch SW13 or the switch SW14 according to the potential of the storage node rin, for example, a certain reference potential _Vth is provided for the potential of the storage node rin, and the potential of the storage node rin is set to the reference potential. Control is performed such that the resistance between the node bl and the node gl is high when it is higher than _{Vth, and} the resistance between the node bl and the node gl is low when the potential of the storage node rin is lower than the reference potential _Vth. .

Specifically, when the potential of the storage node rin is higher than the reference potential V _th is caused to conduct the switch SW13, carried out by conducting the switch SW14 when the potential of the storage node rin is lower than the reference potential V _th.

When the potential of the storage node rin is higher than the reference potential V _th by the control method as described above, the resistance between the two nodes bl-node gl is increased by sufficiently reducing the resistance value of the switch SW13 itself. When only the high-resistance element R11 representing the resistance change memory element in the resistance state is present alone and the potential of the storage node rin is lower than the reference potential _Vth , the resistance between the two nodes bl-gl is By sufficiently reducing the resistance value of the switch SW14 itself, only the low resistance element R12 representing the resistance change memory element in the low resistance state is present alone.

At the same time, it is possible to determine whether the resistance between the two nodes bl-gl is in a high resistance state or a low resistance state by looking at the potential of the storage node rin.
Note that the ground line in the strict sense is not the node gl shown in FIG. 2 but a GND node below the selection transistor 44 shown in FIG. 11 to be described later, but is indicated as gl in FIG. The node is called gl indicating the ground line.

Moreover, the structure of the variable resistance part 10 and the memory | storage part 20 shown in FIG. 2 is an example, and the component showing a resistance change memory element other than this can be considered.
However, in the circuit configuration shown in FIG. 2, since the variable resistance unit 10 and the storage unit 20 are mutually controlled, actually, the circuit does not operate normally as a subcircuit of the resistance change memory element for analog simulation. There is a case. This is the case, for example, as follows.

As described above, in the state where the potential of the storage node rin is lower than the reference potential V _th , the resistance between the node bl and the node gl becomes low, and the potential of the storage node rin is higher than the reference potential V _th. The resistance between the node bl and the node gl becomes low.

Here, when the voltage applied between the node bl and the node gl of the variable resistance unit 10 satisfies the set condition, and the potential of the storage node rin is slightly lower than the reference potential _Vth in the storage unit 20, it is immediately variable. The resistance between the node bl and the node gl of the resistance unit 10 is in a low resistance state.

Then, the voltage applied between the two nodes bl-gl decreases, and the voltage between the nodes bl-gl shifts from the set voltage condition to the reset voltage condition.
Then, the potential of the storage node rin immediately reaches the reference potential V _th or more, and resetting occurs.

Then, the voltage applied between the two nodes bl-gl satisfies the set voltage condition, and the potential of the storage node rin shifts below the reference potential _Vth .
Such a repetition causes a phenomenon in which the potential of the storage node rin oscillates with reference to the reference potential _Vth . Due to such vibration, one of the switch SW13 and the switch SW14 is continuously turned on, and the potentials of the node bl and the node gl vibrate violently.

Such a vibration phenomenon is caused by a situation in which the potential of the storage node rin is slightly lower than the reference potential _Vth and the reset is likely to occur immediately after the setting is started.
By the way, when the characteristics of an actual unipolar resistance change memory element are evaluated, it has been found that if a voltage condition necessary for setting is satisfied even in a very short time immediately after a reset occurs, the setting occurs. Further, it is known that even if the voltage condition necessary for reset is satisfied immediately after the set occurs, the reset does not occur immediately. Therefore, it is necessary for the simulation apparatus to have a circuit configuration that does not cause a reset immediately after a set occurs.

  Such a problem of vibration can be solved by determining whether or not the resetter switch SW21 and the setter switch SW23 are turned on by determining a voltage obtained by delaying the voltage between the two nodes bl-gl for a short time.

  That is, the setter switch SW23 is turned on when the voltage signal obtained by delaying the voltage between the two nodes bl-gl is shorter than the set voltage, and the resetter switch SW21 is connected between the two nodes bl-gl. When the voltage signal obtained by delaying the voltage for a short time is not less than the reset voltage and not more than the set voltage, the voltage signal is turned on.

By doing so, the resistance change memory element operates as follows at the time of setting.
As described above, when the delay is not performed, the voltage between the two nodes bl-gl satisfies the set voltage condition, the setter switch SW23 is conductive, and the resetter switch SW21 is insulated ( Open state). In this state, when the potential of the storage node rin changes from a state above the reference potential _Vth to a state below it, the switch SW13 is in an insulated state (open state) and the switch SW14 is in a conductive state. As a result, the resistance value between the two nodes bl-gl shifts from high resistance to low resistance. In this case, the potential of the storage node rin oscillates with reference to the reference potential _Vth .

  However, by providing a circuit capable of delaying the voltage between the two nodes bl-gl for a short time, the voltage signal between the node bl-node gl transmitted from the variable resistance unit 10 to the recording unit 20 is delayed. Delay for hours.

  That is, even if the resistance value between the node bl and the node gl is in a low resistance state and the voltage applied between the node bl and the node gl satisfies the reset voltage condition, the recording unit 20 is variable by the delay time. It is recognized that the resistance unit 10 satisfies the set voltage condition. Therefore, for the delay time, the state where the setter switch SW23 is in a conductive state and the resetter switch SW21 is in an insulating state continues.

As a result, actually, even if the reset voltage condition immediately after the setting is satisfied in the variable resistor section 10, the potential of the storage node rin once falls below the reference potential _Vth and rebounds by the time corresponding to the delay time. Without reaching the same potential as the low potential power supply node vssr. When resetting starts, the potential of the storage node rin does not rebound from a state slightly lower than the reference potential _Vth , but rises from a state of substantially the same potential as the low potential power supply node vssr. Therefore, the time for which the reset voltage condition is satisfied is adjusted by the RC product of the resetter load resistance element R22 and the capacitor C24 in which the potential of the storage node rin rises from the potential of the low potential power supply node vssr to the potential of the high potential power supply node vddr. It will be possible.

Furthermore, it may be necessary to operate the resistance change memory element in the same manner as an actual unipolar resistance change memory element.
It takes into account the resistance of the setter switch SW23 itself and the resistance of the resetter switch SW21 itself, and the time constant represented by the product of the resistance value of the state in which the setter switch SW23 or the resetter switch SW21 is conductive and the capacitor C24, and the delay described above. It is a relationship of time.

Here, the resistance of the setter switches SW23 itself in the case of conduction setter switch SW23 shown in Figure 2 R _23, the resistance value of the resettable load resistance element R22 R ₂₂ Distant, the capacitance value of the capacitor C24 and C _24. The setter switch SW23 has only a switch function and can be considered to have a resistance of 0. However, when expressed in a circuit diagram as shown in FIG. 1 described later, an extremely small resistance is obtained even when the setter switch SW23 is turned on. Have. Therefore, here, it is assumed that the resistance is not 0 even when the setter switch SW23 is turned on.

Then, the time constants in the potential change of the storage node rin at the time of setting and at the time of resetting are set to t ₁ and t ₂ respectively. Further, the delay time described above is assumed to be t ₃ .
It is clear that t ₁ and t ₂ are expressed as t ₁ = R ₂₃ C ₂₄ and t ₂ = R ₂₂ C ₂₄ from FIG. The relationship between t ₁ , t ₂ , and t ₃ needs to be set as t ₁ <t ₃ <t ₂ . In particular, it is desirable that t ₁ << t ₃ << t ₂ be set.

The reason is that by setting t ₁ <t ₃ , the potential of the storage node rin can be made close to the low potential power supply node vssr during the delay time t ₃ immediately after the setting. Further, by setting t ₁ << t ₃ , the potential of the storage node rin can be made substantially equal to the low potential power supply node vssr during the delay time t ₃ immediately after the setting. For example, decrease in the specific calculation, when it is t ₁ = t _3/10, during the delay time t ₃ immediately after the set, until the potential of the storage node rin example, 4.5 × 10 ^-5 (V) Can be made.

Further, by setting t ₃ <t ₂ , it is possible to suppress the influence of the delay time t ₃ at the time of reset. At the time of reset, the delay time t ₃ is delayed as it is. In other words, after the reset voltage condition is satisfied, the resistance value between the two nodes bl and the node gl becomes high after a lapse of time t _{3 and} a time proportional to t ₂ .

However, t ₃ << t ₂ is desirable. This is because, when the time t ₂ is shorter, after a lapse of time is proportional to t _2, until which time the time + t ₃ is proportional to t _2, if it meets the voltage conditions of the set, the set of This is because an unexpected event that the resistance value between the two nodes bl-gl once becomes high resistance and then becomes low resistance is likely to occur while the voltage condition is satisfied.

Next, a method for adjusting the reset time for the resetter switch SW21 to a desired value will be described.
Even if the potential of the storage node rin drops to the potential of the low potential power supply node vssr and the reset voltage condition is satisfied in this state, the resistance value between the two nodes bl-node gl does not immediately become high resistance but is constant. time resistance between only the node bl- node gl if satisfying voltage condition of the reset is set to be a high resistance, RC due to the capacitance value C ₂₄ in the resistance value R ₂₂ and the capacitor C24 of the resettable load resistance element R22 Take advantage of delays.

When the potential of the storage node rin is higher than the reference potential V _th, the resistance value between the two nodes bl-node gl is high, and when the potential of the storage node rin is lower than V _th, between the two nodes bl-node gl Is a low resistance, and the potentials of the high potential power supply node vddr and the low potential power supply node vssr are V _vddr and V _vssr , respectively, the time T ₂ required for resetting is expressed by the following equation.

T ₂ = t ₂ × A + t ₃ (1)
However, t ₂ = R ₂₂ × C ₂₄ (2)
A = ln ((V _vddr −V _vssr ) / (V _th −V _vssr )) (3)
Here, what over factor A to t _2, the potential of the storage node rin during the time required for t ₂ reaches the reference potential V _th from the low potential power supply node VSSR, is reset at a time shorter than t ₂ Because it happens. However, the time required for resetting can be freely adjusted by adjusting the resistance value R _{22 of} the resetter load resistance element R ₂₂ and the capacitance value C ₂₄ of the capacitor C ₂₄ .

  Next, with the configuration of the variable resistance element shown in FIG. 2, the reset voltage condition is satisfied, the voltage applied between the two nodes bl-node gl becomes equal to or lower than the reset voltage, and the reset voltage condition is not satisfied. A description will be given of how the storage node rin operates when the voltage condition is satisfied.

FIG. 3 is a diagram for explaining a change in the potential of the storage node rin when resetting. The horizontal axis represents time (ns), and the vertical axis represents the potential (V) of the storage node rin. This figure shows specific values to be described later, for example, t ₂ = 100 ns, t ₃ = 1 ns, V _vddr = 1.0 V,
V _vssr = _0.0 V, V _th = 0.5 V, T ₂ = 70.3 ns.

  Here, the period A and the period C in the figure are periods in which the reset voltage condition is satisfied. On the other hand, the period B is a period in which neither the reset voltage condition nor the set voltage condition is satisfied, that is, a period in which the voltage between the two nodes bl-node gl is equal to or lower than the reset voltage.

In the period A and the period C, the potential V _rin of the storage node rin changes with the time constant t ₂ .
Then, the potential of the storage node rin in the period A is expressed by the following equation.
V _rin (t) = V _vssr + (V _vddr −V _vssr ) (1−exp (− (t−t ₃ ) / t ₂ )
) …… (4)
The period B is a period in which the potential is held by the function of the capacitor C24. When the length of the period B is T ₄ , the potential V _rin of the storage node rin in the period C is expressed by the following equation.

V _rin (t) = V _vssr + (V _vddr −V _vssr ) (1−exp (− (t− (T ₄ + t ₃ )
) / T ₂ )) …… (5)
In the configuration shown in FIGS. 2 and 3, the accumulated time is applied as the time required for resetting unless the voltage condition of the set is satisfied. In other words, as long as they do not satisfy the voltage condition of the set, reset occurs when the total time period that meets the voltage condition of the reset reaches T _2, the resistance value between the two nodes bl- node gl becomes a high-resistance . In FIG. 3, if the lengths of period A and period C are T _2A and T _2B , respectively, T _2A + T _2B = T ₂ . That is, the potential of the storage node rin be in a low-potential power supply node VSSR, resistance between node bl- nodes gl through time T ₂ is shifted to the high-resistance from a low resistance. In this case, T ₄ is not considered and T ₄ = 0.

  This completes the description of the basic configuration and operation of the resistance change memory element of the present invention. Furthermore, in order to deepen the understanding of the present invention, description will be made using specific numerical values. However, the numerical values used below are merely examples for deepening understanding, and the scope of claims of the present invention is not limited to the numerical values used below.

  By the way, an actual resistance change memory element has a high resistance value when the voltage applied to itself is near 0 V in a high resistance state, and the resistance varies greatly depending on the voltage applied to itself, and is applied to itself. When the voltage is a relatively high voltage near the set voltage, the resistance value becomes low. On the other hand, in the low resistance state of the actual resistance change memory element, the resistance value does not change relatively depending on the voltage applied to itself. Therefore, the resistance value of the high-resistance element R11 representing the resistance-change memory element in the high-resistance state shown in FIG. 2 changes depending on the voltage applied between the two nodes bl-gl, for example, as shown in FIG. To be characteristic. FIG. 4 is a diagram illustrating an example of an IV curve of a high resistance element. Further, the low resistance element R12 representing the resistance change memory element in the low resistance state may be a constant resistance whose resistance value does not change depending on a voltage applied between the two nodes bl-node gl, and may be two nodes bl-node. It is good also as a voltage dependence resistance from which resistance value changes with the voltage applied between gl. In the case of a constant resistance, for example, 4 kΩ is set.

The potential of the high potential power supply node vddr shown in FIG. 2 is always 1.0 V, the potential of the low potential power supply node vssr is always 0.0 V, the resistance value of the resetter load resistance element R22 is 100Ω, and the capacitance value of the capacitor C24 is 1 nF. And The resistance value between the two nodes bl-gl is high when the potential of the storage node rin is higher than 0.5V, and low when the potential of the storage node rin is lower than 0.5V. In terms of the symbols used so far, C ₂₄ = 1 nF, R ₂₂ = 100Ω, t ₂ = 100 ns, t ₃ = 1 ns, V _vddr = 1.0 V, V _vssr = _0.0 V, V _th = 0.5 V It is.

Under this condition, T ₂ = 70.3 ns. However, the change in the potential of the storage node rin is not particularly limited to the above numerical value and the following example shown below, and the theory and description in the present embodiment are based on the above numerical value and the following example. Not only applicable.

Then, Expression 4 and Expression 5 become Expression 6 and Expression 7 below, respectively. However, the t _2, do not assign a numerical value.
V _rin (t) = 1−exp (− (t−t ₃ ) / t ₂ ) ≈1−exp (−t / t ₂ ) (6)
V _rin (t) = 1−exp (− (t− (T ₄ + t ₃ )) / t ₂ ) ≈1−exp (− (t−T ₄ ) / t ₂ ) (7)
The setting will be described in more detail. The time required for the setting varies depending on the potential of the storage node rin immediately before the voltage condition of the set is satisfied. However, the time required for the setting is extremely short, and can be regarded as an instant regardless of the potential of the storage node rin immediately before the voltage condition of the set is satisfied. The potential of the storage node rin immediately before the voltage condition of the set is satisfied is a problem. do not become.

Now that the description of the configuration and operation of FIG. 2 has been completed, more specific arrangement and connection of circuit elements on the simulator will be described. In an analog simulator such as HSPICE, the switches used in FIG. 2 are preferably voltage-dependent resistors. In HSPICE, a voltage-dependent resistor is described as an element whose resistance value changes depending on a voltage with a sign between two specific points. Here, the voltage with a sign between two specific points is represented by “V _DB −V _DA ” when the potential at any two points is V _DA and V _DB . Hereinafter, the potential V _vssr of the low voltage power supply node vssr is _0.0 V, and the “potential of the storage node rin” is “the voltage between the storage node rin and the low voltage power supply node vssr”, or “the potential of the storage node rin. Will be described as the same as “subtracting the potential of the low voltage power supply node vssr”. However, the scope of claims of this patent is not limited to the case of V _vssr = _0.0V .

  FIG. 5 is a diagram for explaining the roles and functions of the elements constituting the resistance change memory element. The description example shown in FIG. 5 shows an example of how the names of circuit elements are set in a netlist description of an analog simulator such as HSPICE described later.

  Now that the description of the operation of the subcircuit has been completed, returning to FIG. 1 again, the operation of the subcircuit used in the simulation apparatus will be described in correspondence with the basic principle shown in FIG.

  As described above, the high resistance element R11 of the variable resistance unit 10 represents the characteristics of the resistance change memory element in the high resistance state, and is a voltage dependent resistance whose resistance value changes depending on the voltage applied to itself. For example, the high resistance element R11 has characteristics as shown in FIG.

  The low resistance element R12 is an element representing the characteristics of the resistance change memory element in the low resistance state. The low resistance element R12 may be a constant resistance whose resistance value does not change depending on the voltage applied to itself, or may be a voltage-dependent resistor whose resistance value changes depending on the voltage applied to itself. For the low resistance element R12, for example, 4 kΩ is suitable in the case of a constant resistance.

  The read characteristics of the resistance change memory element in the high resistance state and the low resistance state can be freely adjusted by adjusting the characteristics of the high resistance element R11 and the low resistance element R12. The high resistance element R11 and the low resistance element R12 can be substituted by using a voltage dependent current source.

The resistance element R13 that selects the high resistance state and the resistance element R14 that selects the low resistance state between the node bl and the node gl are resistances that depend on the potential of the storage node rin.
The resistance element R13 functions as a switch, and has a very low resistance (conducting state) when the potential of the storage node rin is high, and has a very high resistance (open state) when the potential of the storage node rin is low.

  The resistance element R14 functions as a switch, and has a very low resistance (conducting state) when the potential of the storage node rin is low, and has a very high resistance (open state) when the potential of the storage node rin is high.

For example, 0.5 V is suitable for the potential V _th of the storage node rin that serves as a reference for determining whether the resistance element R13 and the resistance element R14 have a very high resistance or a very low resistance.
For the stable operation of the simulation, it is preferable that both the resistance element R13 and the resistance element R14 have no potential at the storage node rin that is in a very high resistance state (open state).

As one method for avoiding both the resistance element R13 and the resistance element R14 from being in a very high resistance state (open state) when the potential of the storage node rin is just V _th , the resistance element R13 Has a very low resistance (conductive state) when the potential of the storage node rin is 0.4999 V or higher, and the resistance element R14 has a very low resistance (conductive state) when the potential of the storage node rin is 0.5001 V or lower. To do so.

When the resistance values of the resistance element R13 and the resistance element R14 themselves in a conductive state are sufficiently low, when the potential of the storage node rin is higher than the standard potential V _th , the resistance between the node bl and the node gl illustrated in FIG. Only the resistance element R11 exists alone, and when the potential of the storage node rin is lower than the standard potential _Vth, only the low resistance element R12 exists alone.

  In order to make the difference between the read element and the actual element negligibly small, the resistance values of the resistance element R13 and the resistance element R14 in a very low resistance state (conductive state) are the resistance values of the high resistance element R11 and the low resistance element R12. The resistance value is very small compared to the resistance value, which is at least an order of magnitude smaller. The resistance values of the resistance element R13 and the resistance element R14 in the very high resistance state (open state) are the resistance values of the high resistance element R11 and the low resistance element R12. It may be very large compared to the value, and may be at least one digit larger.

  For example, 1 mΩ is suitable for the resistance value of the resistance element R13 and the resistance element R14 in a very low resistance state (conduction state), and the resistance value of the resistance element R13 and the resistance element R14 in a very high resistance state (open state) is For example, 1 TΩ is suitable. More specifically, for example, the resistance element R13 becomes 1 mΩ when the potential of the storage node rin is 0.4999 V or more, and becomes 1 TΩ when the potential of the storage node rin is 0.4999 V or less. The resistance element R14 becomes 1 mΩ when the potential of the storage node rin is 0.5001 V or lower, and becomes 1 TΩ when the potential of the storage node rin is 0.5001 V or higher.

As described above, the delay element 31 of the delay potential generator 30 is an element for preventing a reset from being easily caused after setting. The delay element 31 copies the voltage between the two nodes bl-gl to the potential of the node dtmo with a somewhat short delay t ₃ .

  Here, copying to the potential of the node dtmo means copying to the voltage between the node dtmo and the low potential power supply node vssr. “The potential of the node dtmo”, “the voltage between the node dtmo and the low-potential power supply node vssr”, and “the potential of the node dtmo minus the potential of the low-potential power supply node vssr” are synonymous.

For example, 1 ns is suitable as the delay time t ₃ . Since the delay element exists in HSPICE, it may be used as it is. The delay element is described as follows.
For example, “E31 dtmo vssr VCVS DELAY bl-gl TD = 1 ns” is described.

This means that a delay of 1 ns is given and the voltage between the node bl and the node gl is copied to the voltage between the node dtmo and the low potential power supply node vssr.
Further, the resistance element R21 and the resistance element R23 of the storage unit 20 are variable resistances as described above. Note that the resetter load resistance element R22 shown in FIG. 2 is included in the resistance element R21 in FIG.

The resistance element R21 and the resistance element R23 are voltage-dependent resistances that depend on the potential of the node dtmo. Further, the resistance element R21 and the resistance element R23 do not depend directly on the voltage between the two nodes bl-node gl, but depend on the potential of the node dtmo, whereby the voltage between the two nodes bl-node gl Depends on the voltage delayed by the delay time t ₃ .

Resistive element R21, the resistance value becomes a certain low value R ₂₂ when the potential of the node dtmo is equal to or less than the reset voltage higher than the set voltage, otherwise, would be very high resistance (open state). The resistance element R23 has a low resistance (resistance value R ₂₃ ) when the potential of the node dtmo becomes equal to or higher than the set voltage, and in other cases, the resistance element R23 has a very high resistance (open state).

Resistance R ₂₂ of the low resistance state of the resistance element R21 (conductive state), for example 100Ω are suitable. Resistance R ₂₃ of the low resistance state of the resistance element R23 (conductive state), for example, 1 M.OMEGA is suitable.
For example, 10 ¹⁸ Ω is suitable for the resistance value of the resistance element R21 in a very high resistance state (open state). For example, the set voltage and the reset voltage can be 1.6 V and 0.75 V, respectively. Needless to say, the set voltage and the reset voltage can be freely adjusted.

More specifically, for example, the resistance value of the resistance element R21 is 100Ω when the potential of the node dtmo is 0.75 V or more and 1.6 V or less, and otherwise, the resistance value is 10 ¹⁸ Ω. The resistance element R23 becomes 1 mΩ when the potential of the node dtmo becomes 1.6 V or higher, and can be 10 ¹⁸ Ω in other cases.

The capacitor C24 is a capacitive element having a certain capacity for storing and giving a delay. The capacitor C24 has a function of holding the potential of the storage node rin when both the resistance element R21 and the resistance element R23 have very high resistance values (open state). The product t ₂ of the resistance value R _{22 in} the low resistance state (conduction state) of the resistance element R 21 and the capacitance value C ₂₄ of the capacitor C ₂₄ determines the reset time. Capacitance C ₂₄ of the capacitor C24 are suitable, for example 1nF.

In the above description, t ₁ = R ₂₃ C ₂₄ and t ₂ = R ₂₂ C ₂₄ are expressed, but in the example given here, t ₁ = 1 ps, t ₂ = 100 ns, and t ₃ = 1 ns. Therefore, it can be seen that the relationship of t ₁ << t ₃ << t ₂ is satisfied. The potential of the high potential power supply node vddr is V _vddr = 1.0 V, and the potential of the low potential power supply node vssr is V _vssr = _0.0 V as described above. At this time, according to the equations (1) to (3), the time required for reset is T ₂ = 70.3 ns. On the other hand, the time required for setting is approximately 1 ns, which is determined approximately by the delay time t ₃ at which the delay element 31 functions.

  The delay potential generator 30 may not use a delay element given in advance by HSPICE. The delay function can also be produced using RC delay due to resistance and capacitance. Here, the resistance and capacity of the delay potential generating unit 30 are different from the resistance and capacity in the storage unit 20. FIG. 6 shows an example in which the delay function components are made using RC delay.

  FIG. 6 is a diagram for explaining the basic configuration of the delay potential generator. As shown in this figure, the delay potential generator 30 includes a voltage-dependent voltage source 32, a resistance element R33 having a constant resistance value, and a capacitor C34 having a constant capacitance.

  The voltage dependent voltage source 32 copies the voltage between the node bl and the node gl to the voltage at both ends of the voltage dependent voltage source 32 as it is. As a result, the potential of the node 35 is copied to the node dtmo shown in FIG. 6 with a delay time substantially in the same order as the product of the resistance value of the resistance element R33 and the capacitance value of the capacitor C34.

  Further, in the circuit shown in FIG. 1, a capacitor C15 may be further inserted in parallel with the variable resistance unit 10. FIG. 7 is a diagram for explaining the basic configuration of the variable resistance portion in which a capacitor is inserted. Since an actual resistance change memory element has a structure in which a substance having a relatively high resistance value is inserted between parallel plates made of two conductors, a capacitance component exists between the parallel plates. The capacitor C15 reproduces the capacitance component between the parallel plates. The presence of the capacitor C15 does not change the essential operation of the circuit shown in FIG.

Next, an outline of a resistance change memory circuit design support method using the simulation apparatus and the simulation method will be described.
FIG. 8 is a flowchart for explaining a method for supporting the design of the resistance change memory circuit. As shown in the figure, the method for supporting the design of the resistance change memory circuit includes a resistance change memory circuit simulation (step S1), operation verification (step S2), and a netlist change or element attribute change (step S3) support step. have.

  Here, the step of supporting the resistance change memory circuit simulation (step S1) uses the library 100, the subcircuit 101 representing the storage unit, the netlist 102, and the initial setting voltage 103, and the voltage of the node included in the memory circuit. This is a step of simulating the time change of.

  The support step of the operation verification (step S2) is a step of supporting the verification of the operation of the resistance change memory circuit from the expected voltage 104 and the simulation result obtained by the simulation of the resistance change memory circuit (step S1). is there.

  In the support step of changing the net list or changing the element attribute (step S3), if there is a malfunction in the operation of the resistance change memory circuit in the support step of the operation verification (step S2), the change of the net list or the element attribute is changed. This is a support step for making changes.

  FIG. 9 is a flowchart for explaining the simulation steps of the resistance change memory circuit in more detail. As shown in the figure, the resistance change memory circuit simulation (step S1) includes reading of component attributes from the library 100 (step S10), reading of a net list (step S11), and reading of a subcircuit representing a storage unit. (Step S12), reading of the initial setting voltage (Step S13), time analysis simulation of the node voltage (Step S14), and creation of a time dependency table of the node voltage (Step S15).

  Here, the step of reading the component attribute (step S10) is a step of inputting a component attribute shown in FIG.

The step of reading the net list (step S11) is a step of causing the simulation apparatus to read, that is, inputting the net list shown in FIG.
The step of reading the subcircuit (step S12) is a step of causing the simulation apparatus to read, that is, inputting the subcircuit of the storage unit shown in FIGS.

  The step of reading the initial setting voltage (step S13) is a step of causing the simulation apparatus to read, that is, inputting an initial setting voltage table shown in FIG.

  Next, FIG. 10 is a diagram illustrating elements and element attributes. In this figure, for example, transistor A, which is an element, its attribute A and transistor B, its attribute B, capacitor A and its attribute M, resistor A and its attribute X are shown.

FIG. 11 is a diagram illustrating an example of a circuit represented by the net list. FIG. 12 shows a list of netlists.
The circuit shown in FIG. 11 is a list showing components, that is, connection relations of elements and connection nodes. Specifically, the multi-function pMOS 40, the column switches nMOS 41a to 41p, the column switches pMOS 42a to 42p, the resistance change memory element 43, the selection transistor 44, the amplification inverters 45 and 46, the precharge control transistors 47 and 48, A bit line parasitic capacitance 49 is used. Each element is connected by nodes 50, 51, 52, 53 and 54.

  Further, a node 50 is provided between the multi-function pMOS 40, nMOS 41a to 41p and pMOS 42a to 42p, a node 51 between the nMOS 41a to 41p, pMOS 42a to 42p and the resistance change memory element 43, and a resistance change memory element 43 and the selection transistor 44. Have a node 52. Furthermore, the gate of the multi-function pMOS 40 is the node XWE, the gates of the nMOSs 41a to 41p are the node CL1, the gates of the pMOSs 42a to 42p are the node CPL1, the gate of the selection transistor 44 is the node WL, and the gates of the precharge control transistors 47 and 48 are the nodes PRC. Have

  Here, the MN 40 shown in FIG. 12 corresponds to the multi-function pMOS 40, the MNs 41a to MN41p correspond to the nMOSs 41a to 41p of the column switches, the MP42a to MN42p correspond to the pMOSs 42a to 42p of the column switches, and the subcircuit 43 Corresponds to the resistance change memory element 43, MN44 corresponds to the selection transistor 44, subcircuits 45 and 46 correspond to the amplification inverters 45 and 46, and MN47 and MN48 correspond to the precharge control transistors 47 and 48, respectively. Correspondingly, C49 corresponds to the bit line parasitic capacitance 49.

  The parentheses such as MN40 indicating a MOS transistor indicate a drain terminal, a gate terminal, a source terminal, and a terminal connected to the substrate in this order. The attribute of the MOS transistor is shown on the right side of the parenthesis. For example, N, L, and W indicate the conductivity type, channel length (gate electrode width), and channel width in this order.

  As described above, the circuit shown in FIG. 11 is a 1T1R type resistance change memory in which a memory cell includes one selection transistor 44 and one resistance change memory element 43. The circuit shown in FIG. 11 includes circuits necessary for writing and reading in addition to the memory cell.

  The circuit shown in FIG. 1 exhibits electrical characteristics very close to those of an actual resistance change memory element based on the operation principle as described above. The subcircuit shown in FIG. 1 is incorporated in the resistance change memory element 43 of the circuit shown in FIG. 11, so that the circuit shown in FIG. 11 operates very close to the circuit including the actual resistance change memory element. . Therefore, if the netlist is correctly described and the parameters of the netlist incorporated as the resistance change memory element 43 are correct, the operation equivalent to that of a semiconductor chip or semiconductor macro manufactured or prototyped as a product or CTEG is reproduced on the simulation apparatus. Is possible. As a result, the design of the circuit including the resistance change memory element can be supported and made efficient by the method as shown in FIGS.

Next, a circuit design support method using the net list will be described.
FIG. 13 is a diagram illustrating an example of initial setting values input to the analog simulator. FIG. 13 shows node names and initial values.

  A node refers to a connection point between elements, a connection point between subcircuits and elements, or a connection point between subcircuits and subcircuits. The node is designated by, for example, InvA · node (a) when designating the node of the circuit A composed of node inverters.

The initial value is the initial voltage of each node. When the initial value is specified for a node name, for example, InvA · node (a), InvA · node (a), 1.0V is specified.
FIG. 14 is a diagram showing a time dependence table created by the analog simulator. This time dependency table shows the node, the initial value, and the voltage of the node at each time.

  The node is a column in which all nodes in the circuit to be simulated are described. The initial value is a column in which an initial value is described for a node to which an initial setting value is given. The time is a column in which a time at which a result is desired to be obtained by simulation is described. The voltage of each node is a column in which the voltage at each time of each node obtained by simulation is described.

  In the analog simulator, after the simulation, a table of voltage values of each node with respect to each time obtained by the simulation is created. Therefore, the analog simulator creates a time-dependent table shown in FIG. 14 by combining the initial set values initially set for each node and the voltage value table for each node obtained by simulation.

  FIG. 15 is a flowchart showing details of the operation verification support step. This figure shows a flowchart showing details of the operation verification (step S2) shown in FIG. Then, the flowchart of FIG. 15 is obtained by simulation at the node and time at which the expected value is set (step S2a), the expected value is read (step S2b), the node at which the expected value is set, as the operation verification. The node voltage and the expected voltage are compared (step S2c), and it is determined whether the node voltage and the expected voltage match at the designated time (step S2d).

  Here, the step of reading the time dependency table of the voltage of the node is a step of reading the time table. The step of reading the expected value is a step of reading the expected value table. The step of comparing the node voltage obtained by the simulation and the expected voltage is a step of comparing the node voltage obtained by the simulation and the expected voltage at the time when the expected value is set, and outputting the comparison result. The step of determining whether or not the node voltage matches the expected voltage is a step of supporting operation verification of the circuit that performed the simulation based on the comparison result.

  If the result of the operation check is satisfactory, the support for designing the resistance change memory circuit ends. On the other hand, as a result of checking the operation, if there is a voltage at a node that does not match the expected value, the process proceeds to a circuit change and element attribute change support step, which will be described in detail later.

FIG. 16 is a diagram showing an expected value table. The expected value table is represented by nodes, expected values, and times.
The node is a column in which a list of nodes for which expected values are set is described. The expected value is a column in which the expected value of the voltage for each node is described. The time is a column that describes the time at which the expected value is set.

  FIG. 17 is a diagram showing a comparison table between expected values and node voltages obtained by simulation. The comparison table includes a node name, an expected value, a simulation value, a time, and a comparison result.

  The node name is a column in which a node for comparing the expected value with the voltage is described. The expected value is a column in which the expected value for the node described in the node is described. The simulation value is for a node described in the node, and is a column in which a voltage obtained by simulation corresponding to the time described in the time column is described. The time is a column in which the time at which the expected value and the node voltage are compared is described. The comparison result is a column in which the result of comparing the expected value and the voltage of the node obtained by the simulation is described.

  For example, with respect to the node described in the node “InvA node (a)”, when the expected value described in the expected value is> 0.9 V and the voltage of the node described in the simulation value is 1.0 V In the comparison result, “Yes” is described, which indicates that the expected value matches the node voltage.

  On the other hand, for the node “InvA node (b)” described in the node, the expected value described in the expected value column is> 0.9 V, and the voltage of the node described in the simulation value is 0.5 V. In some cases, the comparison result is described as “No”, indicating that the expected value does not match the node voltage. Then, when all the description results described in the comparison result are “Yes”, it is determined that the expected value and the node voltage match.

  Thus, in the support step of the operation verification (step S2) shown in FIG. 8, the expected value is compared with the node voltage obtained by the simulation, and when all the expected values match the node voltage, the expected value is obtained. It is determined that the value matches the node voltage. When the expected value matches the node voltage, the design support for the memory circuit including the resistance change memory element is terminated. On the other hand, when the expected value and the node voltage do not match, the process proceeds to a circuit change or element attribute change support step to further support the design of the memory circuit including the resistance change memory element.

  FIG. 18 is a flowchart showing details of the support step for circuit change or element attribute change. The circuit change or element attribute change support step determines whether or not the element attribute needs to be changed (step S3a). If the element attribute needs to be changed, the element attribute is changed (step S3b). Then, it is determined whether the netlist needs to be changed (step S3c). If the netlist needs to be changed, the netlist is changed (step S3d).

  In the step of determining whether the element attribute needs to be changed, the reason why the expected value and the node voltage do not match is the problem of the signal delay estimation error due to the wrong load estimation, etc. This is a step of determining whether or not the element attribute needs to be changed. The element attribute change support step considers what element attributes should be used when it is determined that the element attribute needs to be changed, and supports the element attribute change to match the element attribute. It is a step to do. In the step of determining whether the netlist needs to be changed, examine whether the reason why the expected value and the node voltage did not match is due to a logic error, etc., and determine whether the netlist needs to be changed. It is a step to do. The netlist change support step is a step of supporting the netlist change when it is determined that the netlist needs to be changed.

  Thus, in the simulation method described above, one of the connection nodes (for example, the storage node rin) that connects the circuit components that constitute the subcircuit is a storage node that holds a voltage corresponding to the storage state of the storage unit. Between the circuit components that make up the storage device, input the netlist that describes the connections between the circuit components that make up the storage device into the analog simulator, perform analog simulation The time change of the voltage of the connection node is obtained.

  Furthermore, the expected value of the voltage of the connection node between the circuit components constituting the storage device is input, and the voltage of the connection node between the circuit components constituting the storage device obtained by the analog simulator and the circuit component constituting the storage device Are compared with each other, the comparison result is output, and it is determined from the comparison result whether or not the operation of the storage device is operating normally.

  The actual simulation result will be described with a more specific example. The example given below does not necessarily correspond to the example of the circuit design support method shown in FIG. 8 to FIG. 18, but shows an example of the simulation result.

  In the example given below, specific potential signals are given to the gate nodes XWE, CL1, CPL1, WL, and PRC of each transistor in the circuit including the resistance change memory element 43 shown in FIG. Reading is performed after writing, a reading result as written is obtained, and it is confirmed whether or not the potential of each node is as intended. The resistance change memory element 43 shown in FIG. 11 uses the subcircuit shown in FIG. The simulation results given below are the results obtained by actually simulating with HSPICE.

In the simulation results described below, the VDDH potential shown in FIG. 11 is 3.3 V, and the parameters used as the characteristics of the resistance change memory element are C ₂₄ = 1 nF, R ₂₂ = 100Ω, R ₂₃ = ₁ mΩ, t _1. = 1 ps, t ₂ = 100 ns, t ₃ = 1 ns, V _vddr = 1.0 V, V _vssr = _0.0 V, V _th = 0.5 V, T ₂ = 70.3 ns, and the reset voltage is 0.75 V, The set voltage is 1.60V.

  FIG. 19 is a diagram showing an operation mode at each time on the simulator. The first 100 ns is the power saving mode, the next 100 ns is the set mode, the next 100 ns is read after setting, the next 200 ns is reset mode, the next 100 ns is read after reset, and the next 100 ns is set mode The next 100 ns is read after setting, the next 200 ns is reset mode, and the next 100 ns is read after reset.

  Here, the power saving mode is a standby mode in which power is not consumed. The set mode is a mode in which the circuit is operated so that the resistance change memory element 43 provides a voltage signal that satisfies the set voltage condition. The reset mode is a mode in which the circuit is operated so that the resistance change memory element 43 provides a voltage signal that satisfies the reset voltage condition.

  The read mode is a mode in which a potential signal is output to the node 54 shown in FIG. 11 in accordance with the storage of the resistance change memory element 43, that is, the resistance state. In the read mode, when the resistance state of the resistance change memory element 43 is low resistance, a low potential close to 0.0 V is applied to the node 54, and when the resistance state of the resistance change memory element 43 is high resistance, the node 54 54 outputs a high potential close to 3.3V.

  In the first reset mode, that is, from 300 to 500 ns, the state in which the resistance change memory element 43 satisfies the reset voltage condition is a continuous mode for a long time. On the other hand, in the second reset mode, that is, from 800 to 1000 ns, in the intermittent mode, the resistance change memory element 43 repeats the state satisfying the reset voltage condition and the state not satisfying the reset voltage condition every relatively short time of about 10 ns. is there. Such an intermittent mode may not be used in an actual resistance change memory, but is set in this way to show the difference in operation between the two reset modes.

  FIG. 20 is a waveform diagram of signals given as XWE, CL1, CPL1, WL, and PRC. Since the detailed description of the circuit shown in FIG. 11 is beyond the scope of the present invention, a signal for performing the operation shown in FIG.

  FIG. 21 is a diagram for explaining the potential of each node obtained as a simulation result. Here, paying attention to the potential of the node 54, it can be estimated that the low-resistance state of the resistance change memory element 43 is read out at the time of 200 to 300 ns because the potential of the node 54 is close to 0.0V. Similarly, at time 500 to 600 ns, the potential of node 54 is close to 3.3 V, and it can be estimated that the high resistance state of resistance change memory element 43 has been read. Similarly, at time 700 to 800 ns, the potential of the node 54 is close to 0.0 V, and it can be assumed that the low resistance state of the resistance change memory element 43 has been read. Similarly, at time 1000 to 1100 ns, the potential of node 54 is close to 3.3 V, and it can be estimated that the high resistance state of resistance change memory element 43 has been read. Therefore, it can be inferred that the low resistance state is read in reading after setting, and the high resistance state is read in reading after resetting.

  FIG. 22 is a diagram for explaining the potential of each node obtained as a simulation result. In this figure, the voltage across the resistance change memory element 43, the current flowing through the selection transistor 44, the potential of the node dtmo in the subcircuit representing the resistance change memory element, the storage node rin in the subcircuit representing the resistance change memory element The potential is shown. Here, the net list shown in FIG. 11 used in this simulation includes only one resistance change memory element 43. Therefore, the node 51 in FIG. 11, the node bl in FIG. 1, the node 52 in FIG. 11, and the node gl in FIG. 1 represent the same node.

The assumption that the data has been read correctly after writing can be confirmed by the signals of the voltages, potentials, and currents shown in FIGS. In particular, a high resistance state is written at a specific time or a low resistance state is written by checking the potential of the storage node rin in the subcircuit shown in FIG. You can check whether or not. For example, at time 490 ns, the potential of the storage node rin is higher than V _th = 0.5V. Therefore, it can be seen that the state of the resistance change memory element at time 490 ns is high resistance.

In the first reset mode, the state where the reset voltage condition is satisfied starts at time 300 ns, and the potential of the storage node rin becomes V _th = 0.5 V around time 370 ns after T ₂ = 70.3 ns has passed. And you can see that a reset is taking place. Looking at the voltage, potential, and current signals in FIGS. 21 and 22, it can be seen that several voltages, potentials, and current signals have changed at this time.

In the second reset mode, a state where the reset voltage condition is satisfied first starts at time 800 ns, and after a certain amount of time has elapsed, the potential of the storage node rin reaches V _th = 0.5 V, and the reset is performed. I can see that it is happening. Here, paying attention to the voltage at both ends of the resistance change memory element 43, it can be seen that a period satisfying a condition of 0.75 V or more and 1.6 V or less as a reset voltage condition and a period not satisfying the condition are repeated. The time when the reset occurred is the time when the period satisfying the condition of 0.75 V or more and 1.6 V or less which is the reset voltage condition from time 800 ns reaches T ₂ = 70.3 ns in the cumulative total time.

Since the set occurs in a very short time that can be regarded as practically infinitesimal, the results shown in FIGS. 21 and 22 occur as soon as the voltage condition of the set is satisfied. For example, at time 100 ns, it can be seen from the fact that the set has occurred because the potential of the storage node rin in the subcircuit representing the resistance change memory element is the same as V _vssr = _0.0V . Here, if the delay element 31 is absent, the potential of the storage node rin stops at the same level as V _th = 0.5 V, so that resetting is very likely to occur immediately after setting, and the actual resistance change It is different from the memory element.

  In the example of the subcircuit described here, there is only one subcircuit representing the resistance change memory element in the simulation target netlist. However, even when there are a large number of subcircuits representing resistance change memory elements in the netlist to be simulated, simulation using this subcircuit is possible, and in such a case, it is more powerful. In an actual memory product or a CTEG that is close to the product, there are many subcircuits representing resistance change memory elements in the net list to be simulated. It should be noted that there are many subcircuits representing resistance change memory elements in the netlist to be simulated even if there are only one subcircuit representing resistance change memory elements on the netlist. Including the case where it is called at the point.

  In the simulation example given here, it can be seen that the operation was normal. In other words, the simulation values and expected values of the voltage, potential, and current signals matched. In such a case, it is concluded that the simulation target netlist operates normally, and the circuit design support ends. However, if it is not normal and there is even one place where the expected value does not match the simulation value of the voltage, potential, or current signal, it is necessary to correct the element attribute and netlist as necessary and perform simulation again. is there.

When the high resistance state is written, the expected value of the potential of the storage node rin after writing is V _th = 0.5 V or more. When the low resistance state is written, after writing, the potential of the storage node rin The expected value of the potential is V _th = 0.5 V or less. Accordingly, when the simulation value of the potential of the storage node rin is outside the range of the expected value of the potential of the storage node rin, it is necessary to correct the netlist of the circuit related to the write operation. Further, when reading is performed in a state where the potential of the storage node rin is V _th = 0.5 V or higher, the expected value of the potential of the node 54 is 2.7 V or higher, and the potential of the storage node rin is V _th. The expected value of the potential of the node 54 when reading is performed in a state of = 0.5V or less is 0.6V or less. In this case, if the simulation value of the potential of the node 54 is outside the range of the expected value of the potential of the node 54, the netlist of the circuit related to the read operation needs to be corrected. The above are only examples, and the scope of the present invention is not limited to these examples.

  According to such a simulation apparatus, the storage node indicating the storage state is provided in the subcircuit representing the storage unit, and the subcircuit representing the storage unit operates according to the state of the variable resistance unit. Therefore, the state after the operation of the subcircuit representing the storage unit is maintained, and based on the state, the subcircuit representing the storage unit can continuously perform the next operation. This is particularly effective when there are a large number of subcircuits representing resistance change memory elements in a simulation in which writing and reading are combined in a complicated manner.

  Further, by introducing a delay element, it is possible to avoid a behavior different from that of an actual resistance change memory element that a reset is likely to occur after setting. Further, by adjusting the resistance value, the capacitance value, and the like in the subcircuit, parameters such as a reset time, a set voltage, a reset voltage, and a resistance value in a high resistance state or a low resistance state can be freely set. Here, the accumulated time of the time that satisfies the reset voltage condition is applied to the reset time.

  As described above, since the analog simulation of the storage device using the storage unit including the resistance change memory element can be continuously performed, the resistance change memory simulation device and the resistance change memory capable of easily simulating the memory circuit including the storage unit described above. The simulation method and the circuit design support method can be provided.

(Second Embodiment)
Next, a second embodiment will be described. In the following description, the same constituent elements described in the first embodiment are denoted by the same reference numerals, and detailed description of the constituent elements and operations will be omitted.

  In the second embodiment, the delayed voltage signal described in the first embodiment is not transmitted from the variable resistance unit 10 to the storage unit 20, but is transmitted from the storage unit 20 to the variable resistance unit 10. It is characterized by.

  FIG. 23 is a circuit diagram showing the contents of a subcircuit corresponding to the resistance change memory element. This figure shows a circuit diagram relating to the second embodiment showing the contents of a sub-circuit corresponding to the resistance change memory element 43 shown in FIG.

  The subcircuit shown in FIG. 23 includes a variable resistance unit 10, a delay potential generation unit 60, and a storage unit 20. In this circuit, information on the state of the resistance change memory element, that is, the high resistance state or the low resistance state is represented by a storage node rin of the storage unit 20.

  The variable resistance unit 10 includes a high resistance element R11, a low resistance element R12, a resistance element R13, a resistance element R14, a node bl, and a node gl, and the high resistance element R11 and the resistance between the node bl and the node gl. The element R13 is connected in series. A low resistance element R12 and a resistance element R14 are connected in series between the node bl and the node gl.

  The high resistance element R11 represents a characteristic of the resistance change memory element 43 in the high resistance state, and is a voltage dependent resistance whose resistance value changes depending on the voltage applied to itself. For example, the high resistance element R11 has characteristics as shown in FIG.

  The low resistance element R12 is an element representing the characteristics of the resistance change memory element in the low resistance state. The low resistance element R12 may be a voltage-dependent resistor whose resistance value changes depending on the voltage applied to itself, or may be a constant resistance whose resistance value does not change depending on the voltage applied to itself. In the case of a constant resistance, for example, 4 kΩ is suitable for the low resistance element R12.

  On the other hand, the storage unit 20 includes a high-potential power supply node vddr, a low-potential power supply node vssr, a storage node rin, a resetter switch, a resistance element R21 that functions as a resetter load resistance element, a resistance element R23 that functions as a setter switch, and a capacitor C24. The resistor element R21 and the resistor element R23 are connected in series between the high potential power supply node vddr and the low potential power supply node vssr. A capacitor C24 is connected between the storage node rin and the low potential power supply node vssr.

Here, the resistance element R21 and the resistance element R23 are voltage-dependent resistances that depend on the voltage between the two nodes bl-gl.
The resistance elements R21, when a voltage between two nodes bl- node gl is equal to or less than the reset voltage higher than the set voltage, the resistance value becomes a certain low value R _22, otherwise, very high Resistance (open state).

The potential of the storage node rin changes by changing the resistance values of the resistance element R21 and the resistance element R23.
The delay potential generator 60 includes a delay element 61, a node drin, and a low potential power supply node vssr. The delay element 61 is an element for preventing a reset from easily occurring after setting. The delay element 61 copies the potential of the storage node rin to the potential of the node drin with a somewhat short delay t ₃ .

  FIG. 24 is a diagram for explaining the role and function of the elements constituting the resistance change memory element. The example described in FIG. 24 shows an example of how the names of circuit elements are set in the netlist description of an analog simulator such as HSPICE.

This completes the description of the configuration of the circuit shown in FIG. 23 and the role of each element. Next, the operation of the circuit shown in FIG. 23 will be described.
FIG. 25 is a circuit diagram corresponding to a resistance change memory element. FIG. 25 is a diagram specifically explaining the circuit configuration shown in FIG. 23 in order to easily understand the operation of the subcircuit shown in FIG. FIG. 25 shows the basic principle of the simulation apparatus according to the second embodiment. In this figure, in order to easily understand the basic principle of the simulation apparatus, a resistive element having a switching function is directly represented as a switching element.

  The left side of FIG. 25 is the variable resistance unit 10, and the right side is the storage unit 20. The storage unit 20 has a function of holding storage and changing the state and stored contents in accordance with information such as a voltage applied to the variable resistance unit 10. Further, the variable resistance unit 10 has a function of changing the resistance value between the two nodes bl-gl by the potential of the storage node rin of the storage unit 20.

  The circuit configuration shown in FIG. 25 is characterized in that information on the state of the resistance change memory element 43 shown in FIG. is there. The above points are the same as the contents described in the first embodiment.

The difference between the second embodiment and the first embodiment is the role of the delay potential generator described below.
One of the switch SW13 that selects the high resistance state and the switch SW14 that selects the low resistance state are always conductive in accordance with the potential of the storage node rin.

  For example, when the potential of the storage node rin is high, the resistance value between the two nodes bl-node gl is a high resistance, and when the potential of the storage node rin is low, between the two nodes bl-node gl When controlling the resistance value to be low, the switch SW13 is turned on when the potential of the storage node rin is high, and the switch SW14 is turned on when the potential of the storage node rin is low. The idea of this point is the same as in the first embodiment.

  In the second embodiment, the voltage between the two nodes bl-gl is used as it is for determining whether the resetter switch SW21 or the setter switch SW23 is to be conducted.

However, one of the switch SW13 and the switch SW14 is always turned on according to the potential obtained by delaying the potential of the storage node rin for a short time.
That is, in the first embodiment, a voltage obtained by delaying the voltage between the two nodes bl-gl for a short time is used to determine whether the resetter switch SW21 and the setter switch SW23 are turned on. On the other hand, in the second embodiment, either one of the switch SW13 and the switch SW14 is always turned on according to the potential obtained by delaying the potential of the storage node rin for a short time. That is, the difference between the first embodiment and the second embodiment is that the delay potential generation unit that generates the potential signal to be delayed and the switch that is affected by the delay potential are changed.

By doing so, the resistance change memory element 43 operates as follows at the time of setting. In a state where the voltage between the two nodes bl and the node gl satisfies the set voltage condition, the setter switch SW23 is in a conductive state and the resetter switch SW21 is in an insulated state (open state). Here, immediately after the potential of the storage node rin is changed from a state above the reference potential _Vth to a state below the reference potential _Vth , the resistance between the two nodes bl-nodegl does not immediately become a low resistance state.

In other words, even in a state where the potential of the storage node rin is lower than the reference potential V _th , the high resistance state between the two nodes bl-gl continues for the length of the delay time.
In the time corresponding to the delay time, the variable resistor 10 recognizes that the setter switch SW23 is in a conductive state and the resetter switch SW21 is in an insulated state. Therefore, the potential of the storage node rin reaches substantially the same potential as the low potential power supply node vssr until the time corresponding to the delay time ends. As a result, even if the reset voltage condition is satisfied after setting, the reset operation starts from the state where the potential of the storage node rin is the same as that of the low potential power supply node vssr. It can be adjusted by the RC product of the resetter load resistance element R22 and the capacitor C24 in which the potential of rin rises from the potential of the low potential power supply node vssr to the potential of the high potential power supply node vddr.

As described above, in the second embodiment, in order to avoid the problem that the reset is likely to occur immediately after the setting, the two nodes bl-node gl in a state where the potential of the storage node rin is lower than the reference potential _Vth. The state in which the resistance value between them is high resistance continues for the length of the delay time.

The role of each other element, the reset time setting method, and the like are the same as in the first embodiment.
Now that the description of the operation of the sub-circuit has been completed, returning to FIG. 23 again, the operation of the sub-circuit used in the simulation apparatus will be described in correspondence with the basic principle shown in FIG. Hereinafter, more specific arrangement and connection of circuit elements on the simulator will be described. In addition, in an analog simulator such as HSPICE, the switches used in FIG.

In HSPICE, a voltage-dependent resistor is described as an element whose resistance value changes with a voltage with a sign between two specific points. Here, the voltage with a sign between two specific points is represented by “V _DB −V _DA ” when the potentials of the two specific points are V _DA and V _DB . Hereinafter, the potential V _vssr of the low voltage power supply node vssr is _0.0 V, and the “potential of the storage node rin” is “the voltage between the storage node rin and the low voltage power supply node vssr” and “the potential of the storage node rin. It is assumed that it is the same as “subtracting the potential of the low voltage power supply node vssr”. However, the scope of claims of this patent is not limited to the case of V _vssr = _0.0V .

  The read characteristics of the resistance change memory element in the high resistance state and the low resistance state can be freely adjusted by adjusting the characteristics of the high resistance element R11 and the low resistance element R12. The high resistance element R11 and the low resistance element R12 can be substituted by using a voltage dependent current source.

The resistance element R13 and the resistance element R14 are resistances that do not depend directly on the potential of the storage node rin, but depend on the potential of the node drin of the delay potential generation unit 60. That is, it depends on the potential obtained by delaying the potential of the storage node rin by the delay time t ₃ .

  The resistance element R13 functions as a switch, and has a very low resistance (conducting state) when the potential of the node drin is high, and has a very high resistance (open state) when the potential of the node drin is low. It becomes.

Resistance element R14 functions as a switch, a node very when the potential of drin is lower than the reference potential V _th becomes low resistance (conductive), when the potential of the node drin is higher than the reference potential V _th is very high Resistance (open state). In this way, the reference of whether the resistance element R13 and the resistance element R14 become very high resistance (open state) or very low resistance (conduction state) is determined by the reference potential V _th , and the value is, for example, 0. 5V is suitable.

For the stable operation of the simulation, it is preferable that there is no potential at the node drin where both the resistance element R13 and the resistance element R14 become very high resistance (open state).
As one method for preventing both of the resistance element R13 and the resistance element R14 from becoming very high resistance (open state) when the potential of the node drin is just V _th , the resistance element R13 includes the node drin. The resistance of the resistance element R14 becomes extremely low resistance (conducting state) when the potential of the node drin is 0.5001V or less. Can be mentioned.

  In order to make the difference between the read element and the actual element negligibly small, the resistance values of the resistance element R13 and the resistance element R14 in a very low resistance (conductive state) state are the resistance values of the high resistance element R11 and the low resistance element R12. The resistance value of the resistance element R13 and the resistance element R14 in a very high resistance (open state) is very small compared to the resistance value, and is at least an order of magnitude smaller than the resistance value of the high resistance element R11 and the low resistance element R12. It should be very large compared to the value, at least an order of magnitude larger.

  The resistance value of the resistance element R13 and the resistance element R14 in the low resistance (conducting state) state is, for example, 1 mΩ, and the resistance value of the resistance element R13 and the resistance element R14 in the very high resistance state (high resistance state) is For example, 1 TΩ is suitable. Specifically, for example, the resistance element R13 becomes 1 mΩ when the potential of the node drn is 0.4999 V or more, and becomes 1 TΩ when the potential of the node drn is 0.4999 V or less. The resistance element R14 becomes 1 mΩ when the potential of the node drn is 0.5001V or lower, and becomes 1TΩ when the potential of the node drin is 0.5001V or higher.

When the resistance values of the resistance element R13 and the resistance element R14 themselves in a conductive state are sufficiently lowered, when the potential of the storage node rin is higher than the standard potential V _th, between the node bl and the node gl illustrated in FIG. Only the high resistance element R11 exists alone, and when the potential of the storage node rin is lower than the standard potential _Vth, only the low resistance element R12 exists alone.

As described above, the delay element 61 of the delay potential generation unit 60 is an element for preventing a reset from being easily caused after setting. The delay element 61 copies the potential of the storage node rin to the potential of the node drin with a somewhat short delay time (t ₃ ). Here, copying to the potential of the node drin means copying to the voltage between the node drin and the low potential power supply node vssr. “Drin potential”, “voltage between the node drin and the low potential power supply node vssr”, and “the potential of the node drin minus the potential of the low potential power supply node vssr” are synonymous.

For example, 1 ns is suitable as the delay time t ₃ . Since the delay element 61 exists in HSPICE, it may be used as it is.
The delay element 61 is described as, for example, “E61 drain vssr VCVS DELAY rin vssr TD = 1 ns”.

  This means that a delay of 1 ns is applied and the voltage between the storage node rin and the low potential power supply node vssr is copied to the voltage between the node drin and the low potential power supply node vssr.

Resistive element R23 of the memory unit 20, as described above, will be somewhat lower resistance when the voltage between two nodes bl- node gl becomes set voltage or higher (the resistance value R _23), otherwise In this case, the resistance becomes very high (open state).

Also, the somewhat lower resistance R ₂₂ of resistor elements R21, for example, 100Ω are suitable. Resistance R ₂₃ of the state resistance of the resistive element R23 (conductive state), for example, 1 M.OMEGA is suitable. For example, 10 ¹⁸ Ω is suitable for the resistance value of the resistance element R21 in a very high resistance (open state) state.

The set voltage and the reset voltage can be, for example, 1.6V and 0.75V, respectively. Needless to say, the set voltage and the reset voltage can be freely adjusted. Specifically, for example, the resistance value of the resistance element R21 is 100Ω when the voltage between the two nodes bl and the node gl is 0.75 V or more and 1.6 V or less, and otherwise, the resistance value is 10Ω. ¹⁸ Ω, and the resistance element R23 becomes 1 mΩ when the voltage between the two nodes bl-gl becomes 1.6 V or more, otherwise it becomes 10 ¹⁸ Ω.

The capacitor C24 is a capacitive element having a certain capacity for storing and giving a delay. The capacitor C24 has a function of holding the potential of the storage node rin when both the resistance element R21 and the resistance element R23 have very high resistance values (open state). The product t ₂ of the resistance value R ₂₂ of the resistance element R 21 and the capacitance value C ₂₄ of the capacitor C ₂₄ determines the reset time. Capacitance C ₂₄ of the capacitor C24, for example 1nF is suitable.

The time constants of the potential change of the storage node rin at the time of setting and at the time of resetting are expressed as t ₁ = R ₂₃ C ₂₄ and t ₂ = R ₂₂ C ₂₄ , respectively, but in the example given here, t ₁ = 1 ps, t ₂ = 100 ns, t ₃ = 1 ns. Therefore, it can be seen that the relationship of t ₁ << t ₃ << t ₂ is satisfied. The potential of the high potential power supply node vddr is V _vddr = 1.0 V, and the potential of the low potential power supply node vssr is V _vssr = _0.0 V as already described. At this time, according to the equations (1) to (3), the time required for reset is T ₂ = 70.3 ns. On the other hand, the time required for the set is approximately determined by the delay time t ₃ at which the delay element 61 functions, and is approximately 1 ns.

As described in the first embodiment, the delay element 61 provided in advance by HSPICE may not be used for the delay potential generator 60.
In the circuit shown in FIG. 23, a capacitor C15 may be inserted in parallel with the variable resistor 10 as shown in FIG. 7 described in the first embodiment.

The circuit shown in FIG. 23 exhibits electrical characteristics very close to those of an actual resistance change memory element based on the above operation principle.
23 is incorporated as the resistance change memory element 43 of the circuit shown in FIG. 11, the circuit shown in FIG. 11 operates very close to the circuit including the actual resistance change memory element. Therefore, if the netlist is correctly described and the parameters of the netlist incorporated as the resistance change memory element 43 are correct, the operation equivalent to that of a semiconductor chip or semiconductor macro manufactured or prototyped as a product or CTEG is reproduced on the simulation apparatus. Is possible. As a result, the design of the circuit including the resistance change memory element can be supported and made efficient by the method as shown in FIGS.

  Also in the second embodiment, a circuit design support method and simulation similar to the circuit design support method example and simulation example described with reference to FIGS. 13 to 22 of the first embodiment are possible.

The effect of the invention of the second embodiment is the same as that of the first embodiment.
(Third embodiment)
Next, a third embodiment will be described. In the following description, the same constituent elements described in the first and second embodiments are denoted by the same reference numerals, and detailed description of the constituent elements and operations will be omitted.

The third embodiment is characterized in that the storage unit includes a pullback switch.
FIG. 26 is a circuit diagram showing the contents of a subcircuit corresponding to the resistance change memory element. This figure is a circuit diagram relating to the third embodiment showing the contents of a sub-circuit corresponding to the resistance change memory element 43 shown in FIG.

  The circuit shown in this figure includes a variable resistance unit 10, a delay potential generation unit 70, and a storage unit 20. The circuit configuration shown in FIG. 26 is characterized in that the state of the resistance change memory element, that is, information on the high resistance state or the low resistance state is represented by the storage node rin of the storage unit 20.

  The variable resistance unit 10 includes a high resistance element R11, a low resistance element R12, a resistance element R13, and a resistance element R14. In addition, the delay potential generator 70 includes a delay element 71. These two portions are the same as those of the variable resistor 10 and the delay potential generator 30 shown in FIG. 1 in the first embodiment, and the description thereof is omitted.

  The storage unit 20 includes a resistance element R21 that functions as a resetter switch and a resetter load resistance element, a resistance element R23 that functions as a setter switch, resistance elements R25 and R26 that function as a pullback switch, and a capacitor C24. A resistance element R21 and a resistance element R23 are connected in series between the power supply node vddr and the low potential power supply node vssr. In addition to the capacitor C24, resistance elements R25 and R26 are connected in parallel between the storage node rin and the low potential power supply node vssr. Here, the resistance elements R25 and R26 are variable resistors.

  FIG. 27 is a diagram for explaining the roles and functions of the elements constituting the resistance change memory element. The description example shown in this figure shows an example of how the names of circuit elements are set in the netlist description of an analog simulator such as HSPICE. In this figure, the description example of the variable resistance section is the same as that in FIG.

This completes the description of the configuration of the circuit shown in FIG. 26 and the role of each element. Next, the operation of the circuit shown in FIG. 26 will be described.
FIG. 28 is a circuit diagram corresponding to a resistance change memory element. FIG. 28 is a diagram more specifically explaining the circuit configuration shown in FIG. 26 in order to easily understand the operation of the subcircuit shown in FIG. FIG. 28 shows the basic principle of the simulation apparatus according to the third embodiment. In this figure, in order to easily understand the basic principle of the simulation apparatus, a resistive element having a switching function is directly represented as a switching element.

  The left side of FIG. 28 is the variable resistance unit 10, and the right side is the storage unit 20. The storage unit 20 has a function of holding storage and changing the state and stored contents in accordance with information such as a voltage applied to the variable resistance unit 10. On the other hand, the variable resistance unit 10 has a function of changing the resistance value between the two nodes bl-gl by the potential of the storage node rin of the storage unit 20.

  The circuit configuration shown in FIG. 28 is characterized in that information on the state of the resistance change memory element, that is, the high resistance state or the low resistance state, is represented by the storage node rin of the storage unit 20 that represents the storage unit. . The above points are the same as in the first embodiment described with reference to FIG.

Moreover, the variable resistance part 10 in 3rd Embodiment is the same as that of the variable resistance part 10 shown in FIG. Therefore, in the following, the storage unit 20 in the third embodiment will be described in detail.
The storage unit 20 includes a high potential power supply node vddr, a low potential power supply node vssr, a storage node rin, a resetter switch SW21, a resetter load resistance element R22, a setter switch SW23, a capacitor C24, and pullback switch SW25 and SW26. Yes.

  The storage unit 20 according to the third embodiment is different from FIG. 1 in that it includes two pullback switch SW25 and SW26 that are connected in series. With these two pullback switch SW25 and SW26, the recording unit 20 is in a state where the resistance between the two nodes bl-gl is in a low resistance state, and the state satisfying such a reset voltage condition is interrupted. , And has a function of returning the potential of the storage node rin to the same potential as that of the low potential power supply node vssr. By providing these two pullback switch SW25 and SW26, the time required for resetting is not an accumulated time but a continuous time (described later).

  The pullback switch SW25 is turned on when the voltage between the two nodes bl-gl does not satisfy the reset voltage condition. The pullback switch SW26 conducts when the potential of the storage node rin is low. In other words, the pullback switch SW25 is turned on when “the state satisfying the reset voltage condition is interrupted”, and the pullback switch SW26 is turned on when “the resistance between the two nodes bl-gl is in a low resistance state. ”. The storage node rin and the low potential power supply node vssr are conducted through the path of the two pullback switches SW25 and SW26 when both the two pullback switches SW25 and SW26 are conducted. That is, when the resistance between the two nodes bl-gl is in a low resistance state and the state satisfying the reset voltage condition is interrupted, both the pullback switches SW25 and SW26 are turned on.

  The setter switch SW23 and the resetter switch SW21 are turned on when the set voltage condition is satisfied and when the reset condition is satisfied, respectively. Since these actions are the same as those in the first embodiment, further explanation is omitted. Incidentally, whether or not the pullback switch SW25 is turned on when the set voltage condition is satisfied hardly affects the operation. This is because when the set voltage condition is satisfied, the setter switch SW23 is conductive.

When neither the set condition nor the reset condition is satisfied, neither the setter switch SW23 nor the resetter switch SW21 is conducted. In this case, when the potential of the storage node rin is equal to or higher than the reference potential _Vth and is in a high resistance state, the pullback switch SW26 is not turned on, and the potential is held by the function of the capacitor C24.

On the other hand, when the potential of the storage node rin satisfies the reset voltage condition is interrupted and becomes equal to or lower than the standard potential _Vth , and when the resistance between the two nodes bl-gl is in the low resistance state, Both the backer switch SW25 and the pull backer switch SW26 conduct, and the potential of the storage node rin becomes the same potential as the low potential power supply node vssr.

Similar to the description of the first embodiment, a delay element is necessary to avoid a state in which reset is likely to occur after setting.
In the third embodiment, a delay element having a function similar to that of the first embodiment is used. A voltage obtained by delaying the voltage between the two nodes bl and the node gl for a short time is used to determine whether or not the setter switch SW23, the resetter switch SW21, and the pullback switch SW26 are made conductive.

  That is, the setter switch SW23 is turned on when the voltage signal obtained by delaying the voltage between the two nodes bl-gl is a set voltage or more, and the resetter switch SW21 is connected between the two nodes bl-gl. Conduction is performed when the voltage signal obtained by delaying the voltage for a short time is not less than the reset voltage and not more than the set voltage. In addition, the pullback switch SW25 conducts when the voltage signal obtained by delaying the voltage between the two nodes bl and gl for a short time is equal to or lower than the reset voltage.

  The delay element described in the second embodiment and the storage unit 20 in the third embodiment can be combined. The reset time setting method and the like are the same as those in the first embodiment, and a description thereof is omitted here.

  Next, from the state where the reset voltage condition is satisfied, the voltage applied between the two nodes bl-node gl becomes equal to or lower than the reset voltage (the reset voltage condition is interrupted), and again from the state where the reset voltage condition is not satisfied A description will be given of how the storage node rin operates when the reset voltage condition is satisfied.

FIG. 29 is a diagram for explaining a change in potential of the storage node rin when resetting. The horizontal axis represents time (ns), and the vertical axis represents rin potential (V). This figure was created using the conditions t ₂ = 100 ns, t ₃ = 1 ns, V _vddr = 1.0 V, V _vssr = _0.0 V, V _th = 0.5 V, T ₂ = 70.3 ns. ing.

  A period A and a period C in FIG. 29 are periods in which the reset voltage condition is satisfied. The period B is a period in which neither the reset voltage condition nor the set voltage condition is satisfied, that is, a period in which the voltage between the two nodes bl-node gl is equal to or lower than the reset voltage. Moreover, this figure is an example and is not limited to the above numerical values and the examples described later. In addition, the theory and description in the third embodiment are described using not only the above numerical values and the following examples but also examples.

In the period A and the period C, the potential of the storage node rin, when changes in the constant t _2.
The potential V _rin of the storage node rin in the period A is expressed by the following formula.
V _rin (t) = V _vssr + (V _vddr −V _vssr ) (1−exp (− (t−t ₃ ) / t ₂ )
) …… (4)
Further, when the length of the period A is T _2A and the length of the period B is T ₄ , the potential V _rin of the storage node rin in the period C is expressed by the following expression.

V _rin (t) = V _vssr + (V _vddr −V _vssr ) (1−exp (− (t− (T _2A + T ₄ +
t ₃ )) / t ₂ )) …… (8)
In the configuration shown in FIG. 29, continuous time is applied as the time required for resetting. In other words, as long as they do not satisfy the voltage condition of the set, not occur reset as long as the continuous time period that meets the voltage condition of the reset does not reach T _2, the resistance value between the two nodes bl- node gl high resistance do not become. In FIG. 29, _assuming that the lengths of period A and period C are T _2A and T _2C , no reset occurs even if T _2A + T _2C ≧ T ₂ . If T _2A ≧ T ₂ or T _2C ≧ T ₂ , a reset occurs. This is the difference from the first embodiment. This difference is caused by the functions of the pullback switches SW25 and SW26.

Furthermore, the third embodiment will be described with specific numerical examples.
The potential of the high potential power supply node vddr shown in FIG. 28 is always 1.0 V, the potential of the low potential power supply node vssr is always 0.0 V, the resistance value of the resetter load resistance element R22 is 100Ω, and the capacitance value of the capacitor C24 is 1 nF. . When the potential of the storage node rin is higher than 0.5V, the resistance value between the two nodes bl-node gl is high resistance, and when the potential of the storage node rin is lower than 0.5V, between the two nodes bl-node gl Resistance value is low. When these are expressed by the symbols used so far, C ₂₄ = 1 nF, R ₂₂ = 100Ω, t ₂ = 100 ns, t ₃ = 1 ns, V _vddr = 1.0 V, V _vssr = _0.0 V, V _th = 0. 5V.

Under this condition, T ₂ = 70.3 ns. Further, it can be easily understood that the expressions 4 and 8 become the following expressions 6 and 9, respectively. However, we do not assign a numerical value for the t _2.

V _rin (t) = 1−exp (− (t−t ₃ ) / t ₂ ) ≈1−exp (−t / t ₂ ) (6)
V _rin (t) = 1−exp (− (t− (T _2A + T ₄ + t ₃ )) / t ₂ ) ≈1−exp (− (t− (T _2A + T ₄ )) / t ₂ ) ( 9)
This is the end of the description of the operation of the sub-circuit. Returning to FIG. 26 again, the operation of the sub-circuit used in the simulation apparatus will be described in correspondence with the basic principle shown in FIG. Hereinafter, more specific arrangement and connection of circuit elements on the simulator will be described. In an analog simulator such as HSPICE, the switches used in FIG. 28 are preferably voltage-dependent resistors.

In HSPICE, a voltage-dependent resistor is described as an element whose resistance value changes depending on a voltage with a sign between two specific points. Here, the voltage with a sign between two specific points is represented by “V _DB −V _DA ” when the potentials of the two specific points are V _DA and V _DB . Hereinafter, the potential V _vssr of the low voltage power supply node vssr is _0.0 V, and the “potential of the storage node rin” is “the voltage between the storage node rin and the low voltage power supply node vssr” and “the potential of the storage node rin. It is assumed that it is the same as “subtracting the potential of the low voltage power supply node vssr”. However, the _present invention is not limited to the case where V _vssr = _0.0V .

As described above, the resistance element R21, the resistance element R23, the resistance element R25, and the resistance element R26 of the storage unit 20 are voltage-dependent resistors that depend on the potential of the node dtmo. It does not depend directly on the voltage between the two nodes bl-gl, but depends on the voltage obtained by delaying the voltage between the two nodes bl-gl by the delay time t ₃ by depending on the potential of the node dtmo. To do.

Resistive element R21, the resistance value becomes a certain low value R ₂₂ when the potential of the node dtmo is equal to or less than the reset voltage higher than the set voltage, otherwise, would be very high resistance (open state).

The resistance element R23 has a low resistance (resistance value R ₂₃ ) when the potential of the node dtmo becomes equal to or higher than the set voltage, and in other cases, the resistance element R23 has a very high resistance (open state).
The resistance element R25 has a low resistance (resistance value R ₂₅ ) when the potential of the node dtmo becomes equal to or lower than the reset voltage, and otherwise has a very high resistance (open state).

The resistance element R26 has a very low resistance (conductive state) when the potential of the storage node rin is low, and has a very high resistance (open state) when the potential of the storage node rin is high.
Somewhat lower resistance R ₂₂ of resistor element R21, for example 100Ω are suitable. For example, 1 mΩ is suitable for each of the resistance values R ₂₃ , R ₂₅ , and R ₂₆ in the low resistance state of the resistance elements R ₂₃ , R ₂₅ , and R ₂₆ . For example, 10 ¹⁸ Ω is suitable as the resistance value of the resistance element R21 and the resistance elements R25 and R26 in a very high resistance (open state) state. For example, the set voltage and the reset voltage can be 1.6 V and 0.75 V, respectively. However, the set voltage and the reset voltage can be freely adjusted.

The potential of the storage node rin, which is a criterion for determining whether the resistance value of the resistance element R26 is very high resistance (open state) or very low resistance (conduction state), is that the resistance element R13 and the resistance element R14 are very It is assumed that it is the same as the reference potential V _th of the storage node rin that is a criterion for determining whether the resistance is high (open state) or very low resistance (conduction state). For example, 0.5V is suitable.

More specifically, the resistance value of the resistance element R21 is 100Ω when the potential of the node dtmo is not less than 0.75V and not more than 1.6V, and otherwise is 10 ¹⁸ Ω. The resistance element R23 becomes 1 mΩ when the potential of the node dtmo becomes 1.6V or more, and becomes 10 ¹⁸ Ω in other cases.

The resistance value of the resistance element R25 is 1 mΩ when the potential of the node dtmo is 0.75 V or less, and 10 ¹⁸ Ω otherwise. The resistance value of the resistance element R26 is 1 mΩ when the potential of the storage node rin is 0.5 V or lower, and 10 ¹⁸ Ω otherwise.

The capacitor C24 is a capacitive element having a certain capacity for storing and giving a delay. In the capacitor C24, both the resistance element R21 and the resistance element R23 are both very high resistance (open state), and at least one of the resistance element R25 and the resistance element R26 has very high resistance (open state). Sometimes, it has a function of holding the potential of the storage node rin. The product t ₂ of the resistance value R ₂₂ of the resistance element R 21 and the capacitance value C ₂₄ of the capacitor C ₂₄ determines the reset time. Capacitance C ₂₄ of the capacitor C24, for example 1nF is suitable.

Although expressed as t ₁ = R ₂₃ C ₂₄ and t ₂ = R ₂₂ C ₂₄ , in the example given here, t ₁ = 1 ps, t ₂ = 100 ns, and t ₃ = 1 ns. Therefore, it can be seen that the relationship of t ₁ << t ₃ << t ₂ is satisfied. The potential of the high potential power supply node vddr is V _vddr = 1.0 V, and the potential of the low potential power supply node vssr is V _vssr = _0.0 V. At this time, according to the equations (1) to (3), the time required for reset is T ₂ = 70.3 ns. On the other hand, the time required for setting is approximately 1 ns, which is determined approximately by the delay time t ₃ at which the delay element 71 functions.

  In the circuit shown in FIG. 26, a capacitor C15 may be inserted in parallel with the variable resistor unit 10. The variable resistance unit 10 in this case is as shown in FIG. Since an actual resistance change memory element has a structure in which a substance having a relatively high resistance value is inserted between parallel plates made of two conductors, a capacitance component exists between the parallel plates. The capacitor C15 reproduces the capacitance component between the parallel plates. The presence of the capacitor C15 does not change the essential operation of the circuit shown in FIG.

  Actual simulation results will be described with specific examples. The example given below does not necessarily correspond to the example of the circuit design support method shown in FIGS. 12 to 18 and 20 in the first embodiment, but shows an example of a simulation result.

  In the example given below, a specific potential signal is given to the gate nodes XWE, CL1, CPL1, WL, and PRC of each transistor of the circuit including the resistance change memory element 43 shown in FIG. Reading is performed later, and a reading result as written is obtained, and it is confirmed whether or not the potential of each node is as intended.

  The resistance change memory element 43 here uses the net list shown in FIG. This point is different from the specific example of the simulation result in the first embodiment. The simulation results given below are the results obtained by actually simulating with HSPICE.

The parameters used as the characteristics of the resistance change memory element with VDDH = 3.3V are C ₂₄ = 1 nF, R ₂₂ = 100Ω, R ₂₃ = 1 mΩ, R ₂₅ = 1 mΩ, R ₂₆ = ₁ mΩ, t ₁ = 1 ps, t ₂ = 100 ns, t ₃ = 1 ns, V _vddr = 1.0 V, V _vssr = _0.0 V, V _th = 0.5 V, T ₂ = 70.3 ns, and reset voltage is 0.75 V, set voltage is 1 .60V.

  The operation mode at each time on the simulator is the same as that shown in FIG. 19 in the first embodiment. The first 100 ns is the power saving mode, the next 100 ns is the set mode, the next 100 ns is read after setting, the next 200 ns is reset mode, the next 100 ns is read after reset, and the next 100 ns is set mode The next 100 ns is read after setting, the next 200 ns is reset mode, and the next 100 ns is read after reset.

  The power saving mode is a standby mode in which power is not consumed. The set mode is a mode for operating the circuit so that the resistance change memory element 43 provides a voltage signal that satisfies the set voltage condition, and the reset mode is a voltage signal that the resistance change memory element 43 satisfies the reset voltage condition. In this mode, the circuit is operated so as to give

  In the read mode, a potential signal is output to the node 54 in accordance with the storage of the resistance change memory element 43, that is, the resistance state. In the read mode, when the resistance state of the resistance change memory element 43 is low resistance, a low potential close to 0.0 V is applied to the node 54, and when the resistance state of the resistance change memory element 43 is high resistance, the node 54 54 outputs a high potential close to 3.3V.

  In the first reset mode, that is, from 300 to 500 ns, the state in which the resistance change memory element 43 satisfies the reset voltage condition is a continuous mode for a long time. On the other hand, in the second reset mode, that is, from 800 to 1000 ns, in the intermittent mode, the resistance change memory element 43 repeats the state satisfying the reset voltage condition and the state not satisfying the reset voltage condition every relatively short time of about 10 ns. is there. Such an intermittent mode may not be used in an actual resistance change memory, but in order to show the difference in operation between these two reset modes, such a setting is used.

  FIG. 30 is a diagram for explaining the waveforms of signals given as XWE, CL1, CPL1, WL, and PRC. Since the detailed description of the circuit shown in FIG. 11 is beyond the scope of the present invention, a signal for causing the operation shown in FIG.

  FIG. 31 is a diagram for explaining the potential of each node obtained as a simulation result. Here, attention is paid to the node 54. From time 200 to 300 ns, the potential of the node 54 is close to 0.0 V, and it can be assumed that the low resistance state of the resistance change memory element 43 has been read.

From time 500 to 600 ns, the potential of the node 54 is close to 3.3 V, and it can be assumed that the high resistance state of the resistance change memory element 43 has been read.
From time 700 to 800 ns, the potential of the node 54 is close to 0.0 V, and it can be assumed that the low resistance state of the resistance change memory element 43 has been read.

At time 1000 to 1100 ns, the potential of the node 54 is close to 0.0 V, and it can be assumed that the low resistance state of the resistance change memory element 43 has been read.
Therefore, the low resistance state is read in the read after the first set, the high resistance state is read in the read after the first reset, and the low resistance state is read in the read after the second set. It can be inferred that the low resistance state is also read out after the second reset. Here, the low resistance state is read even after the second reset, which is different from the specific example of the simulation result in the first embodiment.

  FIG. 32 is a diagram for explaining the potential of each node obtained as a simulation result. FIG. 32 shows the voltage across the resistance change memory element 43, the current flowing through the selection transistor 44, the potential of the node dtmo in the subcircuit representing the resistance change memory element, and the storage node rin in the subcircuit representing the resistance change memory element. The potential is shown. Here, the net list shown in FIG. 26 used in this simulation includes only one resistance change memory element. Therefore, the node 51 shown in FIG. 11 and the node bl shown in FIG. 26, the node 52 shown in FIG. 11 and the node gl shown in FIG. 26 represent the same node.

In order to interpret the results different from those of the first embodiment, the voltage, potential, and current signals in FIGS. 31 and 32 may be examined. In particular, by examining the potential of the storage node rin shown in FIG. 26, it is possible to investigate whether a high resistance state is written or a low resistance state is written at a specific time. For example, at time 490 ns, the potential of the storage node rin is higher than V _th = 0.5V. Therefore, it can be seen that the state of the resistance change memory element at time 490 ns is high resistance.

In the first reset mode, the state where the reset voltage condition is satisfied starts at time 300 ns, and the potential of the storage node rin becomes V _th = 0.5 V around time 370 ns after T ₂ = 70.3 ns has passed. And you can see that a reset is taking place. Looking at the voltage, potential, and current signals in FIGS. 31 and 32, it can be seen that several voltages, potentials, and current signals have changed at this time.

In the second reset mode, the state where the reset voltage condition is satisfied first starts at time 800 ns. However, after that, the potential of the storage node rin does not reach V _th = 0.5 V, indicating that no reset has occurred. Here, paying attention to the voltage at both ends of the resistance change memory element 43, it can be seen that a period satisfying a condition of 0.75 V or more and 1.6 V or less as a reset voltage condition and a period not satisfying the condition are repeated. When the two pullback switch functions shown in FIG. 26 do not satisfy the reset voltage condition, the potential of the storage node rin is returned to the same potential as the low potential power supply node vssr, and the reset voltage condition is changed. This is because the reset does not occur permanently unless the time of continuous T ₂ = 70.3 ns is satisfied. This point is different from the first embodiment. Of course, in the subsequent reading, the low resistance state is read.

Since the set occurs in a very short time that can be regarded as practically infinitesimal, the results of FIGS. 31 and 32 occur as soon as the voltage condition of the set is satisfied. For example, at time 100 ns, it can be seen from the fact that the set has occurred because the potential of the storage node rin in the subcircuit representing the resistance change memory element is the same as V _vssr = _0.0V . Here, if there is no delay element 71, the potential of the storage node rin stops at the same level as V _th = 0.5 V, and resetting is very likely to occur immediately after setting, so that the actual resistance change It is different from the memory element.

  In the example of the subcircuit described here, there is only one subcircuit representing the resistance change memory element in the simulation target netlist. However, even when there are a large number of subcircuits representing resistance change memory elements in the netlist to be simulated, simulation using these subcircuits is possible, and in such a case, power is demonstrated. In an actual memory product or a CTEG that is close to the product, there are many subcircuits representing resistance change memory elements in the net list to be simulated. It should be noted that there are many subcircuits representing resistance change memory elements in the netlist to be simulated even if there are only one subcircuit representing resistance change memory elements on the netlist. Including the case where it is called at the point.

  Here, it is assumed that a high resistance state is expected to be written in the second reset. In that case, the example of the simulation result shown here is different from the expected result. That is, there are portions where the simulation values of voltage, potential, and current signals do not match the expected values. In this case, it is necessary to modify element attributes, netlists, and the like. Here, it is further assumed that the characteristic of the resistance change memory element is the characteristic described with reference to FIGS. In such a case, it can be determined that the simulation target netlist needs to be corrected. In the second reset operation, the resistance change memory element 43 is an intermittent mode in which the state in which the resistance change memory element 43 satisfies the reset voltage condition and the state in which the resistance change memory element 43 does not meet is repeated every relatively short time of about 10 ns. Do not reset. The intermittent mode is set to the continuous mode, that is, the XWE signal is corrected so that the second reset operation is the same as the first reset operation. After such correction, the simulation is performed again.

  The effects of the invention according to this example are as follows. A storage node indicating a storage state is provided in the subcircuit representing the storage unit, and the subcircuit representing the storage unit operates according to the storage node. Therefore, the state after the operation of the subcircuit representing the storage unit is maintained, and based on the state, the subcircuit representing the storage unit can continuously perform the next operation. This effect is particularly effective when there are many subcircuits representing resistance change memory elements in a simulation in which writing and reading are combined in a complicated manner.

  Further, by introducing a delay element, it is possible to avoid a behavior different from that of the original resistance change memory element that a reset is likely to occur after setting. In addition, parameters such as a reset time, a set voltage, a reset voltage, and a resistance value in a high resistance state or a low resistance state can be freely set by adjusting a resistance value, a capacitance value, or the like in the subcircuit. Here, a continuous time that satisfies the reset voltage condition is applied to the reset time.

  As described above, since the analog simulation of the storage device using the storage unit including the resistance change memory element can be continuously performed, the resistance change memory simulation device including the storage unit described above, which can easily perform the simulation of the memory circuit, and the resistance change A memory simulation method and a circuit design support method can be provided.

(Fourth embodiment)
The fourth embodiment relates to a circuit design support apparatus used for the circuit design support method for the resistance change memory according to the first to third embodiments.

  FIG. 33 is a diagram for explaining a circuit design support apparatus. This device is a circuit design support device that supports circuit design of a storage device using a storage unit including a resistance change memory element. The circuit design support apparatus reliably executes the flowchart shown in FIG.

The circuit design support apparatus includes a simulation unit 106, a change unit 107, an operation confirmation unit 108, and an input / output unit 109.
In the circuit design support apparatus, the simulation of the resistance change memory circuit is performed by the simulation unit 106. Specifically, the simulation unit 106 receives data from the library 100, the subcircuit 101 representing the storage unit, the netlist 102, the initial setting voltage 103, and the expected voltage 104 from the input / output unit 109, and configures a storage device. The time change of the voltage of the connection node between circuit components is obtained.

  Here, in the subcircuit 101 representing the storage unit, one of the connection nodes (for example, the storage node rin) connecting the circuit components constituting the subcircuit holds a voltage corresponding to the storage state of the storage unit. This is the data of the subcircuit that is the storage node.

The net list 102 is net list data in which connection relationships between circuit components constituting the storage device are described. For example, the net list shown in FIG. 11 corresponds.
Then, the operation check unit 108 compares the expected value data with the voltage of the connection node, and outputs the comparison result. Specifically, data from the expected voltage 104 is received from the input / output unit 109, and the flowchart of FIG. 8 is executed. Further, the operation confirmation unit 108 includes a result of comparing the expected value at the specified time with each node voltage, a determination result of whether the comparison between the node voltage and the expected voltage matches, a changed netlist or element attribute, and the like. The result is output as the result 105 via the output unit 109.

  Further, the change unit 107 changes the net list or the element attribute. Specifically, the netlist received from the netlist 102 and the library 100 via the input / output unit 109 is changed or the element attribute is changed.

  The circuit design support device is realized together with appropriate hardware resources such as a workstation. Further, parts other than hardware resources of the circuit design support device can be distributed via a magnetic medium, an optical medium, an electric signal, or an optical signal.

According to such a circuit design support apparatus, there is an effect that the circuit design support methods of the first to third embodiments can be easily performed.
(Supplementary note 1) In a simulation apparatus for verifying the operation of a resistance change memory element,
A first power supply node held at a first potential;
A first resistor connected to the first power supply node;
A second power supply node connected in series to the first resistor via a second resistor and held at a second potential;
A storage node located between the first resistor and the second resistor;
A capacitor connected in parallel with the second resistor between the storage node and the second power supply node;
The resistance value of the first resistor and the resistance value of the second resistor are changed by a voltage applied to a variable resistor provided in the simulation device, and the potential of the storage node is changed to the first power supply node or the A simulation device controlled by any potential of a second power supply node.

(Supplementary note 2) The simulation apparatus according to supplementary note 1, wherein a resistance value of the variable resistance unit is controlled by a potential of the storage node.
(Additional remark 3) In the said variable resistance part,
A third resistance representing a high resistance state;
A fourth resistance representing a low resistance state;
A fifth resistor connected to the third resistor;
A sixth resistor connected to the fourth resistor;
The simulation apparatus according to claim 1 or 2, wherein a resistance value of the fifth resistor and a resistance value of the sixth resistor are controlled by a potential of the storage node.

  (Supplementary note 4) The supplementary notes 1 to 3, wherein the resistance value of the first resistor and the resistance value of the second resistor are controlled by a voltage obtained by delaying a voltage applied to the variable resistance unit. The simulation device according to any one of the above.

  (Supplementary Note 5) In the case where the resistance value of the first resistor and the resistance value of the second resistor are changed by a voltage obtained by delaying the voltage applied to the variable resistor unit, the simulation apparatus may A delay potential generator, wherein the first delay potential generator delays and outputs the voltage applied to both ends of the variable resistor, and the resistance values of the first resistor and the second resistor are the first resistance The simulation apparatus according to any one of appendices 1 to 4, wherein the simulation apparatus changes according to a potential output from the delayed potential generation unit.

  (Additional remark 6) The simulation apparatus as described in any one of additional remark 1 thru | or 3 with which the resistance value of the said variable resistance part changes with the electric potential which delayed the electric potential of the said storage node.

  (Supplementary Note 7) In the case where the resistance values of the fifth resistor and the sixth resistor change depending on the potential obtained by delaying the potential of the storage node, the simulation apparatus includes a second delayed potential generation unit, The second delay potential generation unit delays and outputs the potential of the storage node, and the resistance values of the fifth resistor and the sixth resistor change according to the output of the second delay potential generation unit. The simulation apparatus according to any one of Supplementary Notes 1, 2, 3, and 6, characterized by:

  (Supplementary Note 8) A seventh resistor and an eighth resistor are connected in series between the storage node and the second power supply node, and a resistance value of the seventh resistor is a voltage applied to the variable resistance unit. The simulation apparatus according to any one of appendices 1 to 7, wherein the resistance value of the eighth resistor changes according to the potential of the storage node.

(Supplementary Note 9) One resistance of the first resistance or the second resistance is obtained when a voltage applied to both ends of the variable resistance portion is equal to or higher than a third potential and equal to or lower than a fourth potential. When the voltage applied to both ends of the variable resistance portion is a potential other than the first resistance value, the second resistance value is obtained.
The other resistor has a third resistance value when the voltage applied to both ends of the variable resistance portion is equal to or higher than the fourth potential, and the voltage applied to both ends of the variable resistance portion is a potential other than that. The simulation apparatus according to any one of appendices 1 to 8, wherein the fourth resistance value is a fourth resistance value.

(Supplementary Note 10) One of the fifth resistor and the sixth resistor has a fifth resistance value when the potential of the storage node is equal to or higher than the fifth potential, and the potential of the storage node is When the potential is 5 or less, the sixth resistance value is obtained.
The other resistor has a seventh resistance value when the potential of the storage node is equal to or lower than the fifth potential, and an eighth resistance value when the potential of the storage node is equal to or higher than the fifth potential. The simulation apparatus according to any one of appendices 1 to 9, characterized by:

(Supplementary Note 11) The resistance value of the seventh resistor is the ninth resistance value when the voltage applied to both ends of the variable resistor portion is equal to or lower than the third potential, and is applied to both ends of the variable resistor portion. When the voltage to be applied is equal to or higher than the third potential, the tenth resistance value is obtained.
The resistance value of the eighth resistor is the eleventh resistance value when the potential of the storage node is equal to or higher than the fifth potential, and the twelfth resistance value when the potential of the storage node is equal to or lower than the fifth potential. The simulation device according to any one of appendices 1 to 10, wherein the simulation device has a resistance value.

  (Supplementary note 12) Any one of Supplementary notes 1 to 11, wherein the first resistance value is lower than the second resistance value, and the third resistance value is lower than the fourth resistance value. The simulation apparatus according to item.

(Supplementary Note 13) The resistance value of the third resistor is higher than the resistance value of the fourth resistor, and one of the fifth resistance value and the sixth resistance value is the resistance value of the third resistor. The other of the fifth resistance value and the sixth resistance value is one digit higher than the resistance value of the fourth resistor,
One of the seventh resistance value and the eighth resistance value is one digit lower than the resistance value of the third resistor, and the other is one digit higher than the resistance value of the fourth resistor. The simulation apparatus according to any one of appendices 1 to 12.

  (Supplementary Note 14) A product of the first resistance value and the capacitance of the capacitor is a first time constant, and a product of the third resistance value and the capacitor is a second time constant. When the given delay time is a first delay time, the first delay time is longer than the second time constant, and the first time constant is longer than the first delay time. The simulation apparatus according to any one of appendices 1 to 13.

(Supplementary Note 15) When the value of the constant is log _e ((the first potential−the second potential) / (the fifth potential−the second potential)), the resistance change memory element The first resistance value and the capacitance value of the capacitor are determined so that the time required for reset is (the first time constant) × (the constant) + (the delay time). The simulation apparatus according to any one of appendices 1 to 14.

(Supplementary note 16) The simulation device according to supplementary note 11, wherein the ninth resistance value is lower than the tenth resistance value.
(Supplementary note 17) The simulation device according to any one of supplementary notes 1 to 16, wherein a resistance value of the third resistor changes depending on a voltage applied to itself or to both ends of the variable resistance unit. .

(Additional remark 18) The simulation apparatus as described in any one of additional remark 1 thru | or 17 with which the capacitor showing parasitic capacitance is provided in the said variable resistance part.
(Supplementary note 19) inputting a sub-circuit including a node that outputs a storage state of the resistance change memory element;
Inputting a connection relationship between circuit components constituting the storage device;
Inputting a voltage condition between the circuit components;
Obtaining a voltage change between the circuit components in the voltage condition;
A circuit design support method characterized by comprising:

(Supplementary note 20) A circuit design support method for supporting circuit design of a storage device using a storage unit including a resistance change memory element using an analog simulator,
One of the connection nodes for connecting circuit components constituting the subcircuit is to input the subcircuit including a node that holds a voltage corresponding to the storage state of the storage unit to the analog simulator;
Inputting to the analog simulator a netlist describing a connection relationship between circuit components constituting the storage device;
Performing an analog simulation to obtain a time change in voltage of the connection node between the circuit components constituting the storage device;
A circuit design support method characterized by comprising:

(Additional remark 21) The step which inputs the expected value of the voltage of the connection node between the said circuit components which comprise the said memory | storage device,
Compare the voltage of the connection node between the circuit components that constitute the storage device and the expected value of the voltage of the connection node between the circuit components that constitute the storage device, obtained by the analog simulator, and output the comparison result And steps to
Determining whether the operation of the storage device is operating normally from the comparison result;
The circuit design support method according to appendix 20, characterized by comprising:

  (Supplementary note 22) The supplementary note 20 or 21, further comprising a step of supporting a change of the netlist or a change of an element attribute of a circuit component when the operation of the storage device is not operating normally. Circuit design support method.

(Supplementary Note 23) A circuit design support device for supporting circuit design of a storage device using a storage unit including a resistance change memory element,
One of the connection nodes for connecting the circuit components constituting the subcircuit is data of the subcircuit having a node for holding a voltage corresponding to the storage state of the storage unit, between the circuit components constituting the storage device An input / output unit that receives netlist data and expected value data in which connection relations of
A simulation unit that performs an analog simulation using the data of the subcircuit and the data of the netlist, and obtains a time change of a voltage of a connection node between circuit components constituting the storage device;
An operation check unit that compares the expected value data with the voltage of the connection node and outputs a comparison result;
Based on the comparison result, a change unit that performs a netlist change or element attribute change,
Circuit design support device with

It is a circuit diagram showing the contents of the subcircuit equivalent to a resistance change memory element (the 1). It is a circuit diagram equivalent to a resistance change memory element (the 1). FIG. 6 is a diagram for explaining a change in potential of a storage node rin when resetting (part 1); It is a figure explaining an example of the IV curve of a high resistance element. It is the figure explaining the role and function of the element which comprises a resistance change memory element (the 1). It is a figure explaining the basic composition of a delay potential generating part. It is a figure explaining the basic composition of the variable resistance part which inserted the capacitor. It is a flowchart explaining the method of supporting design of a resistance change memory circuit. It is a flowchart figure explaining the simulation step of a resistance change memory circuit in detail. It is a figure explaining the attribute of an element and an element. It is a figure which shows an example of the circuit which a net list | wrist represents. It is a figure showing the list of a net list. It is a figure which shows the example of the initial setting value input into an analog simulator. It is a figure which shows the time dependence table produced by an analog simulator. It is a flowchart figure shown about the detail of the support step of operation verification. It is a figure which shows an expected value table. It is a figure which shows the comparison table of the voltage of the node obtained by performing an expected value and simulation. It is a flowchart figure which shows the detail of the assistance step of a circuit change or an element attribute change. It is the figure which showed the operation mode in each time on a simulator. It is a wave form diagram of the signal given as XWE, CL1, CPL1, WL, and PRC (the 1). It is a figure explaining the electric potential of each node obtained as a simulation result (the 1). It is a figure explaining the electric potential of each node obtained as a simulation result (the 2). FIG. 10 is a circuit diagram showing the contents of a sub-circuit corresponding to the resistance change memory element (No. 2). It is the figure explaining the role and function of the element which comprises a resistance change memory element (the 2). It is a circuit diagram equivalent to a resistance change memory element (the 2). FIG. 10 is a circuit diagram showing the contents of a sub-circuit corresponding to the resistance change memory element (No. 3). It is the figure explaining the role and function of the element which comprises a resistance change memory element (the 3). It is a circuit diagram equivalent to a resistance change memory element (the 3). FIG. 6 is a diagram for explaining a change in potential of a storage node when resetting (part 2); It is a figure explaining the waveform of the signal given as XWE, CL1, CPL1, WL, and PRC (the 2). FIG. 6 is a diagram for explaining the potential of each node obtained as a simulation result (part 3); FIG. 6 is a diagram for explaining the potential of each node obtained as a simulation result (part 4); It is a figure explaining a circuit design support apparatus. It is a figure explaining the general voltage-current characteristic of a unipolar resistance change memory element.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Variable resistance part 20 Memory | storage part 30,60,70 Delay potential generation part 31,61,71 Delay element 32 Voltage dependent voltage source 35,50,51,52,53,54, bl, gl, dtmo, drin node 40 Many Function pMOS
41a-41p nMOS
42a-42p pMOS
43 Resistance change memory element 44 Selection transistor 45, 46 Amplifying inverter 47, 48 Precharge control transistor 49 Bit line parasitic capacitance 100 Library 101 Subcircuit representing storage unit 102 Netlist 103 Initial setting voltage 104 Expected voltage 105 Result 106 Simulation unit 107 change unit 108 operation check unit 109 input / output unit C15, C24, C34 capacitor R11 high resistance element R12 low resistance element R13, R14, R21, R23, R25, R26, R33 resistance element R22 resetter load resistance element rin storage node SW13, SW14 switch SW21 resetter switch SW23 setter switch SW25, SW26 pullback switch vddr high potential power node vssr low potential power node

Claims (5)

In a simulation apparatus for verifying the operation of a resistance change memory element,
A first power supply node held at a first potential;
A first resistor connected to the first power supply node;
A second power supply node connected in series to the first resistor via a second resistor and held at a second potential;
A storage node located between the first resistor and the second resistor;
A capacitor connected in parallel with the second resistor between the storage node and the second power supply node;
The resistance value of the first resistor and the resistance value of the second resistor are changed by a voltage applied to a variable resistor provided in the simulation device, and the potential of the storage node is changed to the first power supply node or the A simulation device controlled by any potential of a second power supply node.   The simulation apparatus according to claim 1, wherein a resistance value of the variable resistance unit is controlled by a potential of the storage node. 3. The simulation apparatus according to claim 1, wherein the resistance value of the first resistor and the resistance value of the second resistor are controlled by a voltage obtained by delaying a voltage applied to the variable resistance unit. .   4. The simulation apparatus according to claim 1, wherein a resistance value of the variable resistance unit changes according to a potential obtained by delaying a potential of the storage node. 5. One of the first resistor and the second resistor is a first resistor when a voltage applied to both ends of the variable resistance portion is equal to or higher than a third potential and equal to or lower than a fourth potential. When the voltage applied to both ends of the variable resistance portion is a potential other than that, the second resistance value is obtained.
The other resistor has a third resistance value when the voltage applied to both ends of the variable resistance portion is equal to or higher than the fourth potential, and the voltage applied to both ends of the variable resistance portion is a potential other than that. The simulation apparatus according to claim 1, wherein the fourth resistance value is a fourth resistance value.

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