JP4747261B2 - Method of manufacturing reverse blocking insulated gate bipolar transistor - Google Patents

Description

The present invention relates to an insulated gate bipolar transistor (IGBT) used in a power converter and the like. More specifically, the present invention relates to a method for manufacturing a bidirectional IGBT device or a reverse blocking IGBT device having bidirectional withstand voltage characteristics.

  An IGBT (insulated gate bipolar transistor) having a conventional planar type pn junction structure as shown in FIG. 5 is used under a direct current power source in an inverter circuit and a chopper circuit which are main applications. There was no problem as long as the withstand voltage could be secured, and it was made without considering the reverse withstand voltage from the element design stage.

  However, recently, in a semiconductor power converter, in order to perform AC (alternating current) / AC conversion, AC / DC (direct current) conversion, and DC / AC conversion, a bidirectional switching element is used for a matrix converter such as a direct link type conversion circuit. By using, research has been conducted to reduce the size, weight, efficiency, speed, and cost of circuits. Therefore, in order to obtain the bidirectional switching element by connecting the reverse breakdown voltage IGBT in reverse parallel, an IGBT having a reverse breakdown voltage has been demanded.

  As described above, the conventional IGBT does not employ an element design and manufacturing method for ensuring effective reverse blocking capability. Therefore, in order to ensure reverse withstand voltage, a diode is connected in series to secure a conversion device. Must be configured. As a result, the generated loss including the diode increases, leading to a decrease in conversion efficiency of the conversion device. Furthermore, the number of elements increases, making it difficult to reduce the size, weight, and cost of the conversion device. In these respects, the existence significance of the IGBT having the reverse blocking ability arises.

  FIG. 5 is a cross-sectional view of a main part of a conventional IGBT that does not substantially have the above-described reverse breakdown voltage. The IGBT will be described. A plurality of p base regions 102 are selectively formed on the first main surface 115 of the high resistivity n-type semiconductor substrate, and a p collector layer 103 is formed on the second main surface 116 on the back surface side. Yes. A region sandwiched between the p base region 102 and the p collector layer 103 in the thickness direction of the semiconductor substrate is an n base region 101 which is also a semiconductor substrate. An n emitter region 104 is selectively formed in a surface layer in the p base region 102 in the active region 114 indicated by an arrow. A guard ring structure 113, which is a kind of breakdown voltage structure of the planar pn junction surface indicated by an arrow, is formed outside the active region 114, and the forward blocking breakdown voltage of the IGBT is ensured. A dotted line 118 indicates the n base side depletion layer when a forward voltage is applied. The guard ring structure 113 includes a p region 111, an oxide film 112, a metal film 124, and the like formed in a ring shape on the surface layer of the n-type semiconductor substrate outside the active region 114 in the first main surface. Made in combination. Gate electrodes 106 are respectively formed on the surface of the p base region 102 sandwiched between the n emitter region 104 and the n base region 101 and the surface of the n base region 101 between the plurality of p base regions 102 via the gate oxide film 105. It is formed. The surface of the n emitter region 104 is covered with an emitter electrode 108, and the surface of the p collector layer 103 is covered with a collector electrode 109. An insulating film 107 is provided between the emitter electrode 108 and the gate electrode 106.

  Since the above-described conventional IGBT is manufactured on the assumption that it is not reverse-biased, the collector indicated by the symbol A (FIG. 5) where the electric field tends to concentrate when a reverse bias is applied with the emitter as the ground potential and the collector as the negative potential. In the vicinity of the bonding surface, no processing is performed by the cutting portion 125 that is still provided with mechanical cutting distortion due to dicing or the like, and of course, a sufficient reverse breakdown voltage cannot be obtained.

  On the other hand, a reverse blocking type such as the mesa type reverse blocking IGBT 200 shown in FIG. 7 is also known. The IGBT includes a mesa groove 201 that exposes the surface of a pn junction 119 formed between the p collector layer 103 and the n base 101, and a passivation film 202 that protects the mesa groove. The mesa groove is formed by etching or the like from the first main surface side. If the depletion layer 117 spreading before and after the pn junction 119 does not spread in the dicing portion (cutting portion) 125 and its damaged region in reverse bias, sufficient reverse breakdown voltage can be obtained.

However, in order to form the IGBT 200 having this mesa-type groove, an epitaxial wafer having a thick collector layer 103 is required to reduce crack defects, so that the turn-off loss becomes large, and between the on-voltage characteristic and the turn-off loss. However, it is difficult to avoid the trade-off (see Patent Documents 1 and 2 below).

  Furthermore, in the case of the separation layer type reverse blocking IGBT 300 in which the separation layer 120 as shown in FIG. 6 is formed only by diffusion from the surface (the other functional regions are the same as those of the IGBT shown in FIG. The reference numeral 117 indicates a reverse bias depletion layer added to the pn junction between the p collector layer 103 and the n base layer 101. An NPT (Non Punch Through) wafer (100 μm) is used. Can do. In this case, by reducing the collector layer 103 and controlling the impurity concentration to be low, the trade-off relationship between the on-voltage characteristic and the turn-off loss, which has been a problem in the past, can be eliminated and both can be reduced.

  However, with respect to the formation of the separation layer, even a thin NPT wafer having a substrate thickness of about 100 μm as in the reverse blocking IGBT 300 shown in FIG. 6 is about 120 μm (reverse blocking breakdown voltage 600 V) due to boron diffusion from the surface. In order to make a separation layer 120 having a depth of 100 μm in the case of a device wafer, the separation layer width (in the direction parallel to the surface) starts thermal diffusion from an initial region of 50 μm on one side (per one side) In the lateral direction (direction parallel to the surface), the initial region is expanded by about 100 μm, so that the separation layer per chip is as large as 150 μm on one side. When both sides are combined, it becomes 300 μm. This greatly reduces the area of the active region and increases the chip area for the same current capacity, which not only results in poor chip area utilization efficiency but also is disadvantageous in terms of cost. When the thickness of the wafer (substrate) is 150 μm, the separation region 120 further expands in the horizontal direction, so that the utilization efficiency of the chip area is further deteriorated and the diffusion time becomes extremely long, which is not practical. (See Patent Documents 1 and 2 below).

JP 2001-185727 A JP 2002-319676 A

As described above, the mesa type reverse blocking IGBT has a problem that the on- voltage and the turn-off loss are in a trade-off relationship. In the case of the separation layer type reverse blocking IGBT in which the separation layer is formed only by diffusion from the surface, There is a problem that not only the use efficiency of the chip area is bad but also the cost is disadvantageous.

  The present invention has been made in view of these problems, and an object of the present invention is to be a problem even in the case of a thin wafer (semiconductor substrate) of 150 μm or less that can avoid a trade-off between on-voltage characteristics and turn-off loss. It is an object of the present invention to provide a reverse blocking insulated gate bipolar transistor that can reduce the occupied area ratio of the isolation region per chip and shorten the diffusion time, and a manufacturing method thereof.

According to the first aspect of the present invention, after forming the trench groove having a depth deeper than the width on the first main surface side of the first conductivity type semiconductor substrate, the second conductivity type from the surface of the trench groove is formed. A step of forming an isolation region by impurity diffusion, a step of filling the trench groove with polysilicon, planarizing the surface of the polysilicon, and removing polysilicon other than in the trench groove; and A step of forming a MOS gate structure including a base region, an emitter region, a gate insulating film and a gate electrode on the first main surface, a step of reducing the thickness of the substrate from the second main surface side, and the isolation region exposed. This is achieved by the reverse blocking insulated gate bipolar transistor manufacturing method in which the step of forming the second conductivity type collector layer on the second main surface is performed in this order.

According to the present invention, even in the case of a thin wafer (semiconductor substrate) of 150 μm or less that can avoid the trade-off between the on-voltage characteristics and the turn-off loss, it is possible to reduce the occupied area ratio of the isolation region per chip, which is a problem. It can provide a method of manufacturing a reverse blocking insulated gate bipolar transitional scan data that attained shorten the diffusion time.

Schematic sectional view of a reverse blocking insulated gate bipolar transistor according to the present invention Different schematic cross-sectional views of a reverse blocking insulated gate bipolar transistor according to the present invention Process sectional drawing which shows the manufacturing method of reverse prevention IGBT concerning this invention Process sectional drawing which shows the post process of FIG. 3 about the manufacturing method of reverse blocking IGBT concerning this invention Schematic sectional view of a conventional insulated gate bipolar transistor Schematic cross section of a conventional reverse blocking insulated gate bipolar transistor Different schematic cross-sectional views of a conventional reverse blocking insulated gate bipolar transistor Different schematic cross-sectional views of a reverse blocking insulated gate bipolar transistor according to the present invention Different schematic cross-sectional views of a reverse blocking insulated gate bipolar transistor according to the present invention

  1, 2, 8, and 9 are cross-sectional views of a reverse blocking insulated gate bipolar transistor (hereinafter abbreviated as IGBT) according to the present invention. FIGS. 3 and 4 show the IGBT shown in FIG. It is the manufacturing process figure which showed the manufacturing method by the cross section of the principal part of a silicon substrate. As long as the gist of the present invention is not exceeded, the present invention is not limited to the description of the examples described below.

Embodiments of the reverse blocking IGBT and its manufacturing method according to the present invention will be described in detail with reference to FIG. 1, FIG. 3, and FIG. This reverse blocking IGBT is a reverse blocking IGBT having a withstand voltage of 600V. An initial oxide film 12 having a thickness of 1.6 μm is formed on the surface of an FZ silicon substrate (wafer) 1 having a thickness of 525 μm and an n-conductivity type impurity concentration of 1.5 × 10 ¹⁴ cm ⁻³ , which corresponds to an isolation region on the outer periphery of the chip The oxide film 12 is patterned on the part to form a ring-shaped or lattice-shaped opening with a width of 5 μm (FIG. 3A).

Using the patterned oxide film as a mask, a trench groove 23 having a width of 5 μm and a depth of 50 μm is formed in the opening by anisotropic etching such as RIE etching using HBr, NF ₃ , or O ₂ gas (FIG. 3). (B)). A boron source 33 is applied to the substrate surface (FIG. 3C), and heat treatment is performed at 1300 ° C. for 96 hours to form a separation layer 32 having a depth of 120 μm (FIG. 3D). Next, the boron glass 34 formed by the diffusion is etched. After removing the boron glass 34 (FIG. 3E), the etch groove 23 is filled with polysilicon 35 (FIG. 3F). Thereafter, the surface of the polysilicon 35 is flattened to remove the polysilicon 35 other than the grooves (FIG. 4A). Next, a MOS gate structure such as a P base region, a gate oxide film, a gate electrode, an N + emitter region, and an emitter electrode is formed by the same process as the planar IGBT structure described in FIG. 5 (FIG. 4B). Since the formation method of this MOS gate structure is the same as that of FIG. 6, it is omitted to avoid redundant description. For this reason, the same reference numerals are used in FIG. Next, the back surface (second main surface) of the silicon substrate 1 is shaved to the chain line 22 shown in FIG. 4C, and the silicon substrate is reduced to a thickness of about 100 μm (FIG. 4C). Next, boron having a dose of 1 × 10 ¹³ cm ⁻² is ion-implanted into the back surface (second main surface) from which the separation layer 32 is exposed, and is activated by performing low-temperature annealing at about 350 ° C. for about 1 hour. A back collector layer having a boron peak concentration of about 1 × 10 ¹⁷ cm ⁻³ and a thickness of about 1 μm is formed (FIG. 4D). Finally, when the wafer 1 is cut by dicing at the position of the chain line 21 (FIG. 4E), a reverse blocking IGBT as shown in FIG. 1 is formed. In FIG. 1, dicing is performed between adjacent separation regions. However, this is a problem of patterning of the separation regions. If a lattice-like separation region pattern is used as shown in FIG. 4E, dicing is performed at the center in the separation region. You can also According to the manufacturing method according to the present invention described above, since the boron diffuses from the bottom of the trench groove 23 in the thickness direction of the silicon substrate, the diffusion time in the depth direction can be shortened. As the diffusion time is shortened, the lateral diffusion spread also decreases, so the width of one side of the separation layer per chip is about 60 μm, which is less than half that of the conventional reverse blocking IGBT using diffusion from the surface. Can do.

  FIG. 2 is a reverse blocking insulated gate bipolar transistor (IGBT) having a trench type isolation layer according to the present invention, and is a cross-sectional view of the main part of an embodiment different from the manufacturing method of FIG. Similar to the IGBT of the first embodiment described with reference to FIGS. 1, 3, and 4, a trench groove 23 having a depth of 50 μm is formed on the outer periphery of the chip, and an oxide film 22 is newly formed only on the sidewall of the groove. Then, the separation layer 31 is formed mainly by diffusing boron from the bottom of the groove without the oxide film. An effect equal to or better than that described above can be obtained. That is, in this case, since the diffusion of the wafer in the lateral direction (direction parallel to the main surface) from the side surface of the groove is almost eliminated, the width of the separation layer 31 can be further reduced.

In Examples 1 and 2 and FIGS. 1, 2, 3 and 4, the coating diffusion is performed using a boron source. However, if the coating is changed to boron ion implantation, the ion implantation tends to be almost only at the groove bottom. Therefore, the lateral diffusion can be reduced without forming the oxide film 22 on the sidewall of the groove as in the case of FIG. In this case, the dose of boron was 1 × 10 ¹⁶ cm ⁻² and the acceleration voltage was 100 kev. The thermal diffusion after the ion implantation is performed after the trench is filled with the polysilicon 35 after the ion implantation, and after the isolation diffusion, the polysilicon 35 on the silicon substrate other than the trench is removed to flatten the substrate surface. Was made. Subsequent steps may be the same as those in the case of boron coating diffusion described with reference to FIGS.

  Further, the step of planarizing the trench groove shown in FIGS. 3 (f) and 4 (a) performed when manufacturing the reverse blocking insulated gate bipolar transistor (IGBT) of the first and second embodiments is omitted. It is also preferable. In this case, the process of dividing the silicon substrate to form an IGBT chip is not obtained by dicing, but is obtained by dividing the thin silicon substrate at the bottom of the trench groove 23 by opening the wall with an external force. There is a profit that becomes unnecessary. A cross-sectional view of the IGBT chip in this case is shown in FIG. In the figure, the same reference numerals as those in FIG.

As an example of ion implantation when the trench is not flattened, if the acceleration voltage is 100 keV, the dose is 1 × 10 ¹⁶ cm ⁻² , and the annealing time is 1440 minutes, the diffusion depth is 40 μm. If the trench groove depth is 90 μm, the collector region and the isolation region are connected when the silicon substrate thickness is 120 μm by back grinding.

  In Example 3, after forming the depth of the trench groove shallower than the aforementioned 140 μm so as to be about 50 μm to 90 μm from the front surface side, the silicon substrate is similarly ground until the thickness becomes 120 μm from the back surface, and the trench groove is formed. You may manufacture so that it may not penetrate the back. In the third embodiment, in any trench depth, unlike the first embodiment, it is necessary not to provide a step of filling the trench groove with polysilicon and flattening. In this way, the silicon substrate is not divided into chips as described above at the stage after the back surface grinding, so that it is easy to form the collector region and the collector electrode on the back surface side. In this case, since the silicon substrate at the bottom of the trench groove can be divided by opening the walls, the dicing process can be omitted.

Similar to Example 1, in order to manufacture a reverse blocking IGBT having a withstand voltage of 600 V, a thickness of 525 μm on the surface of an FZ silicon substrate (wafer) 1 having an n-conductivity type impurity concentration of 1.5 × 10 ¹⁴ cm ⁻³ is formed. An initial oxide film 12 having a thickness of 1.6 μm is formed, and the oxide film 12 is patterned in a portion corresponding to the separation region on the outer periphery of the chip to form a grid-like opening having a width of 5 μm. A trench groove having an opening width of 5 μm and a depth of 140 μm deeper than that of the first embodiment is formed by anisotropic etching similar to that of the first embodiment.

  Next, as in the first embodiment, a p-type isolation region having boron as an impurity around the trench groove, and a p base region, a gate oxide film, a gate electrode, and an n emitter on the silicon substrate surface surrounded by the p-type isolation region Regions and emitter electrodes are formed. After applying the protective tape on the front surface side, the silicon substrate is shaved from the back surface to a thickness of about 120 μm.

Since the depth of the trench groove is 140 μm, the trench groove penetrates the silicon substrate and is divided into semiconductor chips at this stage, but is in a state of being held by being adhered to the protective tape on the surface side. In this state, boron with a dose of 1 × 10 ¹³ cm ⁻² is ion-implanted into the back side of the silicon substrate, and low-temperature annealing is performed at 350 ° C. for about 1 hour, and the peak concentration of activated boron is 1 × 10 ¹⁷ cm. A back collector layer having a thickness of about ⁻³ and a thickness of about 1 μm is formed. After forming the collector electrode, a tape is applied to the entire back surface, the front surface tape is peeled off (reverse blocking IGBT), and the chip is taken out. A cross-sectional view of the IGBT chip in this case is shown in FIG. In the figure, the same reference numerals as those in FIG.

  According to this manufacturing method, there is no need for dicing to divide into chips, and there is no chipping defect due to dicing, and the cutting width of dicing itself is eliminated, so that the area of the active region is increased accordingly. Can do.

In the first to fourth embodiments described above, the case of boron diffusion and ion implantation before the formation of the surface-side MOS gate structure has been described for the separation diffusion. However, before the formation of the metal electrode of the MOS gate structure, the separation is performed. Diffusion may be performed. As another diffusion method, it is used as diffusion using solid, gas, liquid, or the like as a source. BN can be used as the solid source, BBr ₃ can be used as the gas source, and B ₂ H ₆ can be used as the liquid source. However, when the surface of the silicon substrate is planarized in the above three diffusion methods, unlike the case of ion implantation, polysilicon is buried after diffusion.

1 n base layer (semiconductor substrate)
12 Oxide film 23 Trench groove 31, 32 isolation region 35 Polysilicon 102 p base region
103 p + collector layer 104 n + emitter region 105 gate oxide film
106 Gate electrode 108 Emitter electrode
109 Collector electrode 133 Boron source 134 Boron glass.

Claims (1)

A step of forming an isolation region by diffusion of a second conductivity type impurity from the surface of the trench groove after forming a trench groove deeper than the width on the first main surface side of the first conductivity type semiconductor substrate; and Filling with polysilicon, planarizing the surface of the polysilicon, removing polysilicon other than in the trench groove, and a base region, an emitter region, and a gate insulating film on the first main surface surrounded by the isolation region A step of forming a MOS gate structure including a gate electrode, a step of reducing the thickness of the substrate from the second main surface side, and a step of forming a second conductivity type collector layer on the second main surface exposing the isolation region And a reverse blocking type insulated gate bipolar transistor manufacturing method, wherein: