JP4749383B2 - Encoding device, encryption device, and program - Google Patents

Description

  The present invention relates to an encoding device that performs block-type error correction encoding on information data using a register and a coefficient data storage unit, an encryption device that performs encryption, and a program that causes a computer to function as these devices. is there.

  For example, in the conventional encoding device disclosed in Patent Document 1, when multiplying each term in the Reed-Solomon code generator polynomial, the multiplier performs multiplication in symbol units of the Reed-Solomon code, and the adder uses the bit. Add in units. In addition, the conventional encoding device disclosed in Patent Document 2 distributes input information to be encoded to a plurality of encoders with a switch when performing encoding by interleaving.

JP-A-9-33162 JP 2002-27464 A

  The conventional encoding device includes processing that cannot efficiently use the CPU in encoding, and requires dedicated hardware. For example, in the encoding device of Patent Document 1, since the CPU shifts the shift register in the adder operation to move the data, the CPU can efficiently perform the arithmetic operation of the register that can perform the register operation by shifting every plural bits. Not available.

  Furthermore, the encoding device of Patent Document 1 requires a multiplier and an adder as dedicated hardware in order to calculate a Reed-Solomon code check symbol. Also in the encoding device of Patent Document 2, it is necessary to provide a plurality of encoders in order to perform interleaving processing, or the upper limit of the interleave value is fixed depending on the number of encoders.

  Further, the conventional encoding device does not have a function of interrupting and resuming the encoding process, and it is necessary to encode and transmit data within a time during which communication with the data transmission destination is possible. For example, in a data handling system mounted on an artificial satellite orbiting the earth, it is necessary to return response data immediately upon receiving a control command from the ground station, and the response data and observation data are encoded simultaneously. You may have to. In this case, in a data handling system to which a conventional encoding device is applied, after receiving a control signal from the ground station, if the artificial satellite becomes hidden from the ground and becomes invisible from the ground station side, the data transmission destination ground station and Communication is interrupted, and the encoding process according to the control signal cannot be performed.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to obtain an encoding device, an encryption device, and a program that allows a computer to function as these devices, which can efficiently use the computing power of a CPU. To do.

  The present invention also provides an encoding device that can change the interleave value without increasing the number of encoders, can interrupt and restart encoding as appropriate, and a program that causes a computer to function as this device. With the goal.

An encoding apparatus according to the present invention includes a calculation data storage unit that stores coefficient data for encoding calculation of information symbols, a plurality of registers each having a bit width that is an integral multiple of the number of bits of the information symbols, A data input unit that inputs a series of information symbols to be converted into a plurality of registers, a data output unit that outputs data from the registers, and a coefficient of the data storage unit for calculation based on the data output from the register by the data output unit Of the data, a designation unit for specifying coefficient data used for encoding information symbols stored in a plurality of registers, and encoding of information symbols stored in a plurality of registers using the coefficient data specified by the specification unit It performs calculation, a calculation section for obtaining encoded data of the information symbols, and a counter for counting the number of operations by the arithmetic unit, the counter A processing progress storage unit for storing the number of operations and the operation result being recorded in each register when interrupting the encoding process in the number of operations counted by the The number of operations stored in the progress storage unit and the intermediate result of the operation recorded when the encoding process is interrupted are used .

According to the present invention, a calculation data storage unit that stores coefficient data for encoding calculation of information symbols, a plurality of registers each having a bit width that is an integral multiple of the number of bits of information symbols, and a series of codes to be encoded A data input unit that inputs information symbols to a plurality of registers, a data output unit that outputs data from the registers, and coefficient data in the arithmetic data storage unit based on the data output from the register by the data output unit A designation unit for specifying coefficient data used for encoding information symbols stored in a plurality of registers, and a coding operation for information symbols stored in the plurality of registers using the coefficient data specified by the specification unit an arithmetic unit for obtaining encoded data of the information symbols, and a counter for counting the number of operations by the arithmetic unit, mosquitoes by the counter unit A processing progress storage unit for storing the number of computations and the computation results recorded in each register when the encoding process is interrupted. Since the number of operations stored in the storage unit and the result of the operation recorded when the encoding process is interrupted are used , a plurality of information symbols can be encoded together in the register, and the CPU's computing power can be used efficiently There is an effect that encoding that can be performed can be realized.

Embodiment 1 FIG.
FIG. 1 is a diagram showing a configuration of an encoding apparatus according to Embodiment 1 of the present invention, and shows a case where it is applied to a data handling system mounted on an artificial satellite. 1, the encoding apparatus according to Embodiment 1 includes shift registers 1a to 1d, a data output unit 2, an exclusive OR calculator (arithmetic unit) 3, an address designation unit (designation unit) 4, and a coefficient table storage unit. (Calculation data storage unit) 6, reception unit 7, data collection unit 8, data input unit 9, information data storage unit (data storage unit) 10, processing progress data storage unit (processing progress storage unit) 12, and counter unit 14 Is provided. The shift registers 1a to 1d are registers having the same number of bits as the register width of the CPU of the computer functioning as the encoding device according to the first embodiment. In the example of FIG. 1, it is assumed that the register width of the CPU is 64 bits, and the register widths of the shift registers 1a to 1d are each 64 bits.

  The data output unit 2 outputs information symbols for one symbol (one processing unit) input from the register 1 d to the address designating unit 4. Here, it is assumed that 8 bits (1 byte) is one processing unit. The exclusive OR calculator 3 calculates the exclusive OR of the coefficient data 5 extracted from the coefficient table storage unit 6 to the registers 1a to 1d and the respective values of the registers 1a to 1d, and stores them in the registers 1a to 1d. Store. The address designating unit 4 uses four 64-bit coefficients for Reed-Solomon encoding that are output from the coefficient table storage unit 6 to the registers 1a to 1d based on the address value derived from the information symbol input from the data output unit 2. Specify data 5.

The coefficient data 5 is a product of a numerical value obtained by converting all elements of a vector representation of a Galois field GF (2 ⁸ ) based on 8-bit (one processing unit) digital data into an exponential representation and a Galois field constant of the exponential representation. This is data in the form of vector representation. For example, a primitive root alpha ⁱ was exponential representation of the Galois field GF (2 ⁸⁾ (i = 0 to 254), a value obtained by exponential expressed as a primitive root of constant coefficients G ₀ ~G ₃₁ a Galois field GF (2 ⁸⁾ Find the product of Values B _{0 to} B ₃₁ obtained by converting the integration result α ^{k (i)} (i = 0 to 31) into a binary representation of 1 byte (one processing unit) are associated with the shift registers 1a to 1d and B ₀ to B ₇ , B _{8 to} B ₁₅ , B _{16 to} B ₂₃ , and B _{24 to} B ₃₁ are connected to each other, whereby the coefficient data 5 is converted into four 8-byte data K ₁ , K ₂ , K ₃ , K You can say ₄ .

The coefficient table storage unit 6 stores the coefficient data 5 as a table associated with each predetermined address value. Here, when the coefficient data 5 designates 8-bit data m corresponding to any value of the primitive root α ⁱ expressed exponentially in the Galois field GF (2 ⁸ ), four 8-bytes corresponding to the data m are designated. Data K ₁ (m), K ₂ (m), K ₃ (m), and K ₄ (m) can be obtained. In the coefficient table storage unit 6, an address value corresponding to the data m is set in the storage area for all 8-bit data (256 pieces), and K ₁ (m), K is stored in the storage area specified by this address value. ₂ (m), K ₃ (m), K ₄ (m) are stored. That is, a coefficient data table is constructed in which the coefficient data 5 can be searched at the address corresponding to the data m. The address value may be a result obtained by performing predetermined arithmetic processing on an 8-bit information symbol, but 8-bit data m corresponding to the information symbol is directly used as K ₁ (m), K ₂ ( m), K ₃ (m), and K ₄ (m) may be used as address values.

  The receiving unit 7 is a communication processing unit of a data handling system that performs communication with the ground station. The receiving unit 7 receives response commands transmitted from the ground station by radio waves and includes response data CLCW (Command Link Control Word). (4 information symbols) is generated. The data collection unit 8 is a communication processing unit of a data handling system that communicates with an observation device group mounted on an artificial satellite. The data collection unit 8 collects observation data from the observation device group and stores it in the information data storage unit 10 with 8 bits. Saved as unit information symbol 11. The data input unit 9 stores the information symbol 11 in the first 8 bits of the 64-bit register 1a. The information data storage unit 10 stores the observation data collected by the data collection unit 8 as information symbols 11.

  When the Reed-Solomon encoding process is interrupted, the process progress data storage unit 12 stores the values stored in the registers 1a to 1d as interrupt data 13a to 13d, respectively, and counts the loop process in the Reed-Solomon encoding process. The value is stored as count data 15. The counter unit 14 counts the number of loop processes in the Reed-Solomon encoding process, that is, the number of calculations performed by the exclusive OR calculator 3, and outputs the count value to the process progress data storage unit 12.

  The data output unit 2, the exclusive OR calculator 3, the address specifying unit 4, the receiving unit 7, the data collecting unit 8, the data input unit 9 and the counter unit 14 described above are encoded programs according to the spirit of the present invention. By reading into a computer having four 64-bit registers corresponding to the registers 1a to 1d and controlling its operation, it can be realized as a specific means in which software and hardware cooperate on the computer. . The coefficient table storage unit 6, the information data storage unit 10, and the process progress data storage unit 12 are constructed on a general-purpose memory mounted on the computer.

  Note that the configuration of the computer itself and its basic functions can be easily recognized by those skilled in the art based on the common general technical knowledge in the technical field, and are not directly related to the essence of the present invention, so detailed description thereof is omitted. To do.

Next, the operation will be described.
2 and 3 are flowcharts showing the flow of the encoding process by the encoding device in FIG. 1. After the data handling system to which this encoding device is applied receives the control signal from the ground station, the artificial satellite The process when it becomes invisible from the ground station side is shown. In the following, the (255, 223) code recommended by CCSDS (Consultative Committee for Space Data System Standards) is assumed as the Reed-Solomon code. The (255, 223) code has an information symbol part of 223 bytes and a redundant part of 32 bytes.

  First, the data collection unit 8 collects observation data from the observation device group of artificial satellites, and stores it in the information data storage unit 10 as information symbols 11 in units of 8 bits. The data input unit 9 takes out the information symbol 11 from the information data storage unit 10 (step ST1).

  Thereafter, the CPU of the encoding apparatus according to the first embodiment outputs the last 8 bits of information symbols in the register 1d to the data output unit 2 (step ST2), and the contents of the register 1d for one information symbol (8 bits). Shift right logically (step ST3). Subsequently, the CPU adds the last 8 bits of the information symbol in the register 1c to the first 8 bits of the register 1d (step ST4), and right-shifts the contents of the register 1c by one information symbol (8 bits) (step ST4). ST5).

  Next, the CPU adds the last 8 bits of information symbols in the register 1b to the first 8 bits of the register 1c (step ST6), and right-shifts the contents of the register 1b by one information symbol (8 bits) (step ST6). ST7). Thereafter, the CPU adds the last 8 bits of the information symbol in the register 1a to the first 8 bits of the register 1b (step ST8), and right-shifts the contents of the register 1a by one information symbol (8 bits) (step ST8). ST9).

  The data input unit 9 adds the information symbol 11 extracted from the information data storage unit 10 to the first 8 bits of the register 1a (step ST10). On the other hand, the data output unit 2 outputs digital data for one information symbol input from the register 1 d to the address specifying unit 4. The address designating unit 4 performs a predetermined operation on the digital data for one information symbol input from the data output unit 2 to calculate an address value. For example, the address value of the coefficient data 5 may be obtained by adding an offset address value that is a base address value of the coefficient table storage unit 6 to the digital data itself for one information symbol input from the data output unit 2.

  The address specifying unit 4 searches the coefficient table storage unit 6 based on the address value corresponding to the information symbol obtained as described above, and performs Reed-Solomon encoding from the stored data in the coefficient table storage unit 6. Four 64-bit coefficient data 5 are designated (step ST11). The four coefficient data 5 designated by the address designating unit 4 are taken out to the registers 1a to 1d, respectively. The exclusive OR calculator 3 calculates the exclusive OR of the coefficient data 5 extracted from the coefficient table storage unit 6 to the registers 1a to 1d and the respective values of the registers 1a to 1d, and stores them in the registers 1a to 1d. Store (step ST12).

  When the processing up to step ST12 is completed, the counter unit 14 increments the count value by 1 (step ST13). Thereafter, the CPU determines whether or not the number of loop processes counted by the counter unit 14 (the number of operations by the exclusive OR calculator 3) has reached 219 (step ST14). At this time, if the number of times of the loop processing is not 219, the processing returns to step ST1 and the above processing is repeated for the next information symbol 11.

  On the other hand, if the number of loop processes is 219, the CPU stores the contents of the registers 1a to 1d as the interrupt data 13a to 13d in the process progress data storage unit 12 (step ST15). As a result, 219-byte information symbols excluding the four information symbols of the response data CLCW among the 223-byte information symbols to be encoded in the (255, 223) code are encoded. Further, the counter unit 14 stores the count value as the count data 15 in the process progress data storage unit 12 (step ST16).

  Next, the CPU determines whether or not the satellite on which the device is mounted is visible from the ground station side (step ST17). For example, it is determined whether or not the receiving unit 7 is visible depending on whether or not the communication with the ground station is established. Here, if it is not visible time, it returns to the process of step ST16, and the count value of the counter part 14 is stored in the process progress data storage part 12 as the count data 15. FIG.

  If it is determined in step ST17 that it is the visible time, the receiving unit 7 receives a command transmitted by radio waves from the ground station, and generates response data CLCW (4 information symbols) including the command number (step ST18). ). Next, the CPU returns the interruption data 13a to 13d stored in the processing progress data storage unit 12 during the invisible time to the registers 1a to 1d, respectively, and returns the count data 15 to the counter unit 14 (step ST19).

  The receiving unit 7 extracts one of the four information symbols of the response data CLCW generated in step ST18 and sets it in the data input unit 9 (step ST20), and repeats the processing from step ST2 to step ST13 described above ( Step ST21). Here, when the processing of step ST21 is completed for one of the four information symbols of the response data CLCW, the CPU determines whether or not all four information symbols of the response data CLCW have been processed (step ST22). At this time, if all the information symbols have not been processed, the process returns to step ST20 and shifts to a process for the next information symbol of the response data CLCW.

  When processing of all four information symbols of the response data CLCW is completed, the contents of the registers 1a to 1d at this point are Reed-Solomon code check symbols (step ST23). The data output unit 2 inputs the check symbol of the Reed-Solomon code from the registers 1a to 1d and outputs it as an encoding result.

  As described above, according to the first embodiment, the coefficient table storage unit 6 that stores the coefficient data 5 for the encoding operation of the information symbol 11 and the bit width that is an integral multiple of the number of bits of the information symbol 11 are respectively set. Registers 1a to 1d, a data input unit 9 for inputting a series of information symbols 11 to be encoded to the registers 1a to 1d, a data output unit 2 for outputting data from the register 1d, and a data output unit 2 for register 1d. Address specifying unit 4 for specifying coefficient data 5 used for encoding information symbol 11 stored in registers 1a to 1d among coefficient data 5 of coefficient table storage unit 6 based on the data output from An exclusive OR operation is performed on the coefficient data 5 designated by the designation unit 4 and the information symbol 11 stored in the registers 1a to 1d, and the information is obtained. Since the exclusive OR calculator 3 for obtaining the encoded data of the symbol 11 is provided, since 8 information symbols are stored in one register, the exclusive OR operation can be performed simultaneously for 8 information symbols. The computing power can be used efficiently.

In addition, the following effects can be obtained by applying the encoding apparatus according to the first embodiment to a data handling system mounted on an artificial satellite.
As described above, in a data handling system mounted on an artificial satellite to which a conventional encoding device is applied, if the artificial satellite is hidden in the shadow of the earth, it becomes invisible from the ground station side and receives a telecommand to generate response data CLCW Accordingly, it becomes impossible to transmit telemetry data and response data CLCW relating to observation data by the observation device in the satellite to the ground station.

  On the other hand, in the data handling system to which the encoding apparatus according to the first embodiment is applied, telemetry data excluding the response data CLCW (4 information symbols) can be encoded in invisible time, and the visible time is reached. It is only necessary to encode the response data CLCW. That is, of the 223 information symbols to be encoded, 219 information symbols excluding the 4 information symbols constituting the response data CLCW are encoded in an invisible time and are on standby. As a result, the number of symbols to be encoded in the visible time only needs to be four information symbols of the response data CLCW, and the burden of the encoding process performed in the visible time can be greatly reduced.

  In the first embodiment, an example in which 64-bit registers 1a to 1d are used has been described. However, a register that can store all check symbols and has a size that is an integral multiple of the number of bits of an information symbol is used. It may be a configuration. Thus, the number of operations can be reduced as the register can store more information symbols.

  Furthermore, in Embodiment 1 described above, the number of encoding processing operations is 219, and the arithmetic processing is interrupted in order to wait for a state in which the satellite and the ground station can communicate with each other. When the CPU is desired to be used for processing other than encoding processing, the encoding processing is performed by storing the contents of the registers 1a to 1d and the number of operations of the counter unit 14 in the processing progress data storage unit 12. After interrupting and causing the CPU to perform processing other than encoding processing, the contents of the registers 1a to 1d and the count data 15 are returned from the processing progress data storage unit 12 to each register and counter unit 14 again. It is possible to resume processing.

Embodiment 2. FIG.
In the first embodiment, an example of the operation for extracting a series of information symbols 11 from the information data storage unit 10 to the data input unit 9 has been described. However, in the second embodiment, the information symbols 11 are extracted to the data input unit 9. The interleaving function is realized by changing the way.

  The basic configuration of the coding apparatus according to the second embodiment is the same as that shown in FIG. 1 described in the first embodiment, but the operation for extracting information symbols from the information data storage unit 10 differs depending on the data input unit 9. . FIG. 4 is a diagram for explaining an information symbol extraction operation according to Embodiment 2 of the present invention. As shown in FIG. 4, in the second embodiment, the data input unit 9 stores one of the series of information symbols stored in the information data storage unit 10 from the first information symbol 11-1. The information symbol group 11A composed of the information symbols 11-3, 11-5, 11-7, and 11-9 taken out is extracted, and the encoding process shown in FIGS. 2 and 3 in the first embodiment is executed. To do.

  When the encoding of the information symbol group 11A is completed, the data input unit 9 starts from the remaining information symbols 11-2, 11-4, 11-6, 11-8, and 11-10 in the series of information symbols. The information symbol group B is extracted from the information data storage unit 10 and the encoding process shown in FIGS. 2 and 3 in the first embodiment is executed. By doing so, an encoding process with an interleave value of 2 can be performed.

  In addition, among the series of information symbols stored in the information data storage unit 10, by reading information symbols stored in N skips and performing encoding processing alternately, encoding processing of the interleave value N + 1 is possible. is there.

  As described above, according to the second embodiment, the data input unit 9 includes the information symbol groups 11A and 11B composed of a series of information symbols 11 to be encoded stored in the information data storage unit 10. Since the information symbols 11 arranged in a predetermined order such as one skip are selectively extracted and input to the registers 1a to 1d, an interleave function with a variable interleave value can be realized without increasing the number of encoders. it can.

Embodiment 3 FIG.
In the first embodiment, the telemetry data encoding process in the artificial satellite data handling system is taken as an example. In the third embodiment, an encryption unit is configured by adding an encryption unit to the encoding device shown in the first embodiment, and an encryption process that efficiently uses the computing capability of the CPU is possible. .

  FIG. 5 is a diagram showing a configuration of an encryption apparatus according to Embodiment 3 of the present invention. Hereinafter, a case will be described in which this encryption apparatus is applied to a monitoring control system that exchanges encrypted data using TCP / IP. In this monitoring control system, the monitoring device and the base station are connected via a network, and the encryption device in FIG. 5 is mounted on the monitoring device. In the encryption device, the monitoring data acquired by the monitoring device is encrypted including response confirmation data for the base station, and the encrypted data is transmitted to the base station via the network.

  As shown in FIG. 5, the encryption apparatus according to the first embodiment includes an encryption unit 16 in addition to the configuration of FIG. 1 shown in the first embodiment. The receiving unit 7 in this encryption apparatus has an interface that handles TCP / IP, and receives data from the base station via the network. The data collection unit 8 stores monitoring data acquired by a monitoring device (not shown) (for example, a monitoring camera) mounted on the monitoring device as the information symbol 11 in the information data storage unit 10.

  The coefficient table storage unit 6 stores encryption data instead of the coefficient data 5. 5 returns the coefficient data 5 (table data) to the coefficient table storage unit 6, and the address designating unit 4 designates the coefficient data 5 in the coefficient table storage unit 6 so that the above-described implementation is performed. It is also possible to function as the encoding device shown in the first embodiment or the second embodiment.

  The encryption unit 16 performs an encryption process according to a predetermined encryption algorithm. Here, it is assumed that the CTR mode is executed as the encryption mode. In the CTR mode, the data obtained by encrypting the data in which the nonce, which is constant data set with a different value for each communication with the base station, and the count data are encrypted is used as encryption data.

  In the encryption apparatus in FIG. 5, encryption data combined with the count data 15 of the counter unit 14 is generated, and the coefficient table storage unit 6 encrypts the data as table data associated with the count data 15 of the counter unit 14. Stores data for conversion. Since the other components operate in the same manner as those shown in FIG. 1, duplicate descriptions are omitted.

  The data output unit 2, the exclusive OR calculator 3, the address specifying unit 4, the receiving unit 7, the data collecting unit 8, the data input unit 9, the counter unit 14, and the encryption unit 16 are encrypted programs according to the spirit of the present invention. , By reading into a computer having four 64-bit registers corresponding to the registers 1a to 1d and controlling its operation, it can be realized as a specific means in which software and hardware cooperate on the computer. it can. The coefficient table storage unit 6, the information data storage unit 10, and the process progress data storage unit 12 are constructed on a general-purpose memory mounted on the computer.

  Note that the configuration of the computer itself and its basic functions can be easily recognized by those skilled in the art based on the common general technical knowledge in the technical field, and are not directly related to the essence of the present invention, so detailed description thereof is omitted. To do.

Next, the operation will be described.
The encryption device in FIG. 5 executes encryption processing according to the following procedure.
(1) Procedure 1
First, the data collection unit 8 collects monitoring data from the monitoring device group of the monitoring device, and stores it in the information data storage unit 10 as information symbols 11 in units of 8 bits. The data input unit 9 takes out the information symbol 11 from the information data storage unit 10 and takes it into the registers 1a to 1d by shifting as in the first embodiment.

  For example, as in the first embodiment, the CPU of the encryption device according to the third embodiment outputs the information symbol set in the register 1d to the data output unit 2, and right-shifts all the values in the register 1c. And set in the register 1d. Further, all the values of the register 1b are logically shifted to the right and set to the register 1c, and all the values of the register 1a are logically shifted to the right and set to the register 1b. Thereafter, the data input unit 9 sets a series of eight information symbols 11 extracted from the information data storage unit 10 in the register 1a.

(2) Procedure 2
Next, the encryption unit 16 generates a nonce for communication with the current base station, acquires the count data from the count unit 14, and creates a 64-bit plaintext block that combines the nonce and the count data. Here, it is assumed that the encryption unit 16 generates a plaintext block in hexadecimal notation in which nonce is set in the upper 4 bytes of 64 bits and count data is set in the lower 4 bytes. For example, “661F98CD00000001” is generated. . Since the lower 4 bytes “00000001” is the count data from the counter unit 14, it is counted up each time the counter unit 14 counts.

(3) Procedure 3
The encryption unit 16 encrypts the 64-bit plaintext block generated in the procedure 2 using a DES (Data Encryption Standard) or triple-DES encryption algorithm, and generates 64-bit encryption data K.
(4) Procedure 4
The encryption unit 16 stores the encryption data K generated in step 3 in the coefficient table storage unit 6.
(5) Procedure 5
The exclusive OR calculator 3 calculates the exclusive OR of the encryption data K read from the coefficient table storage unit 6 and the value of the register 1d, and stores it in the register 1d.

(6) Procedure 6
The CPU outputs all the values of the register 1d obtained by the exclusive OR operation with the encryption data K in the procedure 5 to the data output unit 2, and moves all the values of the register 1c to the register 1d. Further, all values in the register 1b are moved to the register 1c, and all values in the register 1a are moved to the register 1b. Thereafter, the data input unit 9 sets a series of eight information symbols 11 extracted from the information data storage unit 10 in the register 1a. As a result, new data is set in the register 1a.

(7) Procedure 7
When step 6 is completed, the counter unit 14 increments the value of the count data by 1, and outputs the count data to the encryption unit 16. The encryption unit 16 encrypts a plaintext block that is a combination of the count data and the nonce to obtain encryption data. For example, the plaintext block “661F98CD00000002” in which the count data is counted up is encrypted. Thereafter, the information symbols 11 are encrypted by repeating steps 3 to 7.

  As described above, according to the third embodiment, the encryption unit 16 that calculates the encryption data K of the information symbol 11 and the coefficient table storage unit that stores the encryption data K calculated by the encryption unit 16. 6, registers 1 a to 1 d each having a bit width that is an integral multiple of the number of bits of the information symbol 11, a data input unit 9 for inputting a series of information symbols 11 to be encrypted to the registers 1 a to 1 d, and coefficient table storage An exclusive OR operation unit 3 that performs an exclusive OR operation on the encryption data K extracted from the unit 6 and the information symbol 11 stored in the register 1d, and obtains encrypted data of the information symbol 11. Since it is provided, a plurality of information symbols can be collectively encrypted in the register, and encryption that can efficiently use the calculation capability of the CPU can be realized.

  In the third embodiment, the encryption unit 16 performs encryption according to the DES or triple DES encryption algorithm. However, an AES (Rijndael) encryption algorithm may be used. Specifically, in step 2, the encryption unit 16 generates a 128-bit plaintext block with 8 bytes of nonce and 8 bytes of count data, and encrypts it to generate 128-bit encryption data. To do. Here, the encryption unit 16 divides the 128 encryption data into 64-bit data K1 and K2, and stores them in the coefficient table storage unit 6.

  Thereafter, in step 5, the exclusive OR calculator 3 calculates the exclusive OR of the encryption data K1 read from the coefficient table storage unit 6 and the value of the register 1c and stores it in the register 1c. Then, an exclusive OR of the encryption data K2 and the value of the register 1d is calculated and stored in the register 1d.

  In step 6, the CPU outputs all the values of the registers 1c and 1d obtained by the exclusive OR operation in step 5 to the data output unit 2 by two data shifts. That is, all the values of the register 1b are moved to the register 1c, all the values of the register 1c are moved to the register 1d, and all the values of the register 1a are moved to the register 1b. Subsequently, the entire value of the register 1b is moved to the register 1c, and the entire value of the register 1a is moved to the register 1b. Thereafter, the data input unit 9 sets eight information symbols 11 taken out from the information data storage unit 10 as new data in the register 1a.

  When step 6 is completed, the counter unit 14 increments the value of the count data by 1, and outputs the count data to the encryption unit 16. The encryption unit 16 generates a plaintext block that combines the count data and the nonce. Thereafter, the information symbols 11 are encrypted by repeating steps 3 to 7. By doing in this way, the encryption apparatus according to Embodiment 3 can also realize encryption according to a 128-bit encryption algorithm.

It is a figure which shows the structure of the encoding apparatus by Embodiment 1 of this invention. It is a flowchart which shows the flow of the encoding process by the encoding apparatus in FIG. It is a flowchart which shows the flow of the encoding process by the encoding apparatus in FIG. It is a figure for demonstrating the information symbol extraction operation | movement by Embodiment 2 of this invention. It is a figure which shows the structure of the encryption apparatus by Embodiment 3 of this invention.

Explanation of symbols

  1a to 1d register, 2 data output unit, 3 exclusive OR calculator (operation unit), 4 address designation unit (designation unit), 5 coefficient data, 6 coefficient table storage unit (operation data storage unit), 7 reception , 8 data collection unit, 9 data input unit, 10 information data storage unit (data storage unit), 11, 11-1 to 11-10 information symbol, 11A, 11B information symbol group, 12 processing progress data storage unit (processing Progress storage unit), 13a to 13d interruption data, 14 counter unit, 15 count data, 16 encryption unit.

Claims (6)

A calculation data storage unit for storing coefficient data for encoding calculation of information symbols;
A plurality of registers each having a bit width that is an integral multiple of the number of bits of the information symbol;
A data input unit for inputting a series of information symbols to be encoded to the plurality of registers;
A data output unit for outputting data from the register;
A designation unit for designating coefficient data used for encoding information symbols stored in the plurality of registers, among coefficient data in the calculation data storage unit, based on data output from the register by the data output unit When,
An arithmetic unit that performs encoding calculation of information symbols stored in the plurality of registers using the coefficient data specified by the specifying unit, and obtains encoded data of the information symbols ;
A counter unit that counts the number of operations by the operation unit;
A processing progress storage unit that stores the number of operations and the result of the operation being recorded in each register when the encoding process is interrupted in the number of operations counted by the counter unit;
With
An encoding apparatus characterized by using the number of operations stored in the process progress storage unit and the intermediate result of an operation recorded when the encoding process is interrupted when restarting the encoding process. The arithmetic data storage unit takes the product of the numerical value obtained by converting all elements of the Galois field vector representation based on the digital data of one information symbol unit into the exponential representation and the exponential Galois field constant, and expresses this as a vector representation Stored as coefficient data,
The designating unit obtains information symbols stored in a plurality of registers based on the data output from the registers by the data output unit, and regards the information symbols as the vector representation of the Galois field, and the calculation data storage unit Is used to specify coefficient data used for encoding information symbols stored in the plurality of registers,
2. The encoding apparatus according to claim 1, wherein the arithmetic unit performs an exclusive OR operation on the information symbols stored in the plurality of registers and the coefficient data specified by the specifying unit.   3. The encoding apparatus according to claim 2, wherein the designating unit designates coefficient data expressed in a Galois field vector by a bit string that matches a register width of each register.   4. A data collection unit for collecting data from outside the apparatus, and a data storage unit for storing data collected by the data collection unit as information symbols. The encoding device according to claim 1.   The data input unit selectively extracts information symbols arranged in a predetermined order from the information symbol group composed of a series of information symbols to be encoded stored in the data storage unit, and inputs the information symbols to the register The encoding device according to any one of claims 1 to 4. An encryption part for calculating data for encrypting information symbols;
A calculation data storage unit for storing encryption data calculated by the encryption unit;
A plurality of registers each having a bit width that is an integral multiple of the number of bits of the information symbol;
A data input unit for inputting a series of information symbols to be encrypted to the plurality of registers;
Using the encryption data extracted from the calculation data storage unit, the calculation unit performs encryption calculation of the information symbol stored in the register, and obtains encrypted data of the information symbol ;
A counter unit that counts the number of operations by the operation unit;
With
The encryption unit encrypts block data that combines a digital value corresponding to a nonce and a count value of the counter unit to calculate encryption data,
The encryption unit, wherein the calculation unit performs encryption calculation of information symbols stored in a register, using encryption data extracted from the calculation data storage unit based on the count value .

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