JP4760541B2 - Buffer control module, image processing apparatus, and program - Google Patents

Description

  The present invention relates to a technique for performing image processing by dividing image data to be processed into a plurality of bands.

Among image processing apparatuses such as copiers and printers, there are page processing methods that collectively read and process image data for one page, and blocks each page of image data in a plurality of lines in the sub-scanning direction. There is a band processing system (for example, refer to Patent Document 1) that divides the data into bands (hereinafter referred to as “bands”) and reads and processes them in units of bands (see, for example, Patent Document 1), and is implemented to store image data that is the object of image processing. The latter has become the mainstream because of the advantage of requiring less memory.
Japanese Patent Laid-Open No. 11-112873

  By the way, image processing apparatuses such as copiers and printer apparatuses have dedicated modules that execute processing for each processing such as color conversion processing, enlargement / reduction processing, and rotation processing on an image to be processed. In general, image processing is realized by operating the modules in a predetermined order. Hereinafter, the combination of the modules is also referred to as a “pipeline”.

  In the above pipeline, a window base for determining processing contents to be applied to a pixel located at the center of a window composed of, for example, 3 × 3 pixels in accordance with the pixel values of eight pixels located in the vicinity thereof as in the filter processing. If the module for executing the process is included, the number of effective pixels may be reduced after the process is executed (hereinafter referred to as degeneration of the effective pixels). In the image processing apparatus of the page processing method, as shown in FIG. 9A, the effective pixels are degenerated only in the outermost outline of the page (in FIG. 9A, the degenerate pixels are hatched. The same applies to (b)). However, in the image processing apparatus of the band processing method, as shown in FIG. 9B, degeneration of effective pixels occurs in the outermost contour of each band. In other words, in the band processing type image processing apparatus, the reduction of effective pixels due to window-based processing is more conspicuous than the page processing type image processing apparatus. This is a major problem of the band processing type image processing apparatus. It has become.

  In general, since the number of effective pixels needs to match before and after image processing by a pipeline, various measures for dealing with the degeneration of the effective pixels have been proposed in the past. There are two methods, a batch overlap grant method and a divided overlap grant method.

  The batch overlap assigning method is a method of collectively assigning overlap pixels (pixels that are added considering the degeneracy of effective pixels) necessary for all image processing at the beginning of the pipeline. For example, if the pipeline is composed of a module that performs a filter process with a window size of 7 × 7 and a module that performs a filter process with a window size of 3 × 3, image processing by the pipeline Degeneration of the effective pixels for the outermost four pixels of the image data to be processed (image data for one page or one band) occurs. Therefore, in the collective overlap providing method, an overlap of 4 pixels is given to the outside of the image data, 7 × 7 filter processing is performed as shown in FIG. 10A, and then FIG. 3 × 3 filter processing is performed as shown in FIG. In FIGS. 10A and 10B, the image data that is the original processing target is indicated by hatching (the same applies to FIG. 11).

  On the other hand, the divided overlap method is a method in which an overlap pixel corresponding to the number of effective pixels to be degenerated by the process is given immediately before each filter process. Specifically, in the case where the pipeline includes a module that performs a filter process with a window size of 7 × 7 and a module that performs a filter process with a window size of 3 × 3, Immediately before the filter processing, an overlap of 3 pixels is given as shown in FIG. 11A, and an overlap of 1 pixel is given just before the 3 × 3 filter processing as shown in FIG. 11B. Is done.

In FIGS. 11A and 11B, the difference from the overlap applied by the collective overlap applying method is indicated by a dotted line. As is clear from FIGS. 11A and 11B, the divided overlap providing method has a feature that the number of overlaps is smaller than the collective overlap providing method. From this point of view, an increase in the number of pixels input into the pipeline causes a decrease in image processing productivity (for example, the number of paper documents that can be processed per unit time). Can be said to be superior to the split overlap method. However, in the divided overlap addition method, it is necessary to add overlap according to the window size of the filter processing module in the previous stage of each filter processing module, so the address when reading the image data to be processed from the band buffer There is a problem that the control becomes complicated.
The present invention has been made in view of the above problems, and can easily apply an overlap image and does not cause a decrease in productivity even when image processing is performed in band units. An object of the present invention is to provide an overlap pixel providing technique.

  In order to solve the above-described problem, the buffer control module according to the first aspect of the present invention includes a write control unit that divides image data for one page into a plurality of bands and writes the data to a different band buffer for each band; Read control means for reading image data for one band from any of the buffers and outputting the image data to a pipeline including a plurality of image processing modules for executing different image processing, wherein the read control means When the plurality of image processing modules include a plurality of modules for performing window processing, the number corresponding to the number of effective pixels to be reduced in the module having the largest window size among the plurality of window processing modules It is characterized in that it is supplied to the pipeline with an overlap of.

  In order to solve the above problem, an image processing apparatus according to a second aspect of the present invention includes a plurality of band buffers and a plurality of image processing modules that execute different image processing, and the plurality of images. A pipeline including a plurality of modules for performing window processing in a processing module, a writing control for dividing image data for one page into a plurality of bands and writing to different band buffers for each band, and any of the band buffers A buffer control module that reads out image data for one band and outputs the image data to the pipeline, and a buffer control module for supplying the image data to the pipeline. The largest window size among the plurality of modules performing the window processing. Is characterized by supplying to impart several overlap in accordance with the number of effective pixels degenerate in module having.

  In order to solve the above-described problem, a program according to the third aspect of the present invention is a program for controlling a computer device to divide image data for one page into a plurality of bands and write the data into different band buffers for each band. And reading the image data for one band from any one of the band buffers, and functioning as a read control means for outputting the image data to a pipeline including a plurality of image processing modules each performing different image processing, When the plurality of image processing modules include a plurality of modules for performing window processing, the control means sets the effective pixel number to be reduced by the module having the largest window size among the plurality of window processing modules. To supply the pipeline with a corresponding number of overlaps. It is a symptom.

  According to the present invention, it is possible to easily apply an overlap image, and there is an effect that productivity is not reduced even when image processing is performed in band units.

Hereinafter, an embodiment in which the present invention is applied to an electrophotographic copying machine will be described with reference to the drawings.
(A: Configuration)
FIG. 1 is a block diagram illustrating a configuration example of an image processing apparatus 10 according to an embodiment of the present invention.
As shown in FIG. 1, the image processing apparatus 10 includes an input unit 110, an ASIC 120, an output unit 130, and a storage unit 140 configured with an SDRAM.
The input unit 110 optically reads an image to be processed and outputs an image signal corresponding to the image, or signal processing for sample-folding the output signal and performing analog / digital conversion to generate image data A circuit (none of which is shown) is included. The input unit 110 delivers the image data generated as described above to the ASIC 120.

  The ASIC 120 performs various image processing such as color conversion processing, enlargement / reduction, and rotation processing on the image data delivered from the input unit 110 using the storage unit 140 as a work area, and outputs the processing results to the output unit 130. To hand over. As shown in FIG. 1, the ASIC 120 includes buffer control units 1210a, 1210b and 1210c, and image processing units 1220a and 1220b. Hereinafter, when it is not necessary to distinguish the three buffer control units from each other, they are referred to as “buffer control unit 1210”. Similarly, the two image processing units are described as “image processing unit 1220” when it is not necessary to distinguish them from each other.

  The image processing unit 1220 performs a filtering process of a predetermined window size on the image data delivered from the buffer control unit 1210 located at the preceding stage, and delivers the filtered data to the buffer control unit 1210 located at the subsequent stage. In the present embodiment, the image processing unit 1220b is an image processing module that performs filter processing with a 3 × 3 window size, and has a configuration as shown in FIG. On the other hand, the image processing unit 1220a is an image processing module that performs filter processing with a 7 × 7 window size.

  As shown in FIG. 1, in the ASIC 120, image processing units 1220a and 1220b that execute different filter processes are arranged in series via a buffer control unit 1210b, and image data delivered from the input unit 110 Is supplied to the image processing unit 1220a via the buffer control unit 1210a, and the image data output from the image processing unit 1220b is supplied to the output unit 130 via the buffer control unit 1210c. That is, in the ASIC 120, a two-stage pipeline is formed by the image processing units 1220a and 1220b. As described above, the image processing apparatus 10 illustrated in FIG. 1 is an image processing apparatus that executes pipeline-type image processing on image data to be processed.

The buffer control unit 1210 divides the image data delivered from the previous stage into a plurality of bands and writes it to the storage unit 140, while reading the image data thus written in band units and delivers it to the module located at the subsequent stage. Is. For example, the buffer control unit 1210a divides the image data for one page delivered from the input unit 110 into three bands as shown in FIG. Image data is read for each band and delivered to the image processing unit 1220a. The buffer control unit 1210b writes the image data transferred from the image processing unit 1220a in units of bands to the storage unit 140, and reads out the image data thus written in units of bands and transfers it to the image processing unit 1220b. The buffer control unit 1210c writes the image data transferred from the image processing unit 1220b in band units to the storage unit 140, and reads the image data written in this way in band units and transfers it to the output unit 130. The buffer control unit 1210 is constituted by a CPU, a ROM, a RAM, and the like. A control program for causing the CPU to execute control of writing image data to the storage unit 140 and reading control of the image data is stored in the ROM in advance. Has been. On the other hand, the RAM stores various variables such as a read counter, a write counter, and a read reset flag used in the execution process of the control program. These variables will be described later in detail.

  In addition, the buffer control unit 1210 adds an overlap pixel and a replication pixel to the image data for one band, which is the processing target of the window processing, in order to cope with the occurrence of the degeneration of effective pixels in the window processing. It also has a function to do. However, the overlap providing process executed by the buffer control unit 1210 is different from the conventional overlap providing process (the above-described collective overlap providing process or divided overlap providing process) in that a certain amount of overlap pixels is always provided. It is a point to give. Note that data indicating the number of overlap pixels of a certain amount is stored in advance in the ROM.

  More specifically, the buffer control unit 1210 is an image processing module having the largest degenerated effective pixel among the plurality of image processing units forming the pipeline (that is, an image processing module that performs window processing with the largest window size). The number of overlap pixels corresponding to the number of pixels to be degenerated is given in (). In the present embodiment, the window size of window processing in the image processing unit 1220a is 7 × 7 (that is, the outermost three pixels are degenerated), and the window size of window processing in the image processing unit 1220b is 3 × 3. (That is, the outermost one pixel is degenerated), the buffer control unit 1210 gives three pixels of overlap pixels. Specifically, when the buffer control unit 1210 reads the image data stored in the second band area shown in FIG. 3B, as shown in FIG. Image data for three lines from the bottom is read as an upper overlap, and image data for three lines from the upper end of the third band area is read as a lower overlap. In the figure, the readout mode of the replication pixel is not shown, but it is only necessary to read out three pixels at both ends in the main scanning direction of the upper overlap, the second band area, and the lower overlap. .

  Here, as apparent from FIG. 4, the number of overlap pixels given by the buffer control unit 1210 according to the present embodiment is a pipeline that performs 7 × 7 and 3 × 3 filter processing in series. As compared with the number of overlap pixels assigned by the collective overlap assigning method, the outermost one pixel is smaller. For this reason, according to the buffer control unit 1210 according to the present embodiment, the decrease in productivity is reduced as compared with the conventional batch overlap method. In addition, according to the buffer control unit 1210 according to the present embodiment, since a certain amount of overlap pixels is always given, the overlap pixels are given by simple address control as compared with the conventional divided overlap grant method. It becomes possible.

Then, the output unit 130 displays an image corresponding to the image data delivered from the ASIC 120 (that is, image data subjected to pipeline-type image processing by each image processing unit in the ASIC 120) on a recording material such as printing paper. Are formed by electrophotography and output. In this embodiment, the case where the output unit 130 forms an image by an electrophotographic method will be described. However, it is needless to say that the image may be formed by another method such as an inkjet method.
The above is the configuration of the image processing apparatus 10.

(B: Operation)
Hereinafter, operations performed by the buffer control unit 1210 will be described with reference to the drawings.
(B-1: Overlapping process)
FIG. 5 is a flowchart showing the flow of the overlap providing process executed by the buffer control unit 1210 according to the control program stored in its own ROM.
As shown in FIG. 5, the buffer control unit 1210 first determines whether or not the upper overlap has been written to the band buffer to be read (step SA100), and the determination result is “No”. While there is, the process of step SA100 is repeatedly executed. Note that the writing control of image data to the band buffer will be described in detail later.

  If the determination result in step SA100 is “Yes”, the buffer control unit 1210 determines whether or not lower overlap writing to the band buffer to be read has been completed (step SA110). While the result is “No”, the process of step SA110 is repeatedly executed.

If the determination result in step SA110 is “Yes”, the buffer control unit 1210 sets a read target area as shown in FIG. 3B, and sets the image data stored in the read target area. Read one pixel at a time (step SA120). Here, setting the read target area means that the start address of the read target area (at the lower limit of the range of values that can be taken by the Read counter, which is a variable that defines the read position when reading image data from the read target area ( That is, the top address of the upper overlap is set, and the end address of the read target area (that is, the end address of the lower overlap) is set as the upper limit.
By setting the read target area and reading the image data from the read target area in this way, as shown in FIG. 4, the image data delivered to the image processing unit 1220 always has a certain amount as shown in FIG. Will be added.

(B-2: Image data writing process)
FIG. 6 is a flowchart showing a flow of a write control process performed when the buffer control unit 1210 writes the image data delivered from the module positioned in the previous stage to the storage unit 140 in accordance with the control program stored in its own ROM. It is.
As shown in FIG. 6, the buffer control unit 1210 first initializes the value of the Read counter (Step SB100), and then initializes the value of the Write counter (Step SB110). Here, the Read counter is a variable indicating a reading position (address) when reading image data from the above-described reading target area (see FIG. 3B), and the Write counter is a band that is a destination of writing image data. This is a variable indicating the write position (address) in the area. To initialize the Read counter is to set the start address of the read target area to the Read counter, and to initialize the Write counter to the start address of the band area that is the write destination to the Write counter. Is to set.

  Next, the buffer control unit 1210 determines whether a write request signal has been received from the image data supply source (for example, the input unit 110 for the buffer control unit 1210) (step SB120), and the determination result is “Yes”. If "," the processing after step SB130 is executed. Conversely, when the determination result in step SB120 is “No”, the buffer control unit 1210 repeatedly executes the process in step SB120 until the determination result becomes “Yes”.

  In step SB130, which is subsequently executed when the determination result in step SB120 is "Yes", the buffer control unit 1210 determines whether or not there is a vacancy in the band area that is the write destination. Specifically, the buffer control unit 1210 determines that there is a space when the value of the write counter is equal to or less than the address value indicating the end of the band area, and conversely, when the address value exceeds the address value. Is determined to be free.

  When the determination result of step SB130 is “Yes” (that is, when it is determined that there is a free band area as the write destination), the buffer control unit 1210 enters the input unit 110 in the area indicated by the Write counter. The image data for one pixel delivered from is written (step SB140), and the value of the write counter is incremented by one pixel (step SB150), and the processing after step SB120 is repeatedly executed.

  On the other hand, when the determination result in step SB130 is “No” (that is, when it is determined that there is no space in the band area as the write destination), the buffer control unit 1210 is stored in the band area. It is determined whether or not the reading of the image data has been completed (step SB160). Specifically, when the value of the Read reset flag is “ON” (that is, 1), the buffer control unit 1210 determines that reading of the image data stored in the band buffer has been completed, On the contrary, when the value of the Read reset flag is “OFF” (that is, 0), it is determined that the reading is not completed.

  Then, when the determination result in step SB160 is “Yes” (that is, when it is determined that the reading has been completed), the buffer control unit 1210 repeatedly executes the processing after step SB110 described above, and reversely On the other hand, if the determination result in step SB160 is “No”, an overflow process is executed (step SB170). Here, the overflow process is a process of transmitting a predetermined overflow signal to the image data supply source (for example, the input unit 110 regarding the buffer control unit 1210a) to the buffer control unit 1210. When the overflow signal is received, the supply source stops supplying the image data to the buffer control unit 1210. It should be noted that the reason for executing the overflow process described above when the determination result in step SB160 is “No” is that if the writing of the image data is continued under such circumstances, the subsequent module performs the image process. This is because there is a possibility that image data that has not been overwritten will be overwritten, and there is a possibility that a desired image processing result will not be obtained.

  The above is the write control processing executed by the buffer control unit 1210. As described above, the flow of the write control process executed by the buffer control unit 1210 is basically the same as the flow of the write control process performed by the conventional buffer control module. This is different from the write control process performed by the conventional buffer control module in that the start address of the read target area, which is characteristic of the present invention, is set as the initial value of the Read counter.

(B-3: Image data reading process)
Next, a reading control process performed by the buffer control unit 1210 according to the control program when reading the image data written to the storage unit 140 by the writing control process will be described with reference to FIG.
FIG. 7 is a flowchart showing the flow of read control processing performed by the buffer control unit 1210.
As shown in FIG. 7, the buffer control unit 1210 determines whether or not a read request signal has been received from the image data supply destination (for example, the image processing unit 1220a for the buffer control unit 1210a) (step SC100). The process of step SC100 is repeatedly executed until the determination result is “Yes”. On the other hand, if the determination result in step SC100 is “Yes”, the buffer controller 1210a has read all the image data from the read target area set as shown in FIG. Is determined (step SC110). Specifically, when the value of the above-mentioned Read counter is equal to or smaller than the last address value of the read target area, the buffer control unit 1210 determines that the reading is not completed, and conversely, the address value Is exceeded, it is determined that reading has been completed.

When the determination result in step SC110 is “Yes” (that is, when it is determined that reading has been completed), the buffer control unit 1210 initializes the value of the Read counter and sets the Read reset flag to 1. (Step SC120), the processes after Step SC100 are repeatedly executed. For example, when the read target area is composed of the second band area and its upper and lower overlaps, the third band area and its upper and lower overlaps are newly set as the read target areas, The value of the Read counter is initialized with the head address of the read target area.
On the other hand, when the determination result in step SC110 is “No” (that is, when it is determined that reading has not been completed), the buffer control unit 1210 determines whether the value of the Read counter is less than the value of the Write counter. It is determined whether or not (step SC130).

  If the determination result in step SC130 is “No”, the buffer control unit 1210 executes an underflow process (step SC140), and repeatedly executes the processes after step SC100. Here, the underflow process is a process of transmitting a predetermined underflow signal to an image data supply destination (for example, the image processing unit 1220a regarding the buffer control unit 1210a). When the underflow signal is received, the supply destination stops execution of image processing. Note that the reason for executing the above-described underflow processing when the determination result of step SC130 is “No” is that writing of the image data to be supplied to the supply destination to the read target area has not been completed. This is because, if image data reading is continued under such circumstances, a desired image processing result may not be obtained in the subsequent module.

  On the other hand, if the determination result in step SC130 is “Yes”, the buffer control unit 1210 reads the image data for one pixel from the area indicated by the Read counter in the band buffer to be read, and supplies the above-mentioned supply destination. (Step SC150), the value of the Read counter is incremented by one pixel (Step SC160), and the processes after Step SC100 are repeatedly executed.

  The read control processing executed by the buffer control unit 1210 has been described above. As described above, the flow of the read control process performed by the buffer control unit 1210 is basically the same as the flow of the read control process performed by the conventional buffer control module. The above-mentioned address value at the end of the read target area is set as the initial value of the read counter, and the upper limit of the value that can be taken by the read counter. This is different from the read control process performed by the conventional buffer control module.

(C: deformation)
Although one embodiment of the present invention has been described above, it is needless to say that the embodiment may be modified as described below.
(1) In the above-described embodiment, the case where the present invention is applied to a copying machine has been described. However, the application target of the present invention is not limited to a copying machine, and may of course be a printer device or a scanner device. good. For example, when the present invention is applied to a printer apparatus, in the configuration shown in FIG. 1, the input unit 110 is a communication interface (for example, a network interface card) for receiving image data transmitted from another computer apparatus. What is necessary is just to comprise. Similarly, when the present invention is applied to the scanner device, the output unit 130 may be configured by the communication interface.

(2) In the above-described embodiment, the case where a pipeline is formed by two image processing units has been described, but it is needless to say that a pipeline may be formed by three or more image processing units. In the above-described embodiment, the case where the pipeline is formed only by the image processing unit that performs window processing has been described. However, a plurality of image processing modules that perform window processing and at least image processing other than window processing are performed. Of course, a pipeline may be formed with one image processing unit.

(3) In the above-described embodiment, a case where a control program for causing the buffer control unit 1210 to execute buffer write control and buffer read control characteristic of the present invention is written in the ROM of the buffer control unit 1210 in advance is described. However, the program may be written and distributed on a computer-readable recording medium, and installed in the nonvolatile memory of the buffer control unit using the recording medium.
In the above-described embodiment, the case where the buffer writing process and the buffer reading process characteristic of the present invention are realized by a software module has been described. However, it is needless to say that the buffer module may be realized by a hardware module. Specifically, the buffer control unit may be configured by combining the buffer write control circuit having the configuration shown in FIG. 8A and the buffer read control circuit having the configuration shown in FIG. .

1 is a block diagram illustrating a configuration example of an image processing apparatus 10 according to an embodiment of the present invention. It is a figure which shows the structural example of the image process part 1220b. It is a figure for demonstrating the utilization aspect of the memory | storage part. It is a figure for demonstrating the overlap provision system which concerns on this invention. It is a flowchart which shows the flow of the overlap provision process which the buffer control part 1210 performs according to a control program. 10 is a flowchart showing a flow of write control processing executed by a buffer control unit 1210. 12 is a flowchart showing a flow of read control processing executed by a buffer control unit 1210. FIG. 3 is a diagram illustrating a configuration example of a hardware module when the buffer write control and the buffer read control according to the present invention are realized by the hardware module. It is a figure for demonstrating degeneracy of the effective pixel in window processing. It is a figure which shows an example of collective overlap provision. It is a figure which shows an example of division | segmentation overlap provision.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Image processing apparatus, 110 ... Input part, 120 ... ASIC, 1210, 1210a, 1210b, 1210c ... Buffer control module, 1220, 1220a, 1220b ... Image processing part, 130 ... Output part, 140 ... Memory | storage part.

Claims (3)

Write control means for dividing image data for one page into a plurality of bands and writing the data into different band buffers for each band;
Read control means for reading image data for one band from any one of the band buffers and outputting the image data to a pipeline including a plurality of image processing modules for executing different image processing,
The read control means includes
If the plurality of image processing modules include a plurality of modules that perform window processing, the number of effective pixels reduced by the module having the largest window size among the plurality of window processing modules A buffer control module characterized by providing an overlap and supplying the pipeline to the pipeline. Multiple band buffers,
A pipeline including a plurality of image processing modules for executing different image processing, and a plurality of modules for performing window processing in the plurality of image processing modules;
Write control that divides image data for one page into a plurality of bands and writes to different band buffers for each band, and reads out image data for one band from one of the band buffers and outputs the image data to the pipeline A buffer control module for performing control, and
The buffer control module includes:
When supplying image data to the pipeline, the number of overlaps corresponding to the number of effective pixels to be degenerated in the module having the largest window size among the plurality of modules performing the window processing is supplied. An image processing apparatus. Computer equipment,
Write control means for dividing image data for one page into a plurality of bands and writing the data into different band buffers for each band;
Read image data for one band from any one of the band buffers, and function as read control means for outputting the image data to a pipeline including a plurality of image processing modules that execute different image processing,
The read control means includes
If the plurality of image processing modules include a plurality of modules that perform window processing, the number of effective pixels reduced by the module having the largest window size among the plurality of window processing modules A program characterized by providing an overlap and supplying to the pipeline.

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