JP4765634B2 - Add-drop optical time division signal insertion method and apparatus - Google Patents

Description

  According to the present invention, in an add-drop optical time division multiplexing communication, an optical time division multiplexed signal (hereinafter sometimes referred to as “inserted signal”) from which an optical signal for one channel is extracted is extracted. The present invention relates to a method for inserting an optical signal different from the optical signal (hereinafter also simply referred to as “insertion signal”), and an apparatus for realizing the method.

  In recent years, with the widespread use of the Internet, there is a demand for the development of a large-capacity and multifunctional optical communication network. One of the methods for realizing a large-capacity optical communication network is an optical time division multiplex communication method. This optical time division multiplex communication method generates optical pulse signals in parallel, multiplexes them on the time axis and transmits them, and separates the multiplexed optical pulse signals on the receiving side, which is the reverse operation of the transmitting side. This is a communication method that adopts a method of returning to the original parallel optical pulse signal. The communication capacity is increased by multiplexing a plurality of channels on the time axis.

  An optical pulse signal is a binary digital signal RZ (transmission signal) obtained by optically modulating an optical pulse train (hereinafter also referred to as an “optical pulse train”) regularly arranged at regular intervals on the time axis. Return to Zero) signal. Hereinafter, the expression “optical pulse signal” is used only when it means a signal generated as an RZ signal. On the other hand, the expression “optical pulse train” is used to indicate the total of optical pulses arranged at regular intervals on the time axis.

  In these optical communication networks, a multi-functional system having an add / drop function and the like is also required. The add-drop function is to extract (drop) and read out only the optical signal of the required channel from the optical signals of multiple channels transmitted through the optical network, and to drop new information into the vacant channel. A function for inserting (adding) an inserted signal.

  An optical time division multiplex transmission system employing an add / drop function is disclosed (for example, see Patent Document 1). A conventional optical time division multiplex transmission system having an add-drop function has not been provided with means for dealing with the following cases. That is, in the conventional apparatus, when a temporal fluctuation occurs in an area on the time axis assigned to a channel that is dropped and vacant (channel on which new information is placed), or in order to place new information There is no means for dealing with a case where the area allocated on the time axis needs to be changed.

  Hereinafter, an area allocated to one optical pulse carrying 1-bit information on the time axis may be referred to as a time slot. An optical time division multiplexed signal is a signal generated by adding optical pulse signals of a plurality of channels by shifting one time slot on the time axis. Accordingly, in an optical time division multiplexed signal multiplexed by N (N is a positive integer) channel, an optical pulse constituting an optical pulse signal of the same channel is arranged every N time slots on the time axis.

  The region on the time axis assigned to the channel is described as follows by taking the above-described optical time division multiplexed signal multiplexed in the channel as an example. For example, the area on the time axis assigned to the first channel is the total of time slots in which the optical pulses constituting the first channel are arranged every N time slots. The same applies to the second channel and below.

For an inserted signal, an optical pulse signal for one channel is extracted from the optical time division multiplexed signal, and all time slots assigned to this channel (that is, areas on the time axis assigned to this channel) are vacant. The optical signal in the state of being inserted is the inserted signal.
JP 2002-319904 A

  When the transmission speed is increased, the time slot assigned to each channel becomes shorter, so it is necessary to determine the time slot for placing new information more accurately. If the time slot is accurately determined and the insertion signal is not inserted at the exact position, the adjacent time slot is affected, and the insertion signal becomes noise of this adjacent channel. Also, when changing the time slot for placing new information, it is necessary to accurately determine the time slot for placing new information.

  Therefore, the time slot for carrying new information is constantly monitored to confirm that the optical pulse carrying the new information is accurately inserted at the position of the time slot corresponding to the channel that is dropped and vacant. A means for this is needed.

  A first object of the present invention is to provide a method for monitoring a position on a time axis at which an optical pulse carrying new information is to be inserted, and an apparatus for realizing the method.

  A second object of the present invention is to provide a method for automatically inserting an optical pulse carrying new information at the position of a time slot corresponding to a channel that is dropped and vacant, and to realize this method. It is in providing the apparatus of.

In order to achieve the above first object, the time slot monitoring method includes the following steps A to D.
(A) Step A for extracting a first clock signal from an inserted signal, which is a signal obtained by extracting an optical signal for one channel from an optical time division multiplexed signal generated by multiplexing.
Of (B) to be inserted signal, a time slot in which the optical signal of one channel is vacant withdrawn, by inserting the insertion signal is a signal carrying a new signal, the step B of generating a main signal
(C) Step C for extracting the second clock signal from the main signal
(D) Compare the phase of the first clock signal and the second clock signal to monitor the amount of deviation on the time axis between the time slot where the inserted signal should be inserted and the time slot where it was actually inserted Step D where the phase difference between the two is converted into an electrical signal to generate a monitor signal.

The time slot monitoring method can be realized by the following time slot monitoring device. The time slot monitor device includes a first clock signal extraction unit, an optical time division inserter, a second clock signal extraction unit, and a mixer. The first clock signal extraction unit extracts a first clock signal from an inserted signal that is a signal obtained by extracting an optical signal for one channel from an optical time division multiplexed signal generated by multiplexing . Optical time division inserter of the insertion signal, the one channel of the time the optical signal is free is withdrawn slot, insert the insertion signal is a signal carrying a new signal to generate a main signal. The second clock signal extraction unit extracts the second clock signal from the main signal. The mixer compares the phase of the first clock signal and the second clock signal in order to monitor the amount of deviation on the time axis between the time slot in which the inserted signal should be inserted and the actually inserted time slot. Then, the phase difference between the two is converted into an electrical signal to generate a monitor signal.

It is preferable that step A described above includes substeps A1 and A2 shown below.
(A1) First branch step for branching the clock extraction optical signal for extracting the first clock signal from the inserted signal (A2) First clock signal extraction step for extracting the first clock signal from the clock extraction optical signal .

Moreover, it is preferable that the above-described step C includes substeps C1 and C2 shown below.
(C1) Second branching step for branching the optical main signal for clock extraction to extract the second clock signal from the main signal (C2) Second clock signal extraction for extracting the second clock signal from the optical main signal for clock extraction Step.

Furthermore, the first path to the position where the first clock signal extraction step is executed via the position where the first branching step is executed and the second branching step to one of the steps A and C Relative to the phase of the first clock signal and the phase of the second clock signal, which is caused by the path length difference from the second path to the position where the second clock signal extraction step is executed via the position where the second clock signal is executed It is preferable to include a phase adjustment step for adjusting a general phase difference .

  It is preferable that the first clock signal extraction unit described above includes the following components. That is, the first branching unit and the first clock signal extractor. In addition, it is preferable that the second clock signal extraction unit described above includes a second branching device and a second clock signal extractor.

  Further, it is preferable that either one of the first clock signal extraction unit and the second clock signal extraction unit includes a phase adjuster.

The first branching device branches the optical signal for clock extraction for extracting the first clock signal from the inserted signal. The first clock signal extractor extracts the first clock signal from the clock extraction optical signal. The second branching device branches the optical main signal for clock extraction for extracting the second clock signal from the main signal. The second clock signal extractor extracts a second clock signal from the optical main signal for clock extraction. The phase adjuster adjusts a relative phase difference between the phase of the first clock signal output from the first clock signal extractor and the phase of the second clock signal output from the second clock signal extractor.

In order to achieve the second object, the optical time division signal insertion method includes the following steps E and F in addition to steps A to D included in the time slot monitoring method described above. .
(E) Step E that removes high-frequency components from the monitor signal and extracts DC components
(F) Step F for adjusting the phase of the insertion signal so that the DC component extracted in step E becomes zero.

  An optical time division signal insertion device that realizes the optical time division signal insertion method further includes a low-pass filter unit and an insertion signal phase adjuster in addition to the above-described time slot monitor device. The low-pass filter unit removes high-frequency components from the monitor signal and extracts DC components. The insertion signal phase adjuster adjusts the phase of the insertion signal so that the DC component extracted by the low-pass filter becomes zero.

  According to the time slot monitoring method, in step A, the first clock signal is extracted. In step B, the insertion signal is inserted into the insertion target signal to generate the main signal. The inserted signal is a signal obtained by extracting an optical signal for one channel from an optical time division multiplexed signal generated by multiplexing. An insertion signal carrying a new signal is inserted into the extracted time slot for one channel, and a main signal is generated. Therefore, in all the time slots of the main signal, the optical signals of the respective channels exist in all the time slots assigned for each channel.

  In step C, the second clock signal is extracted from the main signal, and in step D, the first clock signal and the second clock signal are mixed.

Before step D is performed, reason for providing the phase and the phase adjustment step of order to adjust the relative phase difference between the phase of the second clock signal of the first clock signal is in the following points. The first path from the position where the inserted signal is branched by the first branching device to the mixer via the first photoelectric converter and the first clock signal extractor, and the position where the inserted signal is branched by the first branching device The path length differs from the second path from the optical time division inserter, the second branching unit, the second photoelectric converter, and the second clock signal extractor to the mixer.

Therefore, the phase adjuster adjusts the phase of the second clock signal so that the path length difference between the first path and the second path substantially disappears from the phase of the first clock signal and the second clock signal. To do. In this way, the relative phase difference between the phase of the first clock signal and the phase of the second clock signal may be adjusted, so the phase adjuster is installed in the second path even if it is installed in the first path. It doesn't matter.

  In the phase adjuster, the phase of the second clock signal is specifically adjusted as follows. By using an optical sampling oscilloscope or the like in advance, the time waveform of the main signal is observed to realize a state in which the insertion signal is accurately inserted in the time slot in which the insertion signal of the inserted signal is to be inserted. In order to realize this state, the phase of the insertion signal may be adjusted.

  When it is confirmed that the insertion signal is correctly inserted in the time slot of the inserted signal into which the insertion signal is to be inserted, the phase adjuster monitors the phase of the second clock signal as the output signal from the mixer. Adjust so that the signal is output as 0 (for example, 0 V).

  As described above, if the phase of the second clock signal is adjusted by the phase adjuster, the inserted signal is not accurately inserted in the time slot where the inserted signal is to be inserted due to the influence of time jitter, etc. If this occurs, a voltage value other than 0 is output as the monitor signal. Although details will be described later, the magnitude of the shift amount on the time axis between the time slot in which the inserted signal is to be inserted and the actually inserted time slot is found from the absolute value of the monitor signal. Further, from the code representing the potential of the monitor signal, it can be determined whether the insertion signal is located at an excessively advanced position or a delayed position from the time slot where the insertion signal is to be accurately inserted.

  Therefore, it is possible to monitor whether or not the insertion signal is accurately inserted in the time slot in which the insertion target signal is to be inserted by the monitor signal. In addition, it can be known from the magnitude of the monitor signal how much the insertion signal has been inserted shifted on the time axis, and the first object of the present invention is achieved.

  As will be described later, the time slot monitoring method is realized by the time slot monitoring device described above.

  According to the optical time division signal insertion method, in step E, the high frequency component is removed from the monitor signal, and the DC component is extracted. This DC component becomes 0 if the insertion signal is correctly inserted in the time slot where the inserted signal is to be inserted as described above, and if the insertion signal is not correctly inserted, the DC component is inserted on the time axis. The voltage value is proportional to the magnitude of the deviation from the position to be made. Therefore, if the phase of the insertion signal is adjusted so that this DC component becomes 0 in step F, the position where the insertion signal is inserted on the time axis is always adjusted so that it matches the position where it should be inserted. Is done.

  Therefore, it is possible to accurately insert an optical pulse carrying new information at the position of a time slot corresponding to an empty channel where an optical signal is dropped, and the second object of the present invention is achieved.

  As will be described later, the optical time division signal insertion method is realized by the optical time division signal insertion device described above.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. Each figure shows one configuration example according to the present invention, and only schematically shows the arrangement relationship of each component to the extent that the present invention can be understood. It is not limited to. In the following description, specific equipment and conditions may be used. However, these materials and conditions are only one of preferred examples, and are not limited to these. Moreover, in each figure, about the same component, it attaches | subjects and shows the same code | symbol, The duplicate description may be abbreviate | omitted. In addition, an optical path is indicated by a thick line, and an electric path is indicated by a thin line. The numbers given to the bold lines and the thin lines mean the optical signal and the electric signal propagating through the optical path and the electric path to which the numbers are attached, respectively.

<First embodiment>
With reference to FIG. 1, the configuration and function of a time slot monitor device for an insertion signal will be described. FIG. 1 is a schematic block diagram of a time slot monitor apparatus.

  The time slot monitor device includes a first clock signal extraction unit 32, an optical time division inserter 14, a second clock signal extraction unit 34, and a mixer 20. The first clock signal extraction unit 32 extracts the first clock signal 19 from the inserted signal 10. The optical time division inserter 14 inserts the insertion signal 11 into the inserted signal 13a to generate the main signal 15. The second clock signal extraction unit 34 extracts the second clock signal 25 from the main signal 15. The mixer 20 mixes the first clock signal 19 and the second clock signal 25 and generates a mixing signal as the monitor signal 35.

  The first clock signal extractor 32 includes a first branching device 12 and a first clock signal extractor 26. The second clock signal extraction unit 34 includes a second branching unit 16, a second clock signal extracting unit 36, and a phase adjuster 24.

  In the embodiment of the time slot monitor device shown in FIG. 1 and the embodiment of the optical time division signal insertion device shown in FIG. 5 described later, the phase adjuster 24 is installed in the second clock signal extraction unit 34. However, the phase adjuster 24 may be installed in the first clock signal extraction unit 32. Whether the phase adjuster 24 is installed in the first clock signal extraction unit 32 or the second clock signal extraction unit 34 is a problem belonging to the design matter.

  The inserted signal 10 is input to the first branching device 12 and branched into the inserted signal 13a and the clock extracting optical signal 13b. The clock extraction optical signal 13b is input to the first clock signal extractor 26, and the first clock signal 19 is generated and output.

  On the other hand, the inserted signal 13a is input to the optical time division inserter 14, is combined with the insertion signal 11, and is generated and output as the main signal 15. The main signal 15 is input to the second branching device 16 and branched into a main signal 17a and an optical main signal 17b for clock extraction. The clock extraction optical main signal 17b is input to the second clock signal extractor 36, and the second clock signal 23 is generated and output. The second clock signal 23 is input to the phase adjuster 24, the phase of which is adjusted, generated as the second clock signal 25, and input to the mixer 20.

  The phase adjuster 24 includes a first path from the position where the inserted signal 10 is branched by the first branching device 12 to the mixer 20 via the first clock signal extractor 26, and the inserted signal by the first branching device 12. The path length difference from the second path from the position where 10 is branched to the mixer through the optical time division inserter 14, the second branching device 16, and the second clock signal extractor 36 is the first clock signal and the second The phase of the second clock signal is adjusted so that it substantially disappears above the phase with the clock signal. Thus, since the relative relationship between the phase of the first clock signal and the phase of the second clock signal may be adjusted, the phase adjuster is installed in the second path even if it is installed in the first path. It doesn't matter.

  Therefore, the second clock signal 25 is converted by the phase adjuster 24 to change the phase of the second clock signal 23 to the first path from the first branching device 12 to the mixer 20 (path through the first clock signal extraction unit 32). And a signal obtained by correcting the path length difference from the second path from the second branching device to the mixer (path through the second clock signal extraction unit 34).

  The function performed by the phase adjuster 24 can be easily realized by a variable phase delay electric circuit using a known delay logic. In addition, an optical element such as a semi-transparent mirror can be used for the first and second branching devices. As the first and second clock signal extractors, a known clock signal extraction device configured with electrical means after photoelectrically converting an optical signal into an electrical signal can be used. As the mixer, a known mixing circuit in the field of high-frequency electric circuits can be used as appropriate.

  The extraction of the first and second clock signals is not limited to the known clock signal extraction device configured with the above-described electrical means, and a difference frequency component is given by using a nonlinear effect of the optical modulator to obtain the difference frequency. A method of extracting a clock signal by configuring a PLL (Phase Locked Loop) using components (for example, “Development of 160 Gb / s clock extractor”, Hiromi Tsuji, et al., 2003 IEICE Communication Society Conference, B -10-115, 2003, or "Scaleable 80 Gbit / s OTDM using a modular architecture based on EA modulators", HT Yamada et al., ECOC 2000 pp. 47-48, Munich, 2000.), mode-locked semiconductor Various methods such as a method of generating an optical clock pulse using a laser and photoelectrically converting the optical clock pulse can be used.

  2 (A) to (G), FIGS. 3 (A) and 3 (B), and FIGS. 4 (A) and 4 (B), with respect to the process of generating the monitor signal 35 output from the mixer 20, The operation principle and the physical meaning of the monitor signal 35 will be specifically described. FIGS. 2A to 2G are time waveform diagrams for explaining the relationship between the inserted signal and the inserted signal, and FIGS. 3A and 3B are diagrams for explaining the clock phase display vector. FIGS. 4A and 4B are diagrams for explaining the operation principle of the time slot monitor device. In FIGS. 2A to 2G, the horizontal axis represents the time axis on an arbitrary scale, and the light intensity is represented on the vertical axis direction (the vertical axis is omitted).

  In the following description, it is assumed that the main signal is a 4-channel multiplexed signal, and the insertion signal is inserted in the time slot of the channel corresponding to the fourth channel. Therefore, the inserted signal is a signal in a state where the time slot corresponding to the fourth channel is vacant. Needless to say, the following description is not limited to the case where the multiplicity of the main signal is 4 channels, and it is obvious that the description is valid regardless of which time slot the insertion signal is inserted into.

  Fig. 2 (A) shows the time waveform of the main signal, Fig. 2 (B) shows the time waveform of the first channel, Fig. 2 (C) shows the time waveform of the second channel, and Fig. 2 (D) shows the third channel. FIG. 2E shows the time waveform of the fourth channel, and FIG. 2F shows the time waveform of the inserted signal. FIG. 2 (G) is a diagram for explaining how an insertion signal is inserted into a signal to be inserted. In FIG. 2 (G), the time waveform of the inserted signal is indicated by a thin line, and the time waveform of the inserted signal is indicated by a thick line.

2A to 2G, assuming that the optical signal of the time slot to which the fourth channel of the main signal is assigned is extracted and the insertion signal is inserted into this time slot, each time is assumed. The waveform is shown. The center position of the time slot to which the fourth channel is assigned (corresponding to the fourth slot described later) is indicated by T ₁ , T ₂ and T ₃ as shown in FIG. 2 (G). The optical pulses constituting the insertion signal inserted in the time slot are denoted by R ₁ , R ₂ and R ₃ , respectively.

  Here, in order to describe the operation of the mixer 20, the concept of the clock phase will be described in advance. The clock phase is a concept for expressing the inserted signal and the time waveform of the inserted signal in correspondence with the vector, and is displayed by a clock phase display vector defined as follows.

  As shown in FIG. 3A, the clock phase display vector corresponds to the first to fourth slots on a one-to-one basis. Here, it is assumed that the first to fourth channels are assigned to the first to fourth slots, respectively. The time waveform of the first channel assigned to the first slot is shown in FIG. 2 (B).

  The main signal shown in FIG. 2 (A) is a signal generated by superimposing all the optical pulse signals of the first to fourth channels assigned to the first to fourth slots. Therefore, each time slot is arranged in the order of the first, second, third, fourth, first, second, third, fourth, first, second, third, and fourth slots on the time axis. Is present.

  FIG. 2B shows a special case where an optical pulse is present in all the bits of the first channel for the sake of simplicity. FIG. 2B shows a time slot range of 3 bits, and an optical pulse exists in all of these 3 bits. 2 (C), (D), and (E) also show a case where optical pulses are present in all three bits. However, since the optical pulse signal of the first channel is actually an RZ signal, there are bits in which no optical pulse exists according to the transmitted information. Thus, even when the optical pulse signal of each channel is an RZ signal, the following description is similarly valid.

The clock phase indication vector is a vector according to the following promise. That is, the magnitude of the clock phase display vector is proportional to the intensity of the optical pulse, and the direction is proportional to the amount of deviation of the time slot from the reference on the time axis. As shown in Fig. 3 (A), the clock phase display vector corresponding to the first slot is assumed to be horizontal rightward, and the clock phase display vector rotated by 90 ° is supported for the second to fourth slots. Let This fourth slot from the first has been reflected that are displaced by a 1/4 phase in time.

As described above, the fourth slot from the first is when are displaced by exactly 1/4 phase on the time axis, when summing all clock phases display vectors corresponding to these time slots, FIG. As shown in 3 (B), it is a zero vector. Therefore, when the insertion signal is inserted into the accurate time slot of the inserted signal, the time waveform of the generated main signal becomes the time waveform shown in FIG. 2 (A), so the clock phase display corresponding to this state The vector is a 0 vector.

  Here, the clock phase display vector of the inserted signal will be described. As shown in FIG. 2 (F), the inserted signal is obtained by extracting the optical pulse signal of the fourth channel assigned to the fourth slot, and there is no optical pulse signal in this fourth slot. It is a state signal. Accordingly, the first, second, and third slots correspond to the first, second, and third slots, respectively, corresponding to the presence of optical pulse signals of the first, second, and third channels, respectively. The clock phase display vector is represented by a state indicated by a solid arrow in FIG. Therefore, a clock phase display vector P (hereinafter, simply referred to as “vector P”) obtained by combining these is represented by an upward broken arrow.

  As shown in Fig. 2 (G), the main signal obtained when the insertion signal corresponding to the fourth channel represented by the thick light pulse is combined with the insertion signal displayed by the vector P A description will be given of how the clock phase display vector corresponding to is represented. As shown in FIG. 4B, when the vector P is drawn with the start point of the vector at X, the clock phase display vector R (hereinafter simply referred to as “vector R”) corresponding to the inserted signal may be used. ) Is placed at the end point of the vector P. This is because the clock phase display vector Q corresponding to the main signal (hereinafter sometimes simply referred to as “vector Q”) is a vector given by the sum of the vector P and the vector R.

  The monitor signal 35 output from the mixer 20 is output as a voltage signal. The absolute value of the voltage value is proportional to the absolute value of the vector Q, and the sign of the voltage value reflects the direction of the vector Q. That is, if the vector Q is a zero vector, a 0 V monitor signal 35 is output from the mixer 20. On the other hand, when the vector Q is not a zero vector, the mixer 20 outputs a voltage signal proportional to the absolute value of the vector Q as the monitor signal 35. The sign of the voltage at this time is determined by the position of the circle S where the end point of the vector Q exists.

  For example, when the end point of the vector Q is on the left half side of the circle S, it is a positive voltage, and when it is on the right half side, it is a negative voltage, or vice versa, on the left half side of the circle S. It can be arbitrarily set with respect to the mixer 20 so that it is sometimes a negative voltage and a positive voltage when it is on the right half side. The sign of the voltage of the monitor signal 35 can be set to any of the above, and the sign setting of the voltage belongs to a design matter. In addition, since the known mixer circuit only needs to have a function of outputting a signal corresponding to the monitor signal 35 described above, the mixer 20 may appropriately use a known mixing circuit having this function. Is possible.

  As is clear from FIG. 3 (B), when the insertion signal is inserted into an accurate time slot (in this case, the fourth slot) to be inserted into the inserted signal, a vector corresponding to the insertion signal. Since R is equal to the clock phase display vector corresponding to the fourth slot, eventually, the magnitude is equal to and opposite to the vector P corresponding to the inserted signal. Therefore, the vector Q corresponding to the main signal, which is given by the sum of the vector R and the vector P, is a zero vector.

  On the other hand, as shown in FIG. 2 (G), the insertion signal indicated by the thick light pulse is in the accurate time slot to be inserted with respect to the inserted signal indicated by the thin light pulse. When not inserted, the vector R corresponding to the inserted signal is as shown in FIG. In FIG. 2 (G), since the insertion signal is inserted between the second slot and the third slot of the inserted signal, the vector R corresponding to the insertion signal corresponds to the second slot and the third slot, respectively. Oriented in the direction between clock phase display vectors. That is, the vector R is oriented in a direction inclined 45 ° to the left from the direction directly above.

  Since the position on the time axis where the insertion signal is inserted is within the range of the first to fourth slots, the end point of the vector R is any position on the circle S with the end point of the vector P as the center. . In FIG. 4 (B) reflecting the case shown in FIG. 2 (G), the absolute value of the vector Q corresponds to the fact that the insertion signal is not inserted into the time slot to be inserted correctly. Is not 0, and the end point of the vector Q exists on the left half side of the circle S.

  As described above, the information indicating whether the insertion signal is inserted into the time slot to be inserted correctly or not inserted is obtained from the absolute value of the monitor signal 35 which is the mixing signal output from the mixer 20. The magnitude of the amount of deviation is found. Further, from the sign representing the potential of the monitor signal 35, it can be determined whether the insertion signal is located at a position that is advanced or delayed from the time slot in which the insertion signal is to be accurately inserted.

  For example, in the case of the example shown in FIG. 2 (G), the time slot into which the insertion signal is to be accurately inserted is the fourth slot, whereas the position on the inserted time axis is the second slot. Between the third slot. That is, the end point of the vector Q exists in the left half of the circle S, reflecting that the insertion signal is inserted at a position delayed on the time axis with respect to the fourth slot.

  If the insertion signal is inserted at a position between the first slot and the second slot, the end point of the vector Q is at the right half of the circle S. Thus, since the end point position of the vector Q is determined according to the position on the time axis where the insertion signal is inserted, the insertion signal is accurately calculated from the sign representing the potential of the monitor signal 35 determined by the end point position of the vector Q. It can be determined whether the position on the time axis to be inserted is at an excessively advanced position or a delayed position.

<Second Embodiment>
The configuration and function of the optical time division signal insertion device will be described with reference to FIG. FIG. 5 is a schematic block diagram of an optical time division signal insertion device.

  This optical time division signal insertion device includes a time slot monitor device 50, a low-pass filter unit 52, and an insertion signal phase adjuster 48. Since the time slot monitor device described in the first embodiment is used as the time slot monitor device 50, the description related to the time slot monitor device 50 is omitted here.

  As described above, the monitor signal 35 output from the time slot monitor device 50 is a mixing signal of the first clock signal 19 extracted from the inserted signal 10 and the second clock signal 25 extracted from the main signal 15. It is. Therefore, the monitor signal 35 has a voltage signal proportional to the difference frequency between the main Fourier frequency component of the first clock signal and the main Fourier frequency component of the second clock signal as a main component, and AC of various frequencies that are noise components. Contains ingredients. These AC components of various frequencies are derived from Fourier frequency components other than the main Fourier frequency component slightly included in the first and second clock signals.

  The main Fourier frequency component of the first clock signal is a sine wave component having a frequency corresponding to the bit rate of the inserted signal. On the other hand, the main Fourier frequency component of the second clock signal is a sine wave component having a frequency corresponding to the bit rate of the main signal. If the insertion signal is correctly inserted in the time slot in which the inserted signal is to be inserted, the main Fourier frequency component of the first clock signal and the main Fourier frequency component of the second clock signal are equal. The mixing signal output from the mixer 20 is generally a signal having a difference frequency between the two frequencies. Therefore, if the frequencies of both are equal, a DC signal is output. In this case, the mixing circuit constituting the mixer 20 can be set so as to output 0 V.

  On the other hand, if the insertion signal is not accurately inserted in the time slot in which the inserted signal is to be inserted, the main Fourier frequency component of the first clock signal and the main Fourier frequency component of the second clock signal described above Differences occur. As a result, as already described in detail, the monitor signal 35 corresponding to the vector indicating the clock phase is output from the mixer 20.

  In any case, the important signal among the signals output from the mixer 20 is 0 V or a voltage signal proportional to the difference frequency between the first clock signal 19 and the second clock signal 25. Therefore, the high-frequency component is removed by the low-pass filter 42.

  Further, since the intensity of the mixing signal output from the mixer 20 is weak, it is practical to amplify the low-frequency component 43 of the mixing signal output by removing the high-frequency component by the low-pass filter 42 by the amplifier 44. is there. The signal 45 output from the amplifier 44 is preferably filtered by a low-pass filter 46 in order to remove high-frequency components mixed in the process of being amplified by the amplifier 44.

  Therefore, it is preferable that the optical time division signal insertion device includes a low-pass filter unit 52. As described above, the low-pass filter unit 52 includes two low-pass filters 42 and 46 and an amplifier 44 in order to realize a function of removing only a DC component by removing high-frequency components from the monitor signal. Is good.

  A signal 47 output from the low-pass filter 46 is an insertion signal phase adjustment signal for input to the insertion signal phase adjuster 48 as a control signal. In FIG. 5, the signal A output from the low-pass filter 46 (hereinafter referred to as “insertion signal phase adjustment signal 47”) is input to the insertion signal phase adjuster 48. It is shown using.

  The operation of the insertion signal phase adjuster 48 will be described with reference to FIGS. 6 (A), (B), and (C). 6A shows a time waveform of the inserted signal 10, FIG. 6B shows a time waveform of the inserted signal 11, and FIG. 6C shows a time waveform of the main signal 15. 6 (A), (B), and (C), as in FIGS. 2 (A) to (G), the main signal is assumed to be a 4-channel multiplexed signal. Further, the slot into which the insertion signal 11 is inserted is shown as being the fourth slot of the inserted signal 10. That is, in FIG. 6A, there is no optical pulse on the time axis corresponding to the fourth slot.

6 (A), (B), and (C), the positions on the time axis corresponding to the fourth slot are T ₁ , T _2, and T ₃ as shown in FIG. 2 (G). It is shown. Similarly, the optical pulses constituting the inserted signal inserted in these time slots are indicated by R ₁ , R ₂ and R ₃ , respectively.

The phase of the insertion signal 11 is adjusted by the insertion signal phase adjuster 48, as shown in FIG. 6B. The optical pulses (R ₁ , R ₂ and R ₃ constituting the insertion signal 11) This corresponds to moving the pulse) along the time axis. In FIG. 6 (B), this is indicated by a double-headed arrow shown along the time axis in the optical pulse constituting the insertion signal 11. Similarly, when the time slot into which the insertion signal in the inserted signal is to be inserted is changed, similarly, the insertion signal phase adjuster 48 moves the optical pulse constituting the insertion signal 11 along the time axis. The time slot in which the insertion signal is to be inserted can be adjusted to match the time slot in which this optical pulse is present.

  If the insertion signal 11 is correctly inserted into the fourth slot of the inserted signal 10, the time waveform of the main signal 15 becomes as shown in FIG. 6 (C). At this time, the monitor signal output from the mixer 20 The value of 35 is 0 V. That is, the value of the insertion signal phase adjuster 48 obtained by filtering and amplifying the monitor signal 35 is 0V.

  In the insertion signal phase adjuster 48, as described above, the phase of the insertion signal 11 is adjusted so that the insertion signal phase adjustment signal 47 is always 0 V. When the insertion signal phase adjustment signal 47 is a positive voltage, the phase of the insertion signal 11 is delayed until the insertion signal phase adjustment signal 47 becomes 0 V. On the other hand, when the insertion signal phase adjustment signal 47 is a negative voltage, the phase of the insertion signal 11 is advanced until the insertion signal phase adjustment signal 47 reaches 0 V. Or, conversely, if the insertion signal phase adjustment signal 47 is a positive voltage, the phase of the insertion signal 11 is advanced until the insertion signal phase adjustment signal 47 reaches 0 V. On the other hand, when the insertion signal phase adjustment signal 47 is a negative voltage, the phase of the insertion signal 11 is delayed until the insertion signal phase adjustment signal 47 reaches 0 V.

  When the optical pulse constituting the insertion signal 11 is accurately inserted into the time slot to be inserted by the insertion signal phase adjuster 48, the insertion signal phase adjustment signal 47 becomes 0 V. The phase adjustment operation of the phase adjuster 48 ends. That is, when the insertion signal phase adjustment signal 47 supplied to the insertion signal phase adjuster 48 becomes 0 V, the operation of the insertion signal phase adjuster 48 stops, and the phase adjustment amount for the insertion signal 11 at that time Is retained.

  If the optical pulse constituting the insertion signal 11 is inserted at a position deviated from the time slot to be inserted due to time jitter occurring in the inserted signal 10 or the like, the phase of the insertion signal is changed according to the deviation. Since the adjustment signal 47 has a value different from 0 V, the phase adjustment of the insertion signal phase adjuster 48 follows the value of the insertion signal phase adjustment signal 47 and delays or advances the phase of the insertion signal 11 described above. Since the function operates, feedback control is performed so that the insertion signal phase adjustment signal 47 is always 0 V.

  Whether the operation of the insertion signal phase adjuster 48 is set to advance or delay the phase of the insertion signal 11 depending on whether the voltage value of the insertion signal phase adjustment signal 47 is positive or negative depends on the clock phase display vector Q described above. Therefore, it belongs to a design matter determined by how the mixer circuit constituting the mixer 20 is set so that the sign of the voltage of the monitor signal 35 is determined.

  As described above, in the low-pass filter unit 52, by controlling the insertion signal phase adjuster 48 by the insertion signal phase adjustment signal 47 obtained by filtering and amplifying the monitor signal 35 output from the mixer 20, It is possible to accurately insert the insertion signal 11 into the time slot in which the inserted signal 10 is to be inserted.

It is a schematic block diagram of a time slot monitor device. It is a time waveform figure with which it uses for description of the relationship between an insertion signal and a to-be-inserted signal. It is a figure where it uses for description of a clock phase display vector. It is a figure with which it uses for description of the operation principle of a time slot monitor apparatus. It is a schematic block diagram of an optical time division signal insertion device. It is a figure where it uses for description of the principle of operation of an optical time division signal insertion apparatus.

Explanation of symbols

10: Inserted signal
11: Insertion signal
12: First turnout
14: Optical time division inserter
15: Main signal
16: Second turnout
20: Mixer
24: Phase adjuster
26: 1st clock signal extractor
32: First clock signal extractor
34: Second clock signal extractor
36: Second clock signal extractor
42, 46: Low-pass filter
44: Amplifier
48: Insertion signal phase adjuster
50: Time slot monitor device
52: Low-pass filter

Claims (4)

(A) Step A for extracting a first clock signal from an inserted signal, which is a signal from which an optical signal for one channel is extracted from an optical time division multiplexed signal generated by multiplexing ;
(B) said of the insertion signal, to the 1 time optical signal channels are empty withdrawn slot, insert the insertion signal is a signal carrying a new signal, a step B of generating a main signal ,
(C) Step C for extracting a second clock signal from the main signal;
(D) the order to monitor the amount of deviation of the size on the time axis of the inserted time slot to be inserted time slots and reality of the insertion signal, the first clock signal and the second clock signal Step D that compares the phase and converts the phase difference between the two into an electrical signal to generate a monitor signal ,
Step A is
(A1) a first branching step for branching the optical signal for clock extraction for extracting the first clock signal from the inserted signal;
(A2) a first clock signal extraction step for extracting the first clock signal from the clock extraction optical signal;
Including
Step C is
(C1) a second branching step for branching the optical main signal for clock extraction for extracting the second clock signal from the main signal;
(C2) a second clock signal extracting step for extracting the second clock signal from the optical main signal for clock extraction;
Including
A first path to a position where the first clock signal extraction step is executed via a position where the first branch step is executed, and the second path via a position where the second branch step is executed For adjusting a relative phase difference between the phase of the first clock signal and the phase of the second clock signal, which is generated by a path length difference from the second path to the position where the clock signal extraction step is executed. A time slot monitoring method comprising a phase adjustment step in any one of the steps A and C. (A) Step A for extracting a first clock signal from an inserted signal, which is a signal from which an optical signal for one channel is extracted from an optical time division multiplexed signal generated by multiplexing ;
(B) Step B for generating a main signal by inserting an insertion signal, which is a signal that bears a new signal, into a time slot in which the optical signal for the one channel of the inserted signal is extracted and vacant ;
(C) Step C for extracting a second clock signal from the main signal;
(D) the order to monitor the amount of deviation of the size on the time axis of the inserted time slot to be inserted time slots and reality of the insertion signal, the first clock signal and the second clock signal Step D for comparing the phases and converting the phase difference between the two into an electrical signal to generate a monitor signal; (E) Step E for removing a high frequency component from the monitor signal and extracting a DC component;
(F) adjusting the phase of the insertion signal so that the DC component extracted in step E becomes 0, and
Step A is
(A1) a first branching step for branching the optical signal for clock extraction for extracting the first clock signal from the inserted signal;
(A2) a first clock signal extraction step for extracting the first clock signal from the clock extraction optical signal;
Including
Step C is
(C1) a second branching step for branching the optical main signal for clock extraction for extracting the second clock signal from the main signal;
(C2) a second clock signal extracting step for extracting the second clock signal from the optical main signal for clock extraction;
Including
A first path to a position where the first clock signal extraction step is executed via a position where the first branch step is executed, and the second path via a position where the second branch step is executed For adjusting a relative phase difference between the phase of the first clock signal and the phase of the second clock signal, which is generated by a path length difference from the second path to the position where the clock signal extraction step is executed. An optical time division signal insertion method characterized by including a phase adjustment step in one of steps A and C. A first clock signal extraction unit for extracting a first clock signal from an inserted signal, which is a signal from which an optical signal for one channel is extracted from an optical time division multiplexed signal generated by multiplexing ;
Wherein of the insertion signal, the in one channel time slot to an optical signal is free is withdrawn, by inserting the insertion signal is a signal carrying a new signal, and an optical time division inserter for generating a main signal ,
A second clock signal extraction unit for extracting a second clock signal from the main signal;
Compare the phases of the first clock signal and the second clock signal in order to monitor the amount of deviation on the time axis between the time slot in which the inserted signal is to be inserted and the actually inserted time slot. And a mixer that converts the phase difference between the two into an electrical signal to generate a monitor signal ,
The first clock signal extraction unit,
A first branching device for branching the optical signal for clock extraction for extracting the first clock signal from the inserted signal;
A first clock signal extractor for extracting the first clock signal from the clock extracting optical signal;
With
The second clock signal extraction unit,
A second branching device for branching the optical main signal for clock extraction for extracting the second clock signal from the main signal;
A second clock signal extractor for extracting the second clock signal from the optical main signal for clock extraction;
With
For adjusting a relative phase difference between the phase of the first clock signal output from the first clock signal extractor and the phase of the second clock signal output from the second clock signal extractor. A time slot monitor device comprising a phase adjuster in one of the first clock signal extraction unit and the second clock signal extraction unit . A first clock signal extraction unit for extracting a first clock signal from an inserted signal, which is a signal from which an optical signal for one channel is extracted from an optical time division multiplexed signal generated by multiplexing ;
Wherein of the insertion signal, the in one channel time slot to an optical signal is free is withdrawn, by inserting the insertion signal is a signal carrying a new signal, and an optical time division inserter for generating a main signal ,
A second clock signal extraction unit for extracting a second clock signal from the main signal;
Compare the phases of the first clock signal and the second clock signal in order to monitor the amount of deviation on the time axis between the time slot in which the inserted signal is to be inserted and the actually inserted time slot. A mixer that converts the phase difference between the two into an electrical signal and generates a monitor signal;
A low-pass filter unit that extracts a DC component by removing a high-frequency component from the monitor signal;
An insertion signal phase adjuster that adjusts the phase of the insertion signal so that the DC component extracted by the low-pass filter unit becomes 0 ;
The first clock signal extraction unit,
A first branching device for branching an optical signal for clock extraction for extracting a first clock signal from the inserted signal;
A first clock signal extractor for extracting the first clock signal from the clock extracting optical signal;
With
The second clock signal extraction unit,
A second branching device for branching the optical main signal for clock extraction for extracting the second clock signal from the main signal;
A second clock signal extractor for extracting the second clock signal from the optical main signal for clock extraction;
With
For adjusting a relative phase difference between the phase of the first clock signal output from the first clock signal extractor and the phase of the second clock signal output from the second clock signal extractor. An optical time division signal insertion device comprising a phase adjuster in one of the first clock signal extraction unit and the second clock signal extraction unit .

Images