JP4769003B2 - Display device - Google Patents

Description

  The present invention relates to a display device including a multi-gradation processing circuit that performs multi-gradation processing on an input video signal.

  In a display device that employs a plasma display panel as a display device, dither processing is performed on an input video signal, thereby increasing the number of visual gradations and improving image quality.

  For example, in the dither processing, four pixels adjacent to each other vertically and horizontally are taken as one set, and four dither coefficients (for example, 0, 1 and the like) having different coefficient values for pixel data corresponding to each of the one set of pixels. 2, 3) are added. By performing light emission control for each pixel based on the dither addition pixel data to which the dither coefficient is added, the apparent number of luminance gradations when these four pixels are regarded as one pixel is increased. .

  However, when a dither coefficient is added to pixel data, a so-called dither noise in which a pseudo pattern unrelated to the original pixel data is visually observed may occur, resulting in a problem that image quality is impaired.

Therefore, in order to reduce such dither noise, an apparatus has been proposed in which the dither coefficient pattern is changed or the dither matrix size is changed in accordance with the average luminance level of the video signal (see, for example, Patent Document 1). )
However, even if the dither processing method is changed in accordance with the average luminance level of the video signal, there is a problem that dither noise occurs depending on the pattern represented by the video signal.
JP 2004-258069 A

  The present invention has been made to solve such a problem, and provides a display device capable of performing a multi-gradation process on an input video signal without degrading the image quality and performing a good image display. The purpose is to do.

A display device according to a first aspect of the present invention includes a display device including a plurality of display cells that carry pixels, and multi-gradation pixel data by performing multi-gradation processing on pixel data for each pixel based on a video signal. And a display driving means for causing the display cell to emit light at a luminance corresponding to the multi-gradation pixel data, and each unit pixel block in the display device Provided with a luminance gradient detecting means for detecting whether or not a luminance gradient based on the pixel data is larger than a predetermined reference gradient, wherein the multi-gradation processing means has the luminance gradient smaller than the reference gradient. the first multi-story when it is ordered dither processing to be added to the pixel data corresponding dither value corresponding to each pixel position of said unit pixel block in the pixel position While obtaining the multi-grayscale pixel data by performing processing on the pixel data, when the luminance gradient is greater than the reference slope is the number of compressed bits than the first multi-gradation processing The multi-gradation pixel data is obtained by subjecting the pixel data to a second multi-gradation process, which is a small tissue dither process .
According to a second aspect of the present invention, there is provided a display device comprising a display device having a plurality of display cells for carrying pixels, and performing multi-gradation processing on pixel data for each pixel based on a video signal to achieve multi-gradation. A display device comprising: multi-gradation processing means for obtaining pixel data; and display drive means for causing the display cell to emit light at a luminance corresponding to the multi-gradation pixel data, wherein the unit pixel in the display device A luminance gradient detecting unit configured to detect whether or not a luminance gradient based on the pixel data is greater than a predetermined reference gradient for each block; and the multi-gradation processing unit includes the luminance gradient that is greater than the reference gradient. 1 is a systematic dither process for adding a dither value corresponding to each pixel position in the unit pixel block to the pixel data corresponding to the pixel position when A second multi-gradation process that is an error diffusion process when the multi-gradation pixel data is obtained by performing a gradation process on the pixel data, while the luminance gradient is larger than the reference gradient. Is applied to the pixel data to obtain the multi-gradation pixel data .
According to a third aspect of the present invention, there is provided a display device comprising a display device having a plurality of display cells for carrying pixels, and performing multi-gradation processing on pixel data for each pixel based on a video signal to achieve multi-gradation. A display device comprising: multi-gradation processing means for obtaining pixel data; and display drive means for causing the display cell to emit light at a luminance corresponding to the multi-gradation pixel data, wherein the unit pixel in the display device A luminance gradient detecting unit configured to detect whether or not a luminance gradient based on the pixel data is greater than a predetermined reference gradient for each block; and the multi-gradation processing unit includes the luminance gradient that is greater than the reference gradient. 1 is a systematic dither process for adding a dither value corresponding to each pixel position in the unit pixel block to the pixel data corresponding to the pixel position when The multi-gradation pixel data is obtained by subjecting the pixel data to gradation processing. On the other hand, when the luminance gradient is larger than the reference gradient, the compression bit is higher than that of the first multi-gradation processing. The multi-gradation pixel data is obtained by subjecting the pixel data to a systematic dither processing process and a random dither process for adding a random dither value to the pixel data .

  When the luminance gradient in each unit pixel block based on the input video signal is smaller than the reference gradient, predetermined first multi-gradation processing is performed on the pixel data for each pixel based on the input video signal. On the other hand, when the luminance gradient is larger than the reference gradient, a second multi-gradation process different from the first multi-gradation process is performed on the pixel data.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a diagram showing a schematic configuration of a display device according to the present invention.

  In FIG. 1, a pixel data conversion circuit 1 samples an input video signal according to a predetermined sampling clock, converts it to, for example, 10-bit pixel data PD for each pixel, and converts this to a multi-gradation processing circuit 2. Supply. The multi-gradation processing circuit 2 supplies the display driving circuit 3 with multi-gradation pixel data MPD obtained by performing multi-gradation processing (described later) on the pixel data PD. The display drive circuit 3 generates various drive signals for driving the display device 4 based on the multi-gradation pixel data MPD and supplies it to the display device 4. The display device 4 includes, for example, a CRT, a plasma display panel, a liquid crystal panel, an electroluminescence display panel, and the like, and displays an image corresponding to the input video signal in accordance with the drive signal supplied from the display drive circuit 3.

  FIG. 2 is a diagram showing an internal configuration of the multi-gradation processing circuit 2.

  In FIG. 2, the random dither processing circuit 21 includes a random number data generation circuit 211, an adder 212, and an upper bit extraction circuit 213. The random number data generation circuit 211 generates a random number, extracts n bits indicated by a compressed bit number designation signal BS1 (described later) from random data indicating a value corresponding to the random number, and extracts this random noise. The data is supplied to the adder 212 as data. The adder 212 adds the value indicated by the n-bit random noise data to the value indicated by the 10-bit pixel data PD, and adds the 10-bit random noise superimposed data indicating the addition result value to the upper level. This is supplied to the bit extraction circuit 213. The upper bit extraction circuit 213 excludes n bits of lower bit groups (including the lowest bit) indicated by the bit number designation signal BS1 from the random noise superimposed data, that is, upper bits (10 -N) Extract bits and supply them to the selector 22 as line dither processing pixel data LDD.

  That is, the random dither processing circuit 21 performs dither processing on the pixel data PD using random data whose value changes as needed as a dither value. By such dither processing, the random dither processing circuit 21 compresses the bit number by n bits indicated by the compression bit number designation signal BS1 while maintaining the number of luminance gradations represented by the pixel data PD. The line dither processing pixel data LDD is generated.

  The selector 22 selects one of the line dither processing pixel data LDD and the pixel data PD indicated by the selection signal S1 (described later), and supplies this to the selector 23, the selector 24, and the error diffusion processing circuit 25. Supply each one.

  First, the error diffusion processing circuit 25 selects pixels G (j, k), G () having the arrangement relationship shown in FIG. 3 from the series of pixel data PD or line dither processing pixel data LDD supplied from the selector 22. Pixel data corresponding to each of j, k-1), G (j-1, k-1), G (j-1, k), and G (j-1, k + 1) is extracted. Next, the error diffusion processing circuit 25 uses these pixels G (j, k-1), G (j-1, k + 1), G (j-1, k), and G (j-1, k- 1) From the pixel data (LDD or PD) corresponding to each, a lower bit group (including the least significant bit) for t bits indicated by a compressed bit number designation signal BS2 (described later) is extracted. Next, the error diffusion processing circuit 25 weights and adds these lower bit groups to obtain a lower bit group weighted addition value WL. Next, the error diffusion processing circuit 25 extracts an upper bit group obtained by removing the lower bit group for the t bits from the pixel data (LDD or PD) corresponding to the pixel G (j, k). Then, the error diffusion processing circuit 25 adds “1” when the lower bit group weighted addition value WL is larger than a predetermined value, and adds “0” to the upper bit group as described above when it is smaller, The addition result is supplied as error diffusion processing pixel data ED to the selectors 23 and 24, respectively.

  That is, the error diffusion processing circuit 25 performs error diffusion processing on the pixel data PD or the line dither processing pixel data LDD, thereby obtaining the number of luminance gradations represented by the pixel data PD or the line dither processing pixel data LDD. While maintaining the above, error diffusion pixel data ED in which the number of bits is compressed by t bits is generated.

  The selector 24 selects the one indicated by the selection signal S2 (described later) from the output from the selector 22 (pixel data PD or line dither processing pixel data LDD) and the error diffusion processing pixel data ED. This is supplied to the tissue dither processing circuit 26.

The systematic dither processing circuit 26 includes a first dither generation circuit 261, a second dither generation circuit 262, a selector 263, an adder 264, and an upper bit extraction circuit 265. The first dither generation circuit 261 generates 16 dither values A _{(1,1) to} A _(4,4) having different values corresponding to each pixel position in the 4 × 4 pixel block. And sequentially supplied to the selector 263. The second dither generation circuit 262 generates four dither values B _{(1,1) to} B _(2,2) having different values corresponding to each pixel position in the 2 × 2 pixel block. And sequentially supplied to the selector 263. The selector 263 relays the dither values A _{(1,1) to} A _(4,4) to the adder 264 when the compression bit number indicated by the compression bit number designation signal BS3 (described later) indicates 4 bits. On the other hand, when the compressed bit number indicated by the compressed bit number designating signal BS3 indicates 2 bits, the dither values B _{(1,1) to} B _(2,2) are relayed to the adder 264. The adder 264 is obtained by adding the dither value A or B supplied from the selector 263 to the pixel data PD, line dithered pixel data LDD or error diffusion processed pixel data ED supplied from the selector 24. The addition result is supplied to the upper bit extraction circuit 265 as dither addition pixel data. When the dither values A _{(1,1) to} A _(4,4) are supplied from the selector 263, the adder 264 outputs data corresponding to each pixel (PD, LDD, or ED) 4 rows × Corresponding to the positions in the four columns of pixel blocks, the dither value A corresponding to the position is added to this data. On the other hand, when the dither values B _{(1,1) to} B _(2,2) are supplied from the selector 263, the data (PD, LDD, or ED) corresponding to each pixel is converted into a pixel block of 2 rows × 2 columns. The dither value B corresponding to the position is added to this data. The upper bit extraction circuit 265 eliminates the lower bit group (including the lowest bit) of the number of bits (2 or 4 bits) indicated by the compressed bit number designation signal BS3 from the dither addition pixel data. A group is extracted and supplied to the selector 23 as the tissue dither processing pixel data CDD.

That is, the systematic dither processing circuit 26 first, for pixel data (PD, LDD or ED) corresponding to each pixel, for each unit pixel block, a dither value (corresponding to each pixel position in the unit pixel block). A _{(1,1) to} A _(4,4) or B _{(1,1) to} B _(2,2) ) is added to the pixel data corresponding to the pixel position. Then, by extracting an upper bit group from which the lower bit group (including the least significant bit) corresponding to the number of bits indicated by the compressed bit number designation signal BS3 is omitted, the luminance in the original pixel data is extracted. The systematic dither processing pixel data CDD in which the number of bits is compressed while maintaining the number of gradations is generated. In the systematic dither processing circuit 26, the size of the unit pixel block is set (4 rows × 4 columns or 2 rows × 2 columns) according to the number of compression bits indicated by the compression bit number designation signal BS3. At this time, the larger the unit pixel block, the greater the number of compression bits by the system dithering process.

  The selector 23 outputs a selection signal S3 (described later) from the output from the selector 22 (pixel data PD or line dithered pixel data LDD), the error diffusion processed pixel data ED, and the tissue dithered pixel data CDD. Is output as the multi-gradation pixel data MPD as described above.

  The luminance gradient detection circuit 27 has a luminance gradient in the unit pixel block for each unit pixel block of N rows × M columns based on the pixel data PD for each pixel based on the input video signal from a predetermined reference gradient. And the luminance gradient detection signal HD indicating the determination result is generated. That is, for each unit pixel block, the luminance gradient detection circuit 27 is supplied with a video signal corresponding to a picture with a large luminance height or a small luminance height. A luminance gradient detection signal HD indicating whether or not it has been generated is generated.

  FIG. 4 is a diagram illustrating an example of an internal configuration of the luminance gradient detection circuit 27 employed when detecting the luminance gradient for each pixel block of 4 rows × 4 columns.

  In FIG. 4, each of the one-pixel delay elements D1 to D12 delays the supplied pixel data by one cycle of the sampling clock and outputs it. Each of the 1-line delay elements DH1 to DH3 delays the supplied pixel data by one horizontal scanning period and outputs it.

Therefore, according to the one-pixel delay elements D1 to D12 and the one-line delay elements DH1 to DH3 as shown in FIG. _4, it corresponds to the pixel G _(4,4) in the pixel block of 4 rows × 4 columns shown in FIG. When the pixel data PD _{(4, 4)} is supplied from the pixel data conversion circuit 1,
Pixel data PD _(4,1) corresponding to the pixel G _(4,1) from the one-pixel delay element D3,
Pixel data PD _(4,2) corresponding to the pixel G _(4,2) from the one-pixel delay element D2;
Pixel data PD _(4,3) corresponding to the pixel G _(4,3) from the one-pixel delay element D1;
Pixel data PD _(3,1) corresponding to the pixel G _(3,1) from the one-pixel delay element D6,
Pixel data PD _(3,2) corresponding to the pixel G _(3,2) from the one-pixel delay element D5,
Pixel data PD _(3,3) corresponding to the pixel G _(3,3) from the one-pixel delay element D4,
Pixel data PD _(3,4) corresponding to the pixel G _(3,4) from the one-line delay element DH1;
Pixel data PD _(2,1) corresponding to the pixel G _(2,1) from the one-pixel delay element D9,
Pixel data PD _(2,2) corresponding to the pixel G _(2,2) from the one-pixel delay element D8,
Pixel data PD _(2,3) corresponding to the pixel G _(2,3) from the one-pixel delay element D7,
Pixel data PD _(2,4) corresponding to the pixel G _(2,4) from the one-line delay element DH2;
Pixel data PD _(1,1) corresponding to the pixel G _(1,1) from the one-pixel delay element D12,
Pixel data PD _(1,2) corresponding to the pixel G _(1,2) from the one-pixel delay element D11,
Pixel data PD _(1,3) corresponding to the pixel G _(1,3) from the one-pixel delay element D10,
Pixel data PD _(1,4) corresponding to the pixel G _(1,4) from the one-line delay element DH3,
Each is output.

The subtractor SH1 includes pixel data PD _(1,1) corresponding to the pixel G _(1,1) as shown in FIG. 5 and a pixel G _{(1,2 )} adjacent to the right side of the pixel G _{(1,1). )} Is supplied to the adder AD1 as an absolute value of a difference from the pixel data PD _{(1, 2)} corresponding to. The subtractor SH2 includes pixel data PD _(1,2) corresponding to the pixel G _(1,2) as shown in FIG. 5, and a pixel G _{(1,3 )} adjacent to the right side of the pixel G _{(1,2). )} Is supplied to the adder AD1 as an absolute value of a difference from the pixel data PD _{(1, 3)} corresponding to the pixel data PD _{(1, 3)} . The subtractor SH3 includes pixel data PD _(1,3) corresponding to the pixel G _(1,3) as shown in FIG. 5 and a pixel G _{(1,4 )} adjacent to the right side of the pixel G _{(1,3). )} Is supplied to the adder AD1 as an absolute value of a difference from the pixel data PD _{(1, 4)} corresponding to the pixel data PD _{(1, 4)} . Differentiator SH4, the pixel G _{(2, 2} pixel data PD _(2,1) corresponding to the pixel G _(2,1) as shown in FIG. 5, adjacent to the right of the pixel G _{(2,1) )} Is supplied to the adder AD1 as an absolute value of a difference from the pixel data PD _{(2, 2)} corresponding to. The subtractor SH5 includes pixel data PD _(2,2) corresponding to the pixel G _(2,2) as shown in FIG. 5, and a pixel G _{(2,3 )} adjacent to the right side of the pixel G _{(2,2). )} Is supplied to the adder AD1 as an absolute value of a difference from the pixel data PD _(2,3) corresponding to. The subtractor SH6 includes pixel data PD _(2,3) corresponding to the pixel G _(2,3) as shown in FIG. 5, and a pixel G _{(2,4 )} adjacent to the right side of the pixel G _{(2,3). )} Is supplied to the adder AD1 as the absolute value of the difference from the pixel data PD _{(2, 4)} corresponding to the pixel data PD The differentiator SH7 includes pixel data PD _(3,1) corresponding to the pixel G _(3,1) as shown in FIG. 5, and a pixel G _{(3,2 )} adjacent to the right side of the pixel G _{(3,1). )} Is supplied to the adder AD1 as an absolute value of a difference from the pixel data PD _{(3, 2)} corresponding to the pixel data PD _{(3, 2)} . The subtractor SH8 includes pixel data PD _{(3, 2)} corresponding to the pixel G _{(3, 2)} as shown in FIG. 5 and a pixel G _{(3, 3)} adjacent to the right side of the pixel G ₍₃ , _2). supplied to the adder AD1 the absolute value of the difference of the pixel data PD _(3,3) corresponding _to). The differentiator SH9 includes pixel data PD _(3,3) corresponding to the pixel G _(3,3) as shown in FIG. 5 and a pixel G _{(3,4 )} adjacent to the right side of the pixel G _{(3,3). )} Is supplied to the adder AD1 as an absolute value of a difference from the pixel data PD _(3,4) corresponding to. The differentiator SH10 includes pixel data PD _(4,1) corresponding to the pixel G _(4,1) as shown in FIG. 5, and a pixel G _{(4,2 )} adjacent to the right side of the pixel G _{(4,1). )} Is supplied to the adder AD1 as an absolute value of a difference from the pixel data PD _{(4, 2)} corresponding to the pixel data PD. The subtractor SH11 includes pixel data PD _(4,2) corresponding to the pixel G _(4,2) as shown in FIG. 5 and a pixel G _{(4,3 )} adjacent to the right side of the pixel G _{(4,2). )} Is supplied to the adder AD1 as an absolute value of a difference from the pixel data PD _(4,3) corresponding to the pixel data PD _(4,3) . The differentiator SH12 includes pixel data PD _(4,3) corresponding to the pixel G _(4,3) as shown in FIG. 5, and a pixel G _{(4,4 )} adjacent to the right side of the pixel G _{(4,3). )} Is supplied to the adder AD1 as an absolute value of a difference from the pixel data PD _{(4, 4)} corresponding to the pixel data PD _{(4, 4)} .

The adder AD1 calculates the sum of the values supplied from each of the differentiators SH1 to SH12, and supplies this to the adder AD3 and the comparator CM1 as a horizontal luminance gradient signal Hg indicating the luminance gradient in the horizontal direction of the screen. . The comparator CM1 determines whether such horizontal brightness gradient or the value indicated by the signal Hg is greater than the reference horizontal gradient value T _H. At this time, when it is determined that the value indicated by the horizontal luminance gradient signal Hg is smaller than the reference horizontal gradient value T _H , the comparator CM1 performs logic indicating that the luminance gradient in the horizontal direction is small. A level 0 horizontal gradient detection signal HGD is generated. On the other hand, that if the value indicated by the horizontal luminance gradient signal Hg is determined to be larger than the reference horizontal gradient value T _H, the comparator CM1, the luminance gradient in the horizontal direction is larger A horizontal gradient detection signal HGD having a logic level 1 is generated. The comparator CM1 supplies the horizontal gradient detection signal HGD to the OR gate circuit OR.

The subtractor SV1 includes pixel data PD _(1,1) corresponding to the pixel G _(1,1) as shown in FIG. 5, and a pixel G _(2,1) adjacent to the pixel G _{( 1,1 ).} The absolute value of the difference from the pixel data PD _(2,1) corresponding to is supplied to the adder AD2. The subtractor SV2 includes pixel data PD _(1,2) corresponding to the pixel G _(1,2) as shown in FIG. 5, and a pixel G _{(2,2) immediately} below the pixel G _{(1,2 ).} The absolute value of the difference from the pixel data PD _{(2, 2)} corresponding to is supplied to the adder AD2. The subtractor SV3 includes pixel data PD _(1,3) corresponding to the pixel G _(1,3) as shown in FIG. 5, and a pixel G _(2,3) adjacent to the pixel G _{( 1,3 ).} The absolute value of the difference from the pixel data PD _(2,3) corresponding to is supplied to the adder AD2. The subtractor SV4 includes pixel data PD _(1,4) corresponding to the pixel G _(1,4) as shown in FIG. 5 and a pixel G _{(2,4) immediately} below the pixel G _{(1,4 ).} The absolute value of the difference from the pixel data PD _{(2, 4)} corresponding to is supplied to the adder AD2. The subtractor SV5 includes pixel data PD _(2,1) corresponding to the pixel G _(2,1) as shown in FIG. 5, and a pixel G _{(3,1) immediately} below the pixel G _{(2,1 ).} The absolute value of the difference from the pixel data PD _{(3, 1)} corresponding to is supplied to the adder AD2. The subtractor SV6 includes pixel data PD _(2,2) corresponding to the pixel G _(2,2) as shown in FIG. 5 and a pixel G _{(3,2) immediately} below the pixel G _{(2,2 ).} The absolute value of the difference from the pixel data PD _{(3, 2)} corresponding to is supplied to the adder AD2. The subtractor SV7 includes pixel data PD _(2,3) corresponding to the pixel G _(2,3) as shown in FIG. 5, and a pixel G _{(3,3) immediately} below the pixel G _{(2,3 ).} The absolute value of the difference from the pixel data PD _{(3, 3)} corresponding to is supplied to the adder AD2. Differentiator SV8 the pixel data PD _{(2, 4)} corresponding to the pixel G _{(2, 4)} as shown in FIG. 5, a pixel G adjacent beneath the pixel G _{(2,4) (3,4)} The absolute value of the difference from the pixel data PD _(3,4) corresponding to is supplied to the adder AD2. Differentiator SV9 the pixel data PD _{(3, 1)} corresponding to the pixel G _{(3, 1)} as shown in FIG. 5, a pixel G adjacent beneath the pixel G _{(3,1) (4,1)} The absolute value of the difference from the pixel data PD ₍₄ , ₁₎ corresponding to is supplied to the adder AD2. The subtractor SV10 includes pixel data PD _{(3, 2)} corresponding to the pixel G _{(3, 2)} as shown in FIG. 5 and a pixel G _{(4, 2) immediately} below the pixel G _{(3, 2).} The absolute value of the difference from the pixel data PD _{(4, 2)} corresponding to is supplied to the adder AD2. Differentiator SV11, the pixel data PD _(3,3) corresponding to the pixel G _(3,3) as shown in FIG. 5, a pixel G adjacent beneath the pixel G _{(3,3) (4,3)} The absolute value of the difference from the pixel data PD _(4,3) corresponding to is supplied to the adder AD2. The subtractor SV12 includes pixel data PD _(3,4) corresponding to the pixel G _(3,4) as shown in FIG. 5 and a pixel G _{(4,4) immediately} below the pixel G _{(3,4 ).} The absolute value of the difference from the pixel data PD _(4,4) corresponding to is supplied to the adder AD2.

The adder AD2 obtains the sum of the values supplied from the differentiators SV1 to SH12, and supplies this to the adder AD3 and the comparator CM2 as a vertical luminance gradient signal Vg indicating the luminance gradient in the screen vertical direction. . Comparator CM2 judges whether is larger than the value of the reference vertical gradient value T _V represented by a perpendicular direction brightness gradient signal Vg. In this case, if the value indicated by the vertical luminance gradients signal Vg is determined to be smaller than the reference vertical gradient value T _V, the comparator CM2 is logic indicating that the luminance gradient in the vertical direction is small A level 0 vertical gradient detection signal VGD is generated. On the other hand, that when the value represented by the vertical luminance gradient signal Vg is determined to be larger than the reference horizontal gradient value T _H, the comparator CM2, the luminance gradient in the vertical direction is large A vertical gradient detection signal VGD having a logic level 1 is generated. The comparator CM2 supplies the vertical gradient detection signal VGD to the OR gate circuit OR.

The adder AD3 supplies the addition result obtained by adding the horizontal luminance gradient signal Hg and the vertical luminance gradient signal Vg to the coefficient multiplier MPX. The coefficient multiplier MPX supplies the multiplication result obtained by multiplying the addition result by (1/2) to the comparator CM3 as an oblique luminance gradient signal Ng indicating the luminance gradient in the oblique direction of the screen. The comparator CM3 determines whether or not the value indicated by the diagonal luminance gradient signal Ng is larger than the reference diagonal gradient value T _N. At this time, when it is determined that the value indicated by the diagonal luminance gradient signal Ng is smaller than the reference diagonal gradient value T _N , the comparator CM3 performs logic indicating that the luminance gradient in the diagonal direction is small. A level 0 oblique gradient detection signal NGD is generated. On the other hand, when it is determined that the value indicated by the diagonal luminance gradient signal Ng is larger than the reference diagonal gradient value T _N , the comparator CM3 determines that the luminance gradient in the diagonal direction is large. An oblique gradient detection signal NGD of logic level 1 shown is generated. The comparator CM3 supplies the oblique gradient detection signal NGD to the OR gate circuit OR. The OR gate circuit OR has a logic indicating that the luminance gradient is large when at least one of the horizontal gradient detection signal HGD, the vertical gradient detection signal VGD, and the diagonal gradient detection signal NGD is at a logic level 1. The level 1 luminance gradient detection signal HD is supplied to the multi-gradation processing mode setting circuit 30. On the other hand, when the horizontal gradient detection signal HGD, the vertical gradient detection signal VGD, and the diagonal gradient detection signal NGD are all at the logic level 0, the luminance gradient detection signal HD at the logic level 0 indicating that the luminance gradient is small. Is supplied to the multi-gradation processing mode setting circuit 30.

That is, with the configuration shown in FIG. 4, the luminance gradient detection circuit 27 first sets each unit pixel block of 4 rows × 4 columns to each other in each of the vertical, horizontal, and diagonal directions within the unit pixel block. A total sum (Hg, Vg, Ng) of luminance differences between pixel data corresponding to adjacent pixels is obtained. Next, the luminance gradient detection circuit 27 determines, for each direction, whether or not the sum of the luminance differences is larger than the reference gradient values (T _H , T _V , T _N ). It is detected for each direction whether the luminance gradient in the block is large (HGD, VGD, NGD). Here, if the luminance gradient detection circuit 27 determines that the luminance gradient is large in at least one of the vertical direction, the horizontal direction, and the diagonal direction, the luminance gradient in the unit pixel block is determined. A luminance gradient detection signal HD of logical level 1 indicating that is large is generated. On the other hand, when it is determined that the luminance gradient is small in all the vertical, horizontal, and diagonal directions, the luminance gradient detection circuit 27 has a small luminance gradient in the unit pixel block. A luminance gradient detection signal HD having a logic level 0 indicating this is generated. The luminance gradient detection circuit 27 supplies the luminance gradient detection signal HD to the multi-gradation processing mode setting circuit 30.

  The multi-gradation processing mode setting circuit 30 operates the multi-gradation processing circuit 2 in [organizational dither processing priority mode] when the luminance gradient detection signal HD indicating that the luminance gradient is small is supplied. The selection signals S1 to S3 and the compressed bit number designation signals BS1 to BS3 to be generated are generated.

  In such a [systematic dither processing priority mode], the multi-gradation processing mode setting circuit 30 supplies, for example, a compression bit number designating signal BS1 for designating 2 bits as the number of compression bits to the random dither processing circuit 21 and a compression bit. A compressed bit number designating signal BS3 designating 4 bits as a number is supplied to the systematic dither processing circuit 26. The multi-gradation processing mode setting circuit 30 supplies the selector 22 with a selection signal S1 for selecting the line dither processing pixel data LDD output from the random dither processing circuit 21. Further, the multi-gradation processing mode setting circuit 30 supplies the selector 24 with a selection signal S2 for selecting the line dither processing pixel data LDD output from the selector 22, and the tissue output from the tissue dither processing circuit 26. A selection signal S3 for selecting the dither processing pixel data CDD is supplied to the selector 23.

  With this control operation, in the systematic dither processing priority mode, the multi-gradation processing circuit 2 performs random dither processing for compressing the pixel data PD by 2 bits (random dither processing circuit 21). The random dither processing result is subjected to a systematic dither process for compressing 4 bits (systematic dither processing circuit 26). As a result, as shown in FIG. 6A, the 10-bit pixel data PD is compressed by 2 bits by the random dither process and by 4 bits by the systematic dither process. Multi-gradation pixel data MPD is generated.

  On the other hand, when the luminance gradient detection signal HD indicating that the luminance gradient is large is supplied, the multi-gradation processing mode setting circuit 30 performs the multi-gradation processing mode indicated by the multi-gradation mode designation signal MOD. The selection signals S1 to S3 and the compressed bit number designation signals BS1 to BS3 to be used to operate the multi-gradation processing circuit 2 are generated.

  The operation will be described below by taking, as an example, the case where the multi-gradation processing mode indicated by the multi-gradation mode designation signal MOD is [error diffusion processing priority mode] and [random dither processing priority mode].

  In the [error diffusion processing priority mode], the multi-grayscale processing mode setting circuit 30 supplies, for example, a compression bit number specifying signal BS1 that specifies 2 bits as the compression bit number to the random dither processing circuit 21 and the compression bit number The compressed bit number designation signal BS2 designating 4 bits is supplied to the error diffusion processing circuit 25. The multi-gradation processing mode setting circuit 30 supplies a selection signal S1 for selecting the line dither processing pixel data LDD output from the random dither processing circuit 21 to the selector 22 and is output from the error diffusion processing circuit 25. The selector 23 is supplied with a selection signal S3 for selecting the error diffusion processed pixel data ED.

  With this control operation, in the error diffusion processing priority mode, the multi-gradation processing circuit 2 performs random dither processing for compressing the pixel data PD by 2 bits (random dither processing circuit 21). The random dither processing result is subjected to error diffusion processing for further compression of 4 bits (error diffusion processing circuit 25). As a result, as shown in FIG. 6B, the 10-bit pixel data PD is compressed by 2 bits by the random dither process and by 4 bits by the error diffusion process. Multi-gradation pixel data MPD is generated.

  In [Random Dither Processing Priority Mode], the multi-gradation processing mode setting circuit 30 supplies, for example, a compression bit number specifying signal BS1 specifying 4 bits as the number of compression bits to the random dither processing circuit 21 and the number of compression bits. The compressed bit number designation signal BS3 designating 2 bits is supplied to the systematic dither processing circuit 26. The multi-gradation processing mode setting circuit 30 supplies the selector 22 with a selection signal S1 for selecting the line dither processing pixel data LDD. Further, the multi-gradation processing mode setting circuit 30 supplies the selector 24 with a selection signal S2 for selecting the line dither processing pixel data LDD output from the selector 22, and the tissue output from the tissue dither processing circuit 26. A selection signal S3 for selecting the dither processing pixel data CDD is supplied to the selector 23.

  With this control operation, in the random dither processing priority mode, the multi-gradation processing circuit 2 performs random dither processing for compressing 4 bits on the pixel data PD (random dither processing circuit 21). A systematic dither process for further compressing the random dither process result by 2 bits is performed (systematic dither processing circuit 26). As a result, as shown in FIG. 6C, the 10-bit pixel data PD is compressed by 4 bits by the random dither process and by 2 bits by the systematic dither process. Multi-gradation pixel data MPD is generated.

  As described above, the multi-gradation processing circuit 2 shown in FIG. 2 is based on the pixel data for each pixel based on the input video signal, and the luminance gradient in the pixel block for each unit pixel block is a predetermined reference gradient. The multi-gradation processing method is changed based on the determination result.

  For example, the multi-gradation processing circuit 2 performs a tissue dither process when a video signal corresponding to a picture with a luminance gradient smaller than a predetermined reference gradient, that is, a so-called luminance high and low width is small. The prioritized multi-gradation process as shown in FIG.

Here, for each unit pixel block of 4 rows × 4 columns, for example, the unit dither processing using the dither values A _{(1,1) to} A _(4,4) as shown in FIG. When applied to the pixel data PD as shown in FIG. 7B where the luminance gradient in the block is small, multi-gradation pixel data MPD as shown in FIG. 7C is generated. At this time, the average luminance in the unit pixel block in the multi-gradation pixel data MPD shown in FIG. 7C is “8”, and the unit pixel block based on the pixel data PD as shown in FIG. It becomes the same as the average luminance at. On the other hand, with respect to the pixel data PD as shown in FIG. 7D where the luminance gradient in the unit pixel block is relatively large, the dither values A _{(1,1) to} A ₍ as shown in FIG. _When the tissue dither processing using ( _{4, 4)} is performed, multi-gradation pixel data MPD as shown in FIG. 7 (e) is generated. However, the average luminance in the unit pixel block in the multi-gradation pixel data MPD shown in FIG. 7E is “17”, and in the unit pixel block based on the pixel data PD as shown in FIG. The brightness level is different from the average brightness “15”, and a correct image may not be displayed.

  Therefore, when pixel data PD having a relatively large luminance gradient in the unit pixel block as shown in FIG. 7D is supplied, error diffusion instead of the above-described system dither processing is performed as multi-gradation processing. The multi-gradation processing circuit 2 is operated in an error diffusion processing priority mode as shown in FIG. Further, when such pixel data PD having a relatively large luminance gradient is supplied, the random dither processing priority mode as shown in FIG. 6C, in which the number of compressed bits in the system dither processing is reduced, is set. Thus, the multi-gradation processing circuit 2 may be operated. Note that in the random dither processing priority mode shown in FIG. 6C, the number of compression bits in the random dither processing is increased by an amount corresponding to the reduction in the number of compression bits in the system dither processing from 4 bits to 2 bits. Bit compression for 6 bits is performed in the same way as when the systematic dither processing priority mode as shown in FIG.

  In short, in the multi-gradation processing circuit 2, a processing method (organization dither processing, error diffusion) adopted as multi-gradation processing according to the determination result of whether or not the luminance gradient is larger than a predetermined reference gradient. By changing the processing) or changing the number of compression bits in the multi-gradation processing, periodic flicker and noise are avoided.

It is a figure which shows schematic structure of the display apparatus by this invention. It is a figure which shows the structure of the multi-gradation processing circuit 2 mounted in the display apparatus shown by FIG. It is a figure for demonstrating the error diffusion process by the error diffusion process circuit 25 shown by FIG. FIG. 3 is a diagram illustrating an example of a circuit configuration of a luminance gradient detection circuit 27 illustrated in FIG. 2. It is a figure which shows the unit pixel block of 4 rows x 4 columns. It is a figure which shows the bit compression form for every mode in the multi-gradation processing circuit 2. It is a figure which shows an example of the organization dither processing result by the organization dither processing circuit.

Explanation of symbols

2 Multi-gradation processing circuit 21 Line dither processing circuit 25 Error diffusion processing circuit 26 Systematic dither processing circuit 27 Luminance gradient detection circuit 30 Multi-gradation processing mode setting circuit

Claims (4)

A display device having a plurality of display cells that carry pixels, and multi-gradation processing means for performing multi-gradation processing on pixel data for each pixel based on a video signal to obtain multi-gradation pixel data; Display driving means for causing the display cell to emit light with luminance according to multi-gradation pixel data,
A luminance gradient detecting means for detecting whether or not a luminance gradient based on the pixel data is larger than a predetermined reference gradient for each unit pixel block in the display device;
The multi-gradation processing unit adds a dither value corresponding to each pixel position in the unit pixel block to the pixel data corresponding to the pixel position when the luminance gradient is smaller than the reference gradient. The multi-gradation pixel data is obtained by performing a first multi-gradation process, which is a systematic dither process, on the pixel data, and the first gradient is obtained when the luminance gradient is larger than the reference gradient . A display device characterized in that the multi-gradation pixel data is obtained by subjecting the pixel data to a second multi-gradation process which is a systematic dither process in which the number of compression bits is smaller than the multi-gradation process. A display device having a plurality of display cells that carry pixels, and multi-gradation processing means for performing multi-gradation processing on pixel data for each pixel based on a video signal to obtain multi-gradation pixel data; Display driving means for causing the display cell to emit light with luminance according to multi-gradation pixel data,
A luminance gradient detecting means for detecting whether or not a luminance gradient based on the pixel data is larger than a predetermined reference gradient for each unit pixel block in the display device;
The multi-gradation processing unit adds a dither value corresponding to each pixel position in the unit pixel block to the pixel data corresponding to the pixel position when the luminance gradient is smaller than the reference gradient. The multi-gradation pixel data is obtained by subjecting the pixel data to a first multi-gradation process, which is a systematic dither process, and when the luminance gradient is larger than the reference gradient, an error diffusion process is performed. the multi-grayscale pixel data characteristics and be Lud Isupurei device to obtain by the second multi-grayscale process is performed on the pixel data is. A display device having a plurality of display cells that carry pixels, and multi-gradation processing means for performing multi-gradation processing on pixel data for each pixel based on a video signal to obtain multi-gradation pixel data; Display driving means for causing the display cell to emit light with luminance according to multi-gradation pixel data,
A luminance gradient detecting means for detecting whether or not a luminance gradient based on the pixel data is larger than a predetermined reference gradient for each unit pixel block in the display device;
The multi-gradation processing unit adds a dither value corresponding to each pixel position in the unit pixel block to the pixel data corresponding to the pixel position when the luminance gradient is smaller than the reference gradient. The multi-gradation pixel data is obtained by performing a first multi-gradation process, which is a systematic dither process, on the pixel data, and the first gradient is obtained when the luminance gradient is larger than the reference gradient. The multi-gradation pixel data is obtained by performing a systematic dither processing process in which the number of compression bits is smaller than that in the multi-gradation process and a random dither process for adding a random dither value to the pixel data, respectively. features and be Lud Isupurei device. The luminance gradient detecting means includes means for detecting a horizontal luminance gradient in the horizontal direction in the unit pixel block, means for detecting a vertical luminance gradient in the vertical direction, and means for detecting an oblique luminance gradient in the oblique direction,
The multi-gradation processing unit is configured to perform the second multi-gradation processing on the pixel data when at least one of the horizontal luminance gradient, the vertical luminance gradient, and the diagonal luminance gradient is larger than the reference gradient. When the gradation processing is performed, and when all of the horizontal luminance gradient, the vertical luminance gradient, and the oblique luminance gradient are smaller than the reference gradient, the first multi-gradation processing is performed on the pixel data. display device according to any one of claims 1-3, characterized in that the subjecting.

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