JP4770064B2 - IPM circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an intelligent power module (IPM) circuit used for an inverter or the like.
[0002]
[Prior art]
FIG. 3 shows an inverter main circuit diagram using this type of IPM.
In the figure, reference numeral 1 denotes a DC power source (in the case of AC input, a rectifier + electrolytic capacitor configuration), and 2 denotes an IPM. In this IPM 2, six sets of power semiconductor elements 3 such as IGBTs and anti-parallel connected diodes 4 are provided for six circuits, and each element 3 has a gate drive circuit 5 for driving the gate, and Protection circuits 6 are provided for protecting the element 3 from overcurrent and overheating (only one of them is shown in FIG. 3). The gate drive circuit 5 turns on and off the element 3 by an external signal L1, and outputs a failure signal L2 when an overcurrent flows through the protection circuit 6 or overheats.
[0003]
FIG. 4 shows a specific example of the gate driver. This can be said to be an IPM in which the protection circuit is not shown.
S1 is a MOSFET (metal oxide film type field effect transistor) that also serves as an on-gate resistance. When this MOSFET is turned on, the IGBT element 3 is turned on. S2 is a MOSFET that also serves as a gate resistance for turning off. When this MOSFET is turned on, the element 3 is turned off. D1 is a delay circuit that delays the rise of the signal L1, and D2 itself is a rise delay circuit. Since the inverter gate I2 is provided in the previous stage, the delay circuit D1, D1 is a circuit that delays the fall of the signal L1. D2 is provided in order to prevent S1 and S2 from being turned on simultaneously and to prevent malfunction due to noise. Reference numeral 7 denotes a power source for the gate drive circuit.
[0004]
[Problems to be solved by the invention]
Normally, the gate drive circuit and protection circuit of the IPM are configured by an IC (integrated circuit). When the delay circuits D1, D2 and the like are configured by an IC, generally an individual difference variation of several tens of percent occurs with respect to a design value. In addition to the buffer circuit B1 shown in the figure, various circuits are connected between the input of the IPM and the last stage switch elements (S1, S2) for driving the switch elements. There are also variations. Therefore, when the IPM is connected in parallel and operated by inputting the signal L1 in parallel, the switching time difference between the switch elements connected in parallel increases due to delay time variations of various circuits, resulting in current imbalance during switching. However, overcurrent detection is performed at an overcurrent detection level or below, and a thermal concentration phenomenon occurs in a specific element due to an increase or imbalance in switching loss responsibilities.
[0005]
The above problem can be solved by short-circuiting the gate terminals of the IPMs that are juxtaposed, but the upper and lower arms of the gate drive switch element are short-circuited between the gate drive circuits that are juxtaposed, and the power consumption of the gate drive circuit is reduced The problem of becoming larger occurs.
Accordingly, an object of the present invention is to prevent an erroneous detection operation and a heat concentration phenomenon to a specific element by eliminating imbalance at the time of switching, and to reduce power consumption of the IC in the IPM.
[0006]
[Means for Solving the Problems]
In order to solve such problems, in the invention of claim 1, in an IPM circuit formed by connecting in parallel an IPM (intelligent power module) including at least a power module and a drive circuit for driving the power module,
Comparison between the gates of the power modules connected in parallel with each other by a short-circuit line and the drive circuit for detecting the gate potential of the power module or the current flowing through the short-circuit line and comparing the detection value with a set value Means, logical operation means for performing a logical product operation of the comparison result and a command signal to the power module, and switching elements for turning on and off the power module based on an output from the logical product operation means , respectively. The on / off states of the switch elements are the same between the IPM circuits connected in parallel.
[0007]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a circuit diagram illustrating the principle of the present invention.
In this configuration, the gate terminals of the IGBTs connected in parallel are short-circuited by the short-circuit line 8. It goes without saying that the IGBT gate terminals can be short-circuited via a resistor instead of short-circuiting the short-circuit wire 8 or via a series circuit of a resistor and a capacitor.
[0008]
Figure 2 is a circuit diagram showing a form of implementation of the present invention.
If there is a variation in the signal transmission time in the gate drive circuit between the A circuit side and the B circuit side in FIG. 1, the switching time of the final stage switch elements (S1A, S2A, S1B, S2B) will vary. For example, if the transmission time on the A circuit side is shorter when the IGBT is turned off, a period (transmission time difference) in which the switch elements S2A and S1B are simultaneously turned on is generated. During this period, the power supply 7 to S1B, the short circuit line 8, A short-circuit current between the upper and lower arms flows through S2A, resulting in an increase in power consumption.
[0009]
FIG. 2 adds AND gates A1A to A4A, OR gates O1A and O2A, set-reset flip-flops F1A and F2A, comparators 91A and 92A, etc., to the A circuit side of the circuit of FIG. It is composed. The B circuit side is configured in the same manner as described above.
The comparator 91A compares the gate potential VG with the reference voltage V1A. This reference voltage V1A is determined based on the gate potential VG when S1A and S2B or S1B and S2A are simultaneously turned on (for example, the gate when S1A and S2B or S1B and S2A are simultaneously turned on). When the potential VG is 7.5V, it is set to 7.5V or less). The AND gate A1A becomes active when the output of the comparator 91A and the signal L1 are low (L) and S1A is an on command, and sets F1A. This state can be said to be a state in which the transmission time of the OFF command on the B circuit side is short and the upper and lower arm short-circuit phenomenon in which S2B and S1A are turned ON in response to the OFF command of the signal L1 is detected. After this state is detected by the setting of F1A, the S1A is forcibly turned off by the AND gates A2A and O2A, and the S2A is turned on to make the switching state the same as the S1B and S2B on the B circuit side. The upper and lower arm short circuit phenomenon is eliminated.
[0010]
Similarly, the AND gate A3A becomes active when the output of the comparator 92A is high (H), the signal L1 is H, and the command of S2A is an on command, and the flip-flop F2A, the OR gate O1A, and the AND gate A4A The on-command transmission time on the circuit side is short, and the state in which S1B and S2A are on with respect to the on-command of the signal L1 is detected. After the detection, S1A is forcibly turned on and S2A is turned off.
In addition, when the signal transmission time on the A circuit side is short, the B circuit side operates.
In addition, as a detection method of the upper and lower arm short circuit phenomenon of the final stage switch element of the gate drive circuit in the IPM, the detection is made from the gate voltage of the IGBT in the above. It is also possible to detect that a short circuit has occurred when the detected value is equal to or greater than a predetermined value.
[0011]
【The invention's effect】
According to this invention, IGBT being driven in parallel by the parallel of IPM, since the same potential driven by short-circuit between the gate terminals, the switching waveform is almost the same. As a result, the loss increases and unnecessary overcurrent detection by the imbalance at the time of switching, not only can eliminate the overheat detection phenomena, since the upper and lower arm short circuit phenomenon in the gate drive circuit is eliminated, consumption of IGBT drive IC Electric power can be reduced.
[Brief description of the drawings]
FIG. 1 is a configuration diagram for explaining the principle of the present invention;
2 is a block diagram showing a form of implementation of the present invention.
FIG. 3 is a configuration diagram showing a conventional example of an inverter using an IPM.
4 is a circuit diagram showing an example of the gate drive circuit of FIG. 3;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... DC power supply, 2 ... IPM (intelligent power module) circuit, 3 ... IGBT, 4 ... Diode, 5 ... Gate drive circuit, 6 ... Protection circuit, 7 ... Power supply for gate drive circuit, 8 ... Short circuit wire, 91A, 92A 91B, 92B... Comparator, B1, B1A, B1B... Buffer circuit, I1, I2, I1A, I2A, I1B, I2B... Inverter gate, D1A, D2A, D1B, D2B. Final stage switch element, A1A to A4A ... AND gate, O1A, O2A, O1B, O2B ... OR gate.

Claims (1)

In an IPM circuit formed by connecting in parallel an IPM (intelligent power module) having at least a power module and a drive circuit for driving the power module,
Comparison between the gates of the power modules connected in parallel with each other by a short-circuit line and the drive circuit for detecting the gate potential of the power module or the current flowing through the short-circuit line and comparing the detection value with a set value Means, logical operation means for performing a logical product operation of the comparison result and a command signal to the power module, and switching elements for turning on and off the power module based on an output from the logical product operation means , respectively. An IPM circuit characterized in that the on / off states of the switch elements are made to be the same between the IPM circuits connected in parallel.

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