JP4770877B2 - DA converter - Google Patents

Description

  The present invention relates to a DA converter (digital / analog converter) for converting a digital signal into an analog signal.

  In digital audio equipment, as a DA converter that converts a digitized acoustic signal into an analog signal, for example, a ladder resistance type DA converter, an integral type DA converter, and the like are known and used. These known DA converters simply convert each sampling value (digital value) of a digital signal that has been sampled and digitized discretely into an analog value. Therefore, the output signal waveform is a stepped waveform and includes an unnecessary high-frequency component not included in the original signal. For this reason, in general, a smooth analog signal is obtained by providing an analog low-pass filter after the DA converter to remove unnecessary high-frequency components.

  However, this DA conversion method has a problem that a delay is caused by the phase characteristics of the analog low-pass filter and a waveform distortion such as overshoot occurs, thereby reducing the quality of reproduced sound.

  Conventionally, with respect to this problem, as disclosed in Japanese Patent No. 3134403, the staircase-like first analog signal DA-converted in real time for the audio data of one channel and the first analog signal. By generating a staircase-shaped second analog signal delayed by one sampling time and adding to the second analog signal while integrating the level difference between the first and second analog signals in each sampling period, There has been proposed a DA converter including a signal processing circuit for outputting an analog signal obtained by smoothly connecting digital signal sampling values as a DA conversion signal.

  In the DA converter described in the above-mentioned patent publication, a DA converter circuit is provided in front of the signal processing circuit, and the first analog signal and the second analog signal are relatively compared with each other by a digital filter integrated circuit. A multi-bit DAC is used because it can be easily obtained. However, this multi-bit DAC generally has a problem that the unit price is high. When the number of channels of audio data for DA conversion increases, a multi-bit DAC twice as many as the number of channels is required, which increases the circuit size. There was a problem that the cost increased.

  Accordingly, the applicant of the present application has proposed a DA converter that employs a one-bit DAC having a relatively low unit price in place of the multi-bit DAC in Japanese Patent No. 3770219 to realize a reduction in circuit size and cost.

  FIG. 11 is a configuration diagram of a DA converter using a one-bit DAC in Japanese Patent No. 3770219. According to the figure, the DA converter 50 includes a serial data format conversion circuit 51 (hereinafter referred to as “SDF conversion circuit 51”), a one-bit DA conversion circuit 52, and an analog signal processing circuit 53 (hereinafter referred to as “ASP circuit 53”). ").

  The SDF conversion circuit 51 separates a digital audio signal input in a serial data format digitized from a digital sound source such as a CD (Compact Disc) into L-channel audio data and R-channel audio data, and outputs each channel. The audio data is converted into data in a format that can be DA-converted by the one-bit DA converter circuit 52.

  Examples of the digital audio signal input in the serial data format include an I2S mode digital audio signal. As shown in FIG. 12, the I2S mode digital audio signal includes audio data DATA (hereinafter referred to as a DATA signal) obtained by mixing L-channel audio data and R-channel audio data, and word data of the DATA signal. A word clock LRCK (hereinafter referred to as LRCK signal) for identification and a bit clock BCLK (hereinafter referred to as BCLK signal) for identifying bit data of the audio data DATA are configured.

  More specifically, the DATA signal is a series of serial data (DL1 / DR1, DL2 / DR2, data) in which L channel data and R channel data DRi at the same sampling position i are paired and each pair is arranged in the sampling order. ... DLm / DRm). The data DLi and DRi are each composed of n-bit data, and this n-bit data corresponds to 1-word data.

  The LRCK signal is a clock having one cycle of the word data DLi / DRi of the DATA signal. In FIG. 12, the L level period of the LRCK signal is synchronized with the L channel word data DLi of the DATA signal, and the LRCK signal The H level period is synchronized with the R channel word data DRi of the DATA signal. The BCLK signal is a clock synchronized with the bit data of the DATA signal.

  FIG. 13 is a block diagram showing a specific circuit configuration of the SDF conversion circuit 51. The SDF conversion circuit 51 includes two AND circuits 61 and 62, two inversion circuits 63 and 64, three delay circuits 65, 66 and 67, two switch circuits 68 and 69, and three latch circuits 70. , 71, 72.

  With the above configuration, the SDF conversion circuit 51 uses the LRCK signal of the digital audio signal in the I2S mode and the L channel word data DLi (i = 1, 2,... M) of the DATA signal and the R channel word data DRi (i = 1). , 2,..., M), and for both channels, word data DLi ′, DRi delayed by ½ time of one cycle T of the LRCK signal (corresponding to the sampling cycle T of the digital signal) for each word data. 'Is generated, the word data DLi' is inserted between the word data DLi and the word data DLi + 1 and sequentially output, and the word data DRi 'is inserted between the word data DRi and the word data DRi + 1. And output sequentially.

  That is, every time the L-channel word data DL1, DL2,... DLm are extracted, the SDF conversion circuit 51 generates word data DLi ′ delayed by T / 2 for each word data DLi. It is output after the word data DLi. Since the content of the word data DLi ′ is the same as that of the word data DLi, the data consisting of the word data strings DL1 ′, DL2 ′,... DLm ′ is the same as the data consisting of the original word data strings DL1, DL2,. The data is phase delayed by T / 2. Therefore, from the L channel output terminal OUT1 of the SDF conversion circuit 51, a DATA 'signal including the word data strings DL1, DL1, DL2, DL2,... DLi, DLi, DLi + 1, DLi + 1,. Similarly, from the R channel output terminal OUT2 of the SDF conversion circuit 51, a DATA 'signal including word data strings DR1, DR1, DR2, DR2,... DRi, DRi, DRi + 1, DRi + 1,.

  Returning to FIG. 11, the one-bit DA conversion circuit 52 converts the L-channel and R-channel DATA ′ signals (digital signals) into analog signals. The one-bit DAC 52 </ b> L and the R-channel that convert the L-channel digital signals. And a one-bit DAC conversion circuit 52R for converting the digital signal.

  More specifically, the one-bit DA conversion circuit 52 converts the digital signal input from the SDF conversion circuit 51 into an analog signal serially for each bit and outputs the analog signal. The one-bit DAC 52L receives the DATA ′ signal, the LRCK signal, and the BCLK signal, which are composed of the L-channel word data strings DL1, DL1, DL2, DL2,..., DLi, DLi,. The DAC 52R is supplied with the DATA ′ signal, the LRCK signal, and the BCLK signal, which are composed of the R channel word data strings DR1, DR1, DR2, DR2,..., DRi, DRi,.

  The one-bit DAC 52L has audio data L (T) consisting of the original word data DLi sequence from the DATA ′ signal and audio data L (-) consisting of the word data DLi ′ sequence delayed by T / 2 from the audio data L (T). T) and the audio data L (T), L (-T) are serially converted into analog signals L (t), L (-t) for each bit and output to the ASP circuit 53. The one-bit DAC 52R has the same configuration as the one-bit DAC 52L, and converts the audio data R (T) and R (-T) into analog signals R (t) and R (-t) serially for each bit. The data is output to the ASP circuit 53.

  The ASP circuit 53 outputs an analog signal obtained by smoothly connecting the sampling values of the output signal of the one-bit DA conversion circuit 52 as a DA conversion signal (analog audio signal), and the ASP circuit 53L is supplied from the one-bit DAC 52L. The L channel analog signals L (t) and L (-t) are processed, and the ASP circuit 53R processes the R channel analog signals R (t) and R (-t).

  Here, in the above configuration, the SDF conversion circuit 51 and the one-bit DA conversion circuit 52 are configured by, for example, a PLD (Programmable Logic Device) whose internal logic circuit can be changed for the convenience of the manufacturer's design. PLD has the advantage that the design cost can be reduced because the logic circuit can be changed at the design stage, but the circuit scale and component cost increase compared to general low-cost general-purpose logic ICs. There was a problem such as.

Japanese Patent No. 3134403 Japanese Patent No. 3770219

  The present invention has been conceived under the above circumstances, and provides a DA converter capable of further simplifying the circuit configuration and reducing the cost as compared with a conventional DA converter. Let that be the issue.

  In order to solve the above problems, the present invention takes the following technical means.

  A DA converter provided by the present invention is for identifying array data obtained by alternately arranging L-channel audio data and R-channel audio data serially in word units, and word data of the array data. A digital audio signal composed of a word clock and a bit clock for identifying bit data of the array data is input, and the first audio data as the input array data is delayed by one sampling time. Audio data generating means for generating two audio data; and separating the first audio data from the audio data generating means into L-channel first audio data and R-channel first audio data; The first channel of the L channel using The D / A data is serially DA-converted for each bit to generate a first analog signal, and the R-channel first audio data is serially DA-converted for each bit using the bit clock to generate a second analog signal. A first one-bit DA converter for generating a signal; and the second audio data from the audio data generator is separated into L-channel second audio data and R-channel second audio data; The second audio data of the L channel is serially DA-converted bit by bit using a clock to generate a third analog signal, and the second audio data of the R channel is converted bit by bit using the bit clock. The second one bit that generates a fourth analog signal by serial DA conversion Between sampling points using an A conversion means, a first analog signal generated by the first one-bit DA conversion means, and a third analog signal generated by the second one-bit DA conversion means A first analog signal processing unit that generates an analog signal having the signal levels connected to each other and outputs the analog signal as an L-channel analog audio signal; a second analog signal generated by the first one-bit DA conversion unit; A second analog signal that generates an analog signal obtained by connecting signal levels between sampling points using the fourth analog signal generated by the second one-bit DA converter and outputs the analog signal as an R-channel analog audio signal. And a signal processing means (claim 1).

  In the DA converter according to the present invention, the audio data generation means may include a delay circuit that delays the array data by a period of one cycle of the word clock to generate the second audio data. ).

  In the DA converter according to the present invention, the delay circuit may be a shift register.

  In the DA converter according to the present invention, each of the first one-bit DA conversion means and the second one-bit DA conversion means is constituted by one integrated circuit mounted on one substrate, and The integrated circuit constituting the one-bit DA converting means is mounted on one side of the substrate, and the integrated circuit constituting the second one-bit DA converting means is mounted on the other side of the substrate. (Claim 4).

  According to the above configuration, the array data of the input digital audio signal is generated by the audio data generation means as the first audio data and the second audio data delayed by one sampling time from the first audio data. The The first audio data is separated into L-channel audio data and R-channel audio data by the first one-bit DA conversion means, which are serially DA-converted for each bit, and the first analog signal and A second analog signal is generated. The second audio data is separated into L-channel audio data and R-channel audio data by the second one-bit DA conversion means, which are serially DA-converted for each bit, and the third analog data A signal and a fourth analog signal are generated.

  Then, using the first analog signal and the third analog signal, the first analog signal processing means generates and outputs an L-channel analog audio signal connecting the signal levels between the sampling points. Further, the second analog signal processing means generates and outputs an R channel analog audio signal that connects the signal levels between the sampling points using the second analog signal and the fourth analog signal.

  As described above, the first one-bit DA conversion means and the second one-bit DA conversion means separate the L-channel audio data and the R-channel audio data, respectively, which are serially DA for each bit. Since the analog signal is generated by conversion, the audio data generation means in the previous stage can be configured to include, for example, a delay circuit that delays the first audio data and the first audio data by one sampling time. Therefore, since the audio data generation means can be configured by, for example, a general-purpose inexpensive logic IC, the circuit configuration is simplified compared to a conventional SDF conversion circuit (corresponding to the audio data generation means) using PDL. This can reduce the cost.

  Other features and advantages of the present invention will become more apparent from the detailed description given below with reference to the accompanying drawings.

  Hereinafter, preferred embodiments of the present invention will be specifically described with reference to the accompanying drawings.

  FIG. 1 is a block diagram of a DA converter according to the present invention.

  The DA converter 1 includes an audio data generation circuit 2, a one-bit DA conversion circuit 3, and an analog signal processing circuit 4 (hereinafter referred to as “ASP circuit 4”).

  The audio data generation circuit 2 converts the first audio data A (T) and the first audio data A (T) from the DATA signal of the digital audio signal (see FIG. 12) input in the serial data format for one sampling time. The second audio data A (-T) delayed by T is generated, and the first and second audio data A (T), A (-T) are output to the one-bit DA conversion circuit 33. is there. A digital audio signal digitized from a digital sound source such as a CD (Compact Disc) is transmitted to the audio data generation circuit 2 and transmitted in, for example, an I2S mode of a real data format.

  The one-bit DA conversion circuit 3 separates the audio data from the audio data generation circuit 2 into an L channel signal and an R channel signal and converts them into an analog signal. The one-bit DA conversion circuit 3 converts the digital signal of the first audio data A (T) into an analog signal, and converts the digital signal of the second audio data A (-T) into an analog signal. And a one-bit DAC 31B.

  From the one-bit DAC 31A, the first audio data A (T) is D / A converted, and an analog signal L (t) for the L channel and an analog signal R (t) for the R channel are output. Also, from the one-bit DAC 31B, the second audio data A (-T) is D / A converted, and the L channel analog signal L (-) is obtained by delaying the L channel analog signal L (t) by one sampling time. t) and an analog signal R (-t) for the R channel obtained by delaying the analog signal R (t) for the R channel by one sampling time.

  The ASP circuit 4 processes the L channel analog signals L (t) and L (-t) from the one-bit DA conversion circuit 3 and the R channel analog signals R (t) and R (-t), respectively. Thus, an analog signal obtained by smoothly connecting the sampling values of the digital signal is output as a DA conversion signal (analog audio signal).

  The ASP circuit 4 processes the L-channel analog signal L (t) from the one-bit DAC 31A and the L-channel analog signal L (-t) from the one-bit DAC 31B, and outputs an L-channel analog audio signal. An ASP circuit that processes the circuit 41L, an R channel analog signal R (t) from the one-bit DAC 31A, and an R channel analog signal R (-t) from the one bit DAC 31B and outputs an R channel analog audio signal 41R.

  As described above, the DA converter 1 generates and outputs an L-channel analog audio signal and an R-channel analog audio signal from the DATA signal of the digital audio signal input in the serial data format. In the present invention, the configuration of the audio data generation circuit 2 is more simplified than the configuration of the conventional SDF conversion circuit 51 (corresponding to the audio data generation circuit 2). Details will be described below.

  FIG. 2 is a block diagram showing a specific circuit configuration of the audio data generation circuit 2. The audio data generation circuit 2 includes a delay circuit 21, three first to third latch circuits 22, 23 and 24, and an inverting circuit 25.

  The audio data generation circuit 2 converts the first word data DLi / DRi as the first audio data A (T) from the DATA signal and the first word data DLi / DRi into one cycle T (digital signal of the LRCK signal). A second word data string DLi ′ / DRi ′ as second audio data A (−T) delayed by a time corresponding to the sampling period T is generated and output to the one-bit DA conversion circuit 3 To do.

  According to FIG. 2, the I2S mode DATA input terminal IN <b> 1 of the audio data generation circuit 2 is connected to the delay circuit 21 and to the first latch circuit 22. The output terminal of the delay circuit 21 is connected to the second latch circuit 23. The LRCK input terminal IN2 in the I2S mode is connected to the third latch circuit 24.

  The output terminal of the first latch circuit 22 is connected to the first output terminal OUT1, and the output terminal of the second latch circuit 23 is connected to the second output terminal OUT2. The output terminal of the third latch circuit 24 is connected to the LRCK output terminal OUT3. The BCLK input terminal IN3 in the I2S mode is connected to the BCLK output terminal OUT4 through the inverting circuit 25. The delay circuit 21, the first to third latch circuits 22, 23, and 23 are used to adjust the data output timing. 24 are connected to each other.

  FIG. 3 is a diagram illustrating data output by signal processing based on the LRCK signal in the audio data generation circuit 2. In FIG. 3, “No” indicates a serial number assigned to each cycle of the LRCK signal. “LRCK” is an LRCK signal, “Low” indicates an L level state, and “High” indicates an H level state. “DATA” indicates a DATA signal. “A (T)” indicates the first audio data signal A (T) output from the first output terminal OUT1, and “A (−T)” indicates the second audio data signal output from the second output terminal OUT2. Audio data signal A (-T).

  The operation of the audio data generation circuit 2 will be described with reference to FIGS. 2 and 3. A DATA signal input from the DATA input terminal IN1 in the I2S mode is input to the first latch circuit 22 and also to the delay circuit 21. Entered. The delay circuit 21 generates the second word data DLi ′ / DRi ′ delayed by 1T by shifting each bit data constituting the first word data DLi / DRi as the DATA signal using the BCLK signal. . The delay circuit 21 is specifically composed of a shift register. For example, when the first word data DLi / DRi is 64-bit data, the delay circuit 21 is composed of a 64-bit shift register.

  The first to third latch circuits 22, 23 and 24 synchronize the first word data DLi / DRi, the second word data DLi ′ / DRi ′ output via the delay circuit 21, and the LRCK signal. And output from the first output terminal OUT1, the second output terminal OUT2, and the LRCK terminal OUT3, respectively. The first to third latch circuits 22, 23, and 24 receive the BCLK signal, and the first to third latch circuits 22, 23, and 24 use the BCLK signal to perform latch processing for each bit that constitutes data. . In this case, as shown in FIG. 3, the second word data DLi ′ / DRi ′ is output at a timing delayed by one sampling time with respect to the first word data DLi / DRi.

  The inverting circuit 25 inverts the BCLK signal and outputs the inverted signal from the BCLK output terminal OUT4, whereby the first word data DLi / DRi output from the first output terminal OUT1, the second output terminal OUT2, and the LRCK output terminal OUT3, respectively. The timing of the BCLK signal with respect to the second word data DLi ′ / DRi ′ and the LRCK signal is adjusted.

  As described above, in the audio data generation circuit 2, I2S mode digital audio including a DATA signal (digital composite signal) in which L-channel audio data and R-channel audio data are mixed, an LRCK signal, and a BCLK signal. .., DLi / DRi,..., DLi / DRi,..., And second word data strings DL1 ′ / DR1 ′, .., DLi ′ / DRi ′,..., Converted into a digital audio signal composed of a second audio data signal A (−T), an LRCK signal, and a BCLK signal.

  Referring back to FIG. 1, the one-bit DAC 31A of the one-bit DA conversion circuit 3 includes a first word data stream DL1 / DR1, DL2 / DR2,..., DLi / DRi,. Audio data signal A (T), LRCK signal, and BCLK signal are input, respectively. The one-bit DAC 31B includes second word data strings DL1 ′ / DR1 ′, DL2 ′ / DR2 ′,... Delayed from the first audio data signal A (T) by one sampling time from the audio data generation circuit 2. The second audio data signal A (-T), LRCK signal, and BCLK signal composed of DLi ′ / DRi ′,.

  As shown in FIG. 4, the one-bit DAC 31A includes audio data L (T) composed of L channel word data DLi and audio data composed of R channel word data DRi from the first audio data signal A (T). It comprises a digital filter 311 that separates R (T) and DA conversion circuits 312 and 313 that serially convert each audio data L (T) and R (T) into analog signals bit by bit.

  As shown in FIG. 5, the one-bit DAC 31B is a word data DLi ′ that is delayed from the second audio data signal A (-T) by one sampling time from the audio data L (T) composed of the L-channel word data DLi. Is a digital signal that separates audio data L (-T) consisting of word data DRi 'delayed from the audio data R (T) consisting of R channel word data DRi by one sampling time. It comprises a filter 314 and DA conversion circuits 315 and 316 for converting the audio data L (-T) and R (-T) into analog signals serially for each bit.

  Therefore, from the one-bit DAC 31A, the analog signal L (t) obtained by DA-converting the L-channel audio data L (T) by the DA converter circuit 312 and the R-channel audio data R (T) by the DA converter circuit 313 are DA-converted. The converted analog signal R (t) is output. From the one-bit DAC 31B, the analog signal L (-t) obtained by DA-converting the L-channel audio data L (-T) by the DA conversion circuit 315 and the R-channel audio data R (-T) are converted into a DA conversion circuit. The analog signal R (-t) obtained by DA conversion at 316 is output.

  FIG. 6 is a detailed circuit diagram of the audio data generation circuit 2 and the one-bit DA conversion circuit 3. According to the figure, the delay circuit 21 is constituted by a logic IC which is a 64-bit shift register, and the first to third latch circuits 22, 23 and 24 are constituted by a logic IC including three latch circuits, and an inverting circuit. 25 is also constituted by a logic IC. Further, a logic IC as a one-bit DAC 31A and a one-bit DAC 31B is connected to the subsequent stage. Although not shown in FIG. 2, the logic IC indicated by reference numeral 26 is a buffer that is connected to the input terminal IN1 and inputs a DATA signal.

  As described above, the audio data generation circuit 2 including the delay circuit 21, the first to third latch circuits 22, 23, and 24 and the inverting circuit 25 is configured with a general-purpose and inexpensive logic IC as shown in FIG. Therefore, the circuit scale of the audio data generation circuit 2 can be reduced and the cost can be reduced as compared with the conventional SDF conversion circuit using PDL.

  FIG. 7 is a side view of a circuit board on which the audio data generation circuit 2 and the one-bit DA conversion circuit 3 are mounted. The audio data generation circuit 2 and the one-bit DA conversion circuit 3 are configured by a logic IC or the like as shown in FIG. 6, and these logic ICs are mounted on a single printed board 33 as shown in FIG. Yes.

  In this case, the logic IC of the one-bit DAC 31A and the logic IC of the one-bit DAC 31B that constitute the one-bit DA conversion circuit 3 are also mounted on the printed board 33, respectively, but the logic IC that constitutes the one-bit DAC 31A is printed For example, the logic IC that is mounted on the component mounting surface (front surface) 33A side of the substrate 33 and constitutes the one-bit DAC 31B is mounted on the back surface 33B side of the printed circuit board 33.

  Signal lines (pattern lines) connecting the one-bit DAC 31A and the one-bit DAC 31B are arranged in the front and back surfaces 33A and 33B of the printed circuit board 33 and through holes 34 that penetrate the front and back surfaces 33A and 33B. A signal line through which the L-channel analog signal L (t) and the R-channel analog signal R (t) from the one-bit DAC 31A flow is arranged on the surface 33A side of the printed circuit board 33, and the L-line analog signal L (t) from the one-bit DAC 31B A signal line through which the analog signal L (-t) of the channel and the analog signal R (-t) of the R channel flow is arranged on the back surface 33B side of the printed circuit board 33.

  In this way, the logic IC constituting the one-bit DAC 31A and the logic IC constituting the one-bit DAC 31B are separately mounted on the front and back surfaces of the printed circuit board 33, and the L and R channel analog signals L ( t), R (t), and signal lines through which the L and R channel analog signals L (-t) and R (-t) delayed by one sampling time are separately arranged on the front and back surfaces of the printed circuit board 33. Therefore, the influence of the L and R channel analog signals L (t) and R (t) and the L and R channel analog signals L (-t) and R (-t) on each other (for example, crosstalk) Can be suppressed, and the sound quality can be improved.

  Returning to FIG. 1, the L channel analog signal L (t) from the one-bit DAC 31A is input to the ASP circuit 41L. On the other hand, the R channel analog signal R (t) from the one-bit DAC 31A is input to the ASP circuit 41R. The L channel analog signal L (-t) from the one-bit DAC 31B is input to the ASP circuit 41L. On the other hand, the R channel analog signal R (-t) from the one-bit DAC 31B is input to the ASP circuit 41R.

  In other words, the L-channel analog signals L (t) and L (-t) are input to the ASP circuit 41L, and processing related to the L-channel signal is performed. The ASP circuit 41R receives R channel analog signals R (t) and R (-t), and performs processing related to the R channel signal.

  The ASP circuit 41L is an analog signal L (t) obtained by smoothly connecting the sampling values of the L-channel digital signal from the L-channel first analog signal L (t) and the second analog signal L (-t). 'Is generated and output as a DA conversion signal. Further, the ASP circuit 41R is configured to provide an analog signal R () in which each sampling value of the R channel digital signal is smoothly connected from the first analog signal R (t) and the second analog signal R (-t) of the R channel. t) ′ is generated and output as a DA conversion signal.

  That is, the ASP circuit 41L receives the first analog signal L (t) having a stepped waveform and the second analog having a stepped waveform delayed by one sampling time from the analog signal L (t). By converting the level difference (difference voltage) from the signal L (-t) into a current, charging this current to the capacitor, and adding the charging voltage to the signal level of the second analog signal L (-t) As shown in FIG. 8, an analog audio signal L (t) ′ in which the sampling levels are smoothly connected is generated and output as a DA conversion signal. The ASP circuit 41R has the same configuration as the ASP circuit 41L.

  Specifically, the ASP circuit 41L is configured by a circuit shown in FIG. 9, for example. In the ASP circuit 41L, the negative terminal of the operational amplifier OP1 is connected to the input terminal IN1 of the first analog signal L (t) via the resistor r1, and the positive terminal of the operational amplifier OP1 is connected via a series circuit of the capacitor C1 and the resistor r3. The second analog signal L (-t) is connected to the input terminal IN2. The output terminal of the operational amplifier OP1 is connected to the-terminal via the resistor r2, and is connected to the output terminal OUT of the ASP circuit 41L via the resistor r6. A resistor r4 is connected between the + terminal of the operational amplifier OP1 and the ground, and a capacitor C2 is connected between the output terminal OUT and the ground. Further, a series circuit of an operational amplifier OP2 and a resistor r5 is connected between the connection point of the resistor r3 and the capacitor C1 and the output terminal OUT.

  The operational amplifier OP1 operates as a negative feedback differential amplifier, and the operational amplifier OP2 operates as a buffer amplifier when a part of the output signal of the operational amplifier OP1 is fed back to the + terminal of the operational amplifier OP1 through the resistor r5. The capacitor C1 cuts the input to the + terminal of the operational amplifier OP1 at the time of steady state when the first analog signal L (t) and the second analog signal L (-t) are substantially the same, and suppresses the generation of noise. Is. The resistor r6 and the capacitor C2 constitute an integrating circuit SC, which generates a signal integrating the output of the operational amplifier OP1 (difference between the first analog signal L (t) and the second analog signal L (-t)). It is.

  In the above configuration, the first analog signal L (t) at each sampling point and the second analog signal L delayed by one sampling time from the analog signal L (t) are respectively connected to the negative terminal and the positive terminal of the operational amplifier OP1. (-t) is input, and the operational amplifier OP1 converts the voltage of the difference value with respect to the reference voltage of the first analog signal L (t) using the second analog signal L (-t) as a reference voltage to a current. Is output. The capacitor C2 of the integration circuit SC is charged with the time constant C2 · r6 by this current, and the charging voltage of the capacitor C2 is the second analog signal L (− (−) that is next input through the buffer amplifier and resistor r5. added to t).

  Since the change in the charging voltage of the capacitor C2 indicates a voltage vector that connects the level difference between the previous sampling point and the subsequent sampling point in the sampling period, as shown in FIG. When the first analog signal L (t) and the second analog signal L (-t) are input at ti, the output level of the ASP circuit at the sampling point ti is the first analog signal L (ti) or the second analog signal L (t). 2, but during the period of ti <t <ti + 1, the voltage vector connecting the level difference between the output level at the sampling point ti and the output level at the sampling point ti + 1 is the capacitor C2. Generated by the charging voltage. Therefore, the analog signal L (t) 'connecting the voltage levels of the respective sampling points is output from the ASP circuit 41L.

  The ASP circuit 41R has the same configuration as the ASP circuit 41L, and the ASP circuit 41R outputs an analog signal R (t) 'that connects the voltage levels of the respective sampling points.

  As described above, the DA converter 1 according to this embodiment includes the audio data generation circuit 2, the one-bit DA conversion circuit 3, and the ASP circuit 4, and based on the array data of the input digital audio signal, The audio data generation circuit 2 generates first audio data A (T) and second audio data A (-T) delayed by one sampling time from the first audio data A (T).

  The first audio data A (T) is separated into L-channel audio data L (T) and R-channel audio data R (T) by the one-bit DAC 31A and DA-converted to obtain an analog signal L (t). , R (t) are generated. The second audio data A (-T) is separated into L-channel audio data L (-T) and R-channel audio data R (-T) by the one-bit DAC 31B, and is DA-converted to be analog. Signals L (-t) and R (-t) are generated.

  The ASP circuit 41L uses the L channel audio data L (t) and L (-t) to generate and output an L channel analog audio signal connecting the signal levels between the sampling points. The ASP circuit 41R uses the R channel audio data R (t) and R (-t) to generate and output an R channel analog audio signal that connects signal levels between sampling points.

  In the conventional configuration, the input audio data is converted into the L channel audio data L (T) and the R channel audio data R (T) by the SDF conversion circuit 51 corresponding to the audio data generation circuit 2 of the present embodiment. In this embodiment, the L-channel audio data L (T) and the R-channel audio data R (T) are separated by the one-bit DACs 31A and 31B. The circuit 2 obtains first audio data A (T) from the input audio data and second audio data A (-T) delayed by one sampling time from the first audio data A (T). It is composed only of the circuit to be generated, and the circuit configuration can be simplified.

  Specifically, as shown in FIG. 6, the audio data generation circuit 2 can be configured by a general-purpose and inexpensive logic IC, so that the audio data can be compared with the conventional SDF conversion circuit 51 using PDL. The circuit scale of the generation circuit 2 can be reduced, and the cost can be reduced.

  Of course, the scope of the present invention is not limited to the above-described embodiment, and the circuit configuration shown in the above embodiment is an example, and various circuits can be applied as long as they have equivalent functions. Can do. In the above embodiment, the case where the above-described DA converter is configured for both the L channel and the R channel has been described. However, the present invention can be applied to the case where the above-described DA converter is configured for any one of the channels. Can be applied.

  In the above embodiment, the case of the I2S mode has been described as the serial data format of the input digital audio signal. However, the present invention is not limited to this mode. For example, as shown in FIG. 10, a Right-Justified (right justified) mode (FIG. 10 (a)), Left-Justified (left justified) mode (FIG. 10 (b)), Left-Justified DSP mode (FIG. 10 (c)). )), 32 × Fs Packed mode ((d) in the figure), the present invention may be applied.

It is a block block diagram of the DA converter which concerns on this invention. It is a block diagram which shows the circuit structure of an audio data generation circuit. It is a figure which shows the data output by the signal processing based on the LRCK signal in an audio data generation circuit. It is a functional block diagram of a one-bit DAC. It is a functional block diagram of another one-bit DAC. It is a detailed circuit diagram of an audio data generation circuit and a one-bit DA conversion circuit. It is a side view of a circuit board on which an audio data generation circuit and a one-bit DA conversion circuit are mounted. It is a figure which shows the circuit structure of an ASP circuit. It is a wave form diagram for demonstrating the analog signal produced | generated by the analog signal process in an ASP circuit. It is a figure which shows the signal waveform of the digital audio signal transmitted in another mode. It is a block block diagram which shows the structure of the conventional DA converter. It is a figure which shows the signal waveform of the digital audio signal transmitted by I2S mode. It is a block diagram which shows the circuit structure of the conventional SDF conversion circuit.

Explanation of symbols

1 DA converter 2 Audio data generation circuit (audio data generation means)
3 One-bit DA conversion circuit (one-bit DA conversion means)
4 Analog signal processing circuit (analog signal processing means)
21 delay circuit 22 first latch circuit 23 second latch circuit 24 third latch circuit 25 inverting circuit 31A one-bit DAC
31B One-bit DAC
41L ASP circuit for L channel 41R ASP circuit for R channel IN1, IN2, IN3 Input terminal OUT1, OUT2, OUT3, OUT4 Output terminal

Claims (4)

Array data obtained by alternately arranging L-channel audio data and R-channel audio data serially in word units, a word clock for identifying the word data of the array data, and bit data of the array data Audio data generating means for inputting a digital audio signal composed of a bit clock for identification and generating second audio data obtained by delaying the first audio data as the input array data by one sampling time When,
The first audio data from the audio data generating means is separated into L-channel first audio data and R-channel first audio data, and the L-channel first audio data is bit-converted using the bit clock. DA is serially converted every time to generate a first analog signal, and the R channel first audio data is serially DA converted to each bit using the bit clock to generate a second analog signal. First one-bit DA conversion means;
The second audio data from the audio data generating means is separated into L channel second audio data and R channel second audio data, and the L channel second audio data is bit-bited using the bit clock. Each time DA is serially converted to generate a third analog signal, and the second audio data of the R channel is serially DA converted bit by bit using the bit clock to generate a fourth analog signal. Second one-bit DA conversion means;
The signal level between the sampling points is connected using the first analog signal generated by the first one-bit DA converter and the third analog signal generated by the second one-bit DA converter. First analog signal processing means for generating an analog signal and outputting it as an L channel analog audio signal;
The signal level between the sampling points is connected using the second analog signal generated by the first one-bit DA converter and the fourth analog signal generated by the second one-bit DA converter. Second analog signal processing means for generating an analog signal and outputting it as an R channel analog audio signal;
A DA converter characterized by comprising:   2. The DA converter according to claim 1, wherein the audio data generation unit includes a delay circuit that generates the second audio data by delaying the array data by one period of the word clock.   The DA converter according to claim 2, wherein the delay circuit includes a shift register. Each of the first one-bit DA conversion means and the second one-bit DA conversion means is constituted by one integrated circuit mounted on one substrate,
The integrated circuit constituting the first one-bit DA conversion means is mounted on one surface of the substrate, and the integrated circuit constituting the second one-bit DA conversion means is the other one of the substrates. The DA converter according to claim 1, wherein the DA converter is mounted on the surface.

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